MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
Signed-off-by: Michal Simek <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..7b077af62b27 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -32,6 +32,7 @@ properties:
oneOf:
- items:
- enum:
+ - amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
--
2.36.1
Hi Conor,
On 11/6/23 12:37, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> Signed-off-by: Michal Simek <[email protected]>
> ---
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..7b077af62b27 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -32,6 +32,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - amd,mbv32
> - andestech,ax45mp
> - canaan,k210
> - sifive,bullet0
Can you please queue this patch to your tree?
Thanks,
Michal
On Thu, 09 Nov 2023 09:15:09 PST (-0800), Conor Dooley wrote:
> On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote:
>> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
>> It is hardware compatible with classic MicroBlaze processor.
>>
>> Signed-off-by: Michal Simek <[email protected]>
>
> Acked-by: Conor Dooley <[email protected]>
> I thought I had already done so, but must have forgot to actually send
> the email.
Conor asked me to pick it up, it's over staged for testing. Pretty much
no chance it fails anything, so should show up on for-next soon.
>
> Cheers,
> Conor.
>
>> ---
>>
>> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> index 97e8441eda1c..7b077af62b27 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> @@ -32,6 +32,7 @@ properties:
>> oneOf:
>> - items:
>> - enum:
>> + - amd,mbv32
>> - andestech,ax45mp
>> - canaan,k210
>> - sifive,bullet0
>> --
>> 2.36.1
>>
On 12/20/23 16:15, Palmer Dabbelt wrote:
> On Thu, 09 Nov 2023 09:15:09 PST (-0800), Conor Dooley wrote:
>> On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote:
>>> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
>>> It is hardware compatible with classic MicroBlaze processor.
>>>
>>> Signed-off-by: Michal Simek <[email protected]>
>>
>> Acked-by: Conor Dooley <[email protected]>
>> I thought I had already done so, but must have forgot to actually send
>> the email.
>
> Conor asked me to pick it up, it's over staged for testing. Pretty much
> no chance it fails anything, so should show up on for-next soon.
Palmer: Any update on this?
Thanks,
Michal
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Mon, 6 Nov 2023 12:37:47 +0100 you wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> Signed-off-by: Michal Simek <[email protected]>
> ---
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
Here is the summary with links:
- dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible
https://git.kernel.org/riscv/c/4a6b93f56296
You are awesome, thank you!
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