On Mon, 29 Jan 2024 01:25:43 PST (-0800), [email protected] wrote:
> Hi All,
>
> This patch series introduces the Andes PMU extension, which serves the
> same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
> is assigned to bit 18 in the custom S-mode local interrupt enable and
> pending registers (slie/slip), while the interrupt cause is (256 + 18).
>
> Linux patches based on:
> - ed5b7cf ("riscv: errata: andes: Probe for IOCP only once in boot stage")
> It can be found on Andes Technology GitHub:
> - https://github.com/andestech/linux/commits/andes-pmu-support-v8
>
> The PMU device tree node used on AX45MP:
> - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3
>
> Locus Wei-Han Chen (1):
> riscv: andes: Support specifying symbolic firmware and hardware raw
> events
>
> Yu Chien Peter Lin (9):
> riscv: errata: Rename defines for Andes
> irqchip/riscv-intc: Allow large non-standard interrupt number
> irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
> dt-bindings: riscv: Add Andes interrupt controller compatible string
> riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
> INTC
> perf: RISC-V: Eliminate redundant interrupt enable/disable operations
> perf: RISC-V: Introduce Andes PMU to support perf event sampling
> dt-bindings: riscv: Add Andes PMU extension description
> riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
>
> .../devicetree/bindings/riscv/cpus.yaml | 6 +-
> .../devicetree/bindings/riscv/extensions.yaml | 7 +
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +-
> arch/riscv/errata/andes/errata.c | 10 +-
> arch/riscv/include/asm/errata_list.h | 13 +-
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/asm/vendorid_list.h | 2 +-
> arch/riscv/kernel/alternative.c | 2 +-
> arch/riscv/kernel/cpufeature.c | 1 +
> drivers/irqchip/irq-riscv-intc.c | 88 ++++++++++--
> drivers/perf/Kconfig | 14 ++
> drivers/perf/riscv_pmu_sbi.c | 37 ++++-
> include/linux/soc/andes/irq.h | 18 +++
> .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
> .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
> .../arch/riscv/andes/ax45/memory.json | 57 ++++++++
> .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> 18 files changed, 494 insertions(+), 39 deletions(-)
> create mode 100644 include/linux/soc/andes/irq.h
> create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
Acked-by: Palmer Dabbelt <[email protected]>
in case someone wants to take this via another tree. I'm also OK taking
it via the RISC-V tree, pending a resolution to Thomas' comments on
patch 2. For now I'm going to assume there's a v9 coming.
Thanks!
Hi Palmer,
On Wed, Feb 21, 2024 at 12:58:31PM -0800, Palmer Dabbelt wrote:
> On Mon, 29 Jan 2024 01:25:43 PST (-0800), [email protected] wrote:
> > Hi All,
> >
> > This patch series introduces the Andes PMU extension, which serves the
> > same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
> > is assigned to bit 18 in the custom S-mode local interrupt enable and
> > pending registers (slie/slip), while the interrupt cause is (256 + 18).
> >
> > Linux patches based on:
> > - ed5b7cf ("riscv: errata: andes: Probe for IOCP only once in boot stage")
> > It can be found on Andes Technology GitHub:
> > - https://github.com/andestech/linux/commits/andes-pmu-support-v8
> >
> > The PMU device tree node used on AX45MP:
> > - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3
> >
> > Locus Wei-Han Chen (1):
> > riscv: andes: Support specifying symbolic firmware and hardware raw
> > events
> >
> > Yu Chien Peter Lin (9):
> > riscv: errata: Rename defines for Andes
> > irqchip/riscv-intc: Allow large non-standard interrupt number
> > irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
> > dt-bindings: riscv: Add Andes interrupt controller compatible string
> > riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
> > INTC
> > perf: RISC-V: Eliminate redundant interrupt enable/disable operations
> > perf: RISC-V: Introduce Andes PMU to support perf event sampling
> > dt-bindings: riscv: Add Andes PMU extension description
> > riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
> >
> > .../devicetree/bindings/riscv/cpus.yaml | 6 +-
> > .../devicetree/bindings/riscv/extensions.yaml | 7 +
> > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +-
> > arch/riscv/errata/andes/errata.c | 10 +-
> > arch/riscv/include/asm/errata_list.h | 13 +-
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/include/asm/vendorid_list.h | 2 +-
> > arch/riscv/kernel/alternative.c | 2 +-
> > arch/riscv/kernel/cpufeature.c | 1 +
> > drivers/irqchip/irq-riscv-intc.c | 88 ++++++++++--
> > drivers/perf/Kconfig | 14 ++
> > drivers/perf/riscv_pmu_sbi.c | 37 ++++-
> > include/linux/soc/andes/irq.h | 18 +++
> > .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
> > .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
> > .../arch/riscv/andes/ax45/memory.json | 57 ++++++++
> > .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
> > tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> > 18 files changed, 494 insertions(+), 39 deletions(-)
> > create mode 100644 include/linux/soc/andes/irq.h
> > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
> > create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
>
> Acked-by: Palmer Dabbelt <[email protected]>
>
> in case someone wants to take this via another tree. I'm also OK taking it
> via the RISC-V tree, pending a resolution to Thomas' comments on patch 2.
> For now I'm going to assume there's a v9 coming.
Yes, I'm working on v9, please hold off taking the series, thanks.
Regards,
Peter Lin
> Thanks!