After allowing case-insensitive ISA string parsing in the kernel code,
the docs should be updated.
Signed-off-by: Yangyu Chen <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 001931d526ec..70afd1e8638b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -79,11 +79,10 @@ properties:
User-Level ISA document, available from
https://riscv.org/specifications/
- While the isa strings in ISA specification are case
- insensitive, letters in the riscv,isa string must be all
- lowercase to simplify parsing.
+ According to RISC-V ISA specification, the isa strings are
+ case insensitive.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ pattern: (?i)^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.40.0