2011-02-09 08:26:19

by Jan Beulich

Subject: [PATCH] x86: adjust section placement in AMD northbridge related code

amd_nb_misc_ids[] can live in .rodata, and enable_pci_io_ecs() can be
moved into .cpuinit.text.

Signed-off-by: Jan Beulich <[email protected]>

---
arch/x86/include/asm/amd_nb.h | 2 +-
arch/x86/kernel/amd_nb.c | 7 ++++---
arch/x86/pci/amd_bus.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)

--- 2.6.38-rc4/arch/x86/include/asm/amd_nb.h
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/include/asm/amd_nb.h
@@ -9,7 +9,7 @@ struct amd_nb_bus_dev_range {
u8 dev_limit;
};

-extern struct pci_device_id amd_nb_misc_ids[];
+extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
struct bootnode;

--- 2.6.38-rc4/arch/x86/kernel/amd_nb.c
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/kernel/amd_nb.c
@@ -12,7 +12,7 @@

static u32 *flush_words;

-struct pci_device_id amd_nb_misc_ids[] = {
+const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
@@ -31,7 +31,7 @@ struct amd_northbridge_info amd_northbri
EXPORT_SYMBOL(amd_northbridges);

static struct pci_dev *next_northbridge(struct pci_dev *dev,
- struct pci_device_id *ids)
+ const struct pci_device_id *ids)
{
do {
dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
@@ -93,8 +93,9 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges
they're useless anyways */
int __init early_is_amd_nb(u32 device)
{
- struct pci_device_id *id;
+ const struct pci_device_id *id;
u32 vendor = device & 0xffff;
+
device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device)
--- 2.6.38-rc4/arch/x86/pci/amd_bus.c
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/pci/amd_bus.c
@@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info

#define ENABLE_CF8_EXT_CFG (1ULL << 46)

-static void enable_pci_io_ecs(void *unused)
+static void __cpuinit enable_pci_io_ecs(void *unused)
{
u64 reg;
rdmsrl(MSR_AMD64_NB_CFG, reg);

2011-02-10 14:44:43

by Jan Beulich

Subject: [tip:x86/amd-nb] x86: Adjust section placement in AMD northbridge related code

Commit-ID: 691269f0d918cd72454c254f97722f194c07b9a8
Gitweb: http://git.kernel.org/tip/691269f0d918cd72454c254f97722f194c07b9a8
Author: Jan Beulich <[email protected]>
AuthorDate: Wed, 9 Feb 2011 08:26:53 +0000
Committer: Ingo Molnar <[email protected]>
CommitDate: Thu, 10 Feb 2011 13:32:52 +0100

x86: Adjust section placement in AMD northbridge related code

amd_nb_misc_ids[] can live in .rodata, and enable_pci_io_ecs()
can be moved into .cpuinit.text.

Signed-off-by: Jan Beulich <[email protected]>
Cc: Hans Rosenfeld <[email protected]>
Cc: Andreas Herrmann <[email protected]>
Cc: Borislav Petkov <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/include/asm/amd_nb.h | 2 +-
arch/x86/kernel/amd_nb.c | 7 ++++---
arch/x86/pci/amd_bus.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 423f11c..2b33c4d 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -9,7 +9,7 @@ struct amd_nb_bus_dev_range {
u8 dev_limit;
};

-extern struct pci_device_id amd_nb_misc_ids[];
+extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
struct bootnode;

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index bf79a4a..ed3c2e5 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -12,7 +12,7 @@

static u32 *flush_words;

-struct pci_device_id amd_nb_misc_ids[] = {
+const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
@@ -36,7 +36,7 @@ struct amd_northbridge_info amd_northbridges;
EXPORT_SYMBOL(amd_northbridges);

static struct pci_dev *next_northbridge(struct pci_dev *dev,
- struct pci_device_id *ids)
+ const struct pci_device_id *ids)
{
do {
dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
@@ -107,8 +107,9 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges);
they're useless anyways */
int __init early_is_amd_nb(u32 device)
{
- struct pci_device_id *id;
+ const struct pci_device_id *id;
u32 vendor = device & 0xffff;
+
device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device)
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index e27dffb..026e493 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info(void)

#define ENABLE_CF8_EXT_CFG (1ULL << 46)

-static void enable_pci_io_ecs(void *unused)
+static void __cpuinit enable_pci_io_ecs(void *unused)
{
u64 reg;
rdmsrl(MSR_AMD64_NB_CFG, reg);