2015-04-02 15:24:17

by Liang, Kan

Subject: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

From: Kan Liang <[email protected]>

Same as Haswell, Broadwell also support LBR callstack.

Signed-off-by: Kan Liang <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index fc6dbc4..4b61fe9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;

- intel_pmu_lbr_init_snb();
+ intel_pmu_lbr_init_hsw();

x86_pmu.event_constraints = intel_bdw_event_constraints;
x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
--
1.8.3.1

2015-04-02 19:46:00

by Andi Kleen

Subject: Re: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

On Thu, Apr 02, 2015 at 04:12:57AM -0400, [email protected] wrote:
> From: Kan Liang <[email protected]>
>
> Same as Haswell, Broadwell also support LBR callstack.
>
> Signed-off-by: Kan Liang <[email protected]>

Thanks looks good.

Acked-by: Andi Kleen <[email protected]>

-Andi


> ---
> arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index fc6dbc4..4b61fe9 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
> hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
> BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
>
> - intel_pmu_lbr_init_snb();
> + intel_pmu_lbr_init_hsw();
>
> x86_pmu.event_constraints = intel_bdw_event_constraints;
> x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
> --
> 1.8.3.1
>

--
[email protected] -- Speaking for myself only

2015-04-18 10:14:59

by tip-bot for Vasyl Gomonovych

Subject: [tip:perf/urgent] perf/x86/intel: Add Broadwell support for the LBR callstack

Commit-ID: 78d504bcd769cc496f63b626f507039eab2316b7
Gitweb: http://git.kernel.org/tip/78d504bcd769cc496f63b626f507039eab2316b7
Author: Kan Liang <[email protected]>
AuthorDate: Thu, 2 Apr 2015 04:12:57 -0400
Committer: Ingo Molnar <[email protected]>
CommitDate: Fri, 17 Apr 2015 09:59:07 +0200

perf/x86/intel: Add Broadwell support for the LBR callstack

Same as Haswell, Broadwell also support the LBR callstack.

Signed-off-by: Kan Liang <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Acked-by: Andi Kleen <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 9da2400..219d3fb 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -3275,7 +3275,7 @@ __init int intel_pmu_init(void)
hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;

- intel_pmu_lbr_init_snb();
+ intel_pmu_lbr_init_hsw();

x86_pmu.event_constraints = intel_bdw_event_constraints;
x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;