This patch series provide support for display subsystem, gpu
and also adds wireless connectivity subsystem support.
Adam Skladowski (8):
arm64: dts: qcom: msm8976: Add IOMMU nodes
dt-bindings: dsi-controller-main: Document missing msm8976 compatible
dt-bindings: msm: qcom,mdss: Include ommited fam-b compatible
arm64: dts: qcom: msm8976: Add MDSS nodes
dt-bindings: drm/msm/gpu: Document AON clock for A506/A510
arm64: dts: qcom: msm8976: Add Adreno GPU
arm64: dts: qcom: msm8976: Declare and wire SDC pins
arm64: dts: qcom: msm8976: Add WCNSS node
.../display/msm/dsi-controller-main.yaml | 2 +
.../devicetree/bindings/display/msm/gpu.yaml | 6 +-
.../bindings/display/msm/qcom,mdss.yaml | 1 +
arch/arm64/boot/dts/qcom/msm8976.dtsi | 610 +++++++++++++++++-
4 files changed, 613 insertions(+), 6 deletions(-)
--
2.43.0
During conversion 28nm-hpm-fam-b compat got lost, add it.
Signed-off-by: Adam Skladowski <[email protected]>
---
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
index 0999ea07f47b..e4576546bf0d 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
@@ -127,6 +127,7 @@ patternProperties:
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-8226
- qcom,dsi-phy-28nm-hpm
+ - qcom,dsi-phy-28nm-hpm-fam-b
- qcom,dsi-phy-28nm-lp
- qcom,hdmi-phy-8084
- qcom,hdmi-phy-8660
--
2.43.0
Add MDSS nodes to support displays on MSM8976 SoC.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 268 +++++++++++++++++++++++++-
1 file changed, 264 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 118174cfd4d3..2d71ce34f00e 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -785,10 +785,10 @@ gcc: clock-controller@1800000 {
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&mdss_dsi1_phy 0>;
clock-names = "xo",
"xo_a",
"dsi0pll",
@@ -808,6 +808,266 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x30000>;
};
+ mdss: display-subsystem@1a00000 {
+ compatible = "qcom,mdss";
+
+ reg = <0x01a00000 0x1000>,
+ <0x01ab0000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ power-domains = <&gcc MDSS_GDSC>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync",
+ "core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@1a01000 {
+ compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
+ reg = <0x01a01000 0x89000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDP_TBU_CLK>,
+ <&gcc GCC_MDP_RT_TBU_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync",
+ "tbu",
+ "tbu_rt";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&gcc MDSS_GDSC>;
+
+ iommus = <&apps_iommu 22>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_mdp5_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_mdp5_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-177780000 {
+ opp-hz = /bits/ 64 <177780000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@1a94000 {
+ compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x01a94000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE0_CLK>,
+ <&gcc GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
+ <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&gcc MDSS_GDSC>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ required-opps = <&rpmpd_opp_svs>;
+
+ };
+
+ opp-161250000 {
+ opp-hz = /bits/ 64 <161250000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi1: dsi@1a96000 {
+ compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x01a96000 0x300>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE1_CLK>,
+ <&gcc GCC_MDSS_PCLK1_CLK>,
+ <&gcc GCC_MDSS_ESC1_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
+ <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&mdss_mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@1a94a00 {
+ compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
+ reg = <0x01a94a00 0xd4>,
+ <0x01a94400 0x280>,
+ <0x01a94b80 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1_phy: phy@1a96a00 {
+ compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
+ reg = <0x01a96a00 0xd4>,
+ <0x01a96400 0x280>,
+ <0x01a96b80 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
ranges = <0 0x01e20000 0x20000>;
--
2.43.0
Adreno 506(MSM8953) and Adreno 510(MSM8976) require
Always-on branch clock to be enabled, describe it.
Signed-off-by: Adam Skladowski <[email protected]>
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index b019db954793..9e36f54a5caf 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -133,7 +133,7 @@ allOf:
properties:
clocks:
minItems: 2
- maxItems: 7
+ maxItems: 8
clock-names:
items:
@@ -148,6 +148,8 @@ allOf:
description: GPU Memory Interface clock
- const: alt_mem_iface
description: GPU Alternative Memory Interface clock
+ - const: alwayson
+ description: GPU Always-On clock
- const: gfx3d
description: GPU 3D engine clock
- const: rbbmtimer
@@ -155,7 +157,7 @@ allOf:
- const: rbcpr
description: GPU RB Core Power Reduction clock
minItems: 2
- maxItems: 7
+ maxItems: 8
required:
- clocks
--
2.43.0
Add Adreno GPU node.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 66 +++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 2d71ce34f00e..765c90ac14cb 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -1068,6 +1068,72 @@ mdss_dsi1_phy: phy@1a96a00 {
};
};
+ adreno_gpu: gpu@1c00000 {
+ compatible = "qcom,adreno-510.0", "qcom,adreno";
+
+ reg = <0x01c00000 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clock-names = "core",
+ "iface",
+ "mem",
+ "mem_iface",
+ "rbbmtimer",
+ "alwayson";
+
+ clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
+ <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
+ <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
+ <&gcc GCC_GFX3D_BIMC_CLK>,
+ <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
+ <&gcc GCC_GFX3D_OXILI_AON_CLK>;
+
+ power-domains = <&rpmpd MSM8976_VDDCX>;
+
+ iommus = <&gpu_iommu 0>;
+
+ status = "disabled";
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp-table {
+ compatible ="operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ opp-supported-hw = <0xff>;
+ };
+ };
+ };
+
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
ranges = <0 0x01e20000 0x20000>;
--
2.43.0
Declare pinctrls for SDC pins and wire them to consumers.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 100 ++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 765c90ac14cb..5a7be93a0115 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -771,6 +771,96 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
drive-strength = <2>;
bias-disable;
};
+
+ sdc1_default: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_sleep: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
gcc: clock-controller@1800000 {
@@ -1246,6 +1336,11 @@ sdhc_1: mmc@7824900 {
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
+
+ pinctrl-0 = <&sdc1_default>;
+ pinctrl-1 = <&sdc1_sleep>;
+ pinctrl-names = "default", "sleep";
+
status = "disabled";
};
@@ -1262,6 +1357,11 @@ sdhc_2: mmc@7864900 {
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
+
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
+
status = "disabled";
};
--
2.43.0
Add node describing wireless connectivity subsystem.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 5a7be93a0115..73ddfaecd3ad 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -861,6 +861,36 @@ data-pins {
bias-pull-up;
};
};
+
+ wcss_wlan_default: wcss-wlan-default-state {
+ wcss_wlan2-pins {
+ pins = "gpio40";
+ function = "wcss_wlan2";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss_wlan1-pins {
+ pins = "gpio41";
+ function = "wcss_wlan1";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss_wlan0-pins {
+ pins = "gpio42";
+ function = "wcss_wlan0";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss_wlan-pins {
+ pins = "gpio43", "gpio44";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
};
gcc: clock-controller@1800000 {
@@ -1540,6 +1570,72 @@ blsp2_i2c4: i2c@7af8000 {
status = "disabled";
};
+ wcnss: remoteproc@a204000 {
+ compatible = "qcom,pronto-v3-pil", "qcom,pronto";
+ reg = <0xa204000 0x2000>, <0xa202000 0x1000>, <0xa21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ memory-region = <&wcnss_fw_mem>;
+
+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ power-domains = <&rpmpd MSM8976_VDDCX>,
+ <&rpmpd MSM8976_VDDMX>;
+ power-domain-names = "cx", "mx";
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcss_wlan_default>;
+
+ status = "disabled";
+
+ wcnss_iris: iris {
+ /* Separate chip, compatible is board-specific */
+ clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+ clock-names = "xo";
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss_ctrl: wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&wcnss>;
+
+ wcnss_bt: bluetooth {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wcnss_wifi: wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable",
+ "tx-rings-empty";
+ };
+ };
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
--
2.43.0
On 2024-01-21 20:41:05, Adam Skladowski wrote:
> Declare pinctrls for SDC pins and wire them to consumers.
>
> Signed-off-by: Adam Skladowski <[email protected]>
Where'd the original sign-offs go?
https://lore.kernel.org/linux-arm-msm/[email protected]/
Thanks taking taking care of this SoC though. My SM8976 Suzu device finally
emitted the magic smoke after rebasing on the latest MSM8976 patches, and will
need board repairs or a replacement before patches can be tested again :(
- Marijn
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 100 ++++++++++++++++++++++++++
> 1 file changed, 100 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 765c90ac14cb..5a7be93a0115 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -771,6 +771,96 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
> drive-strength = <2>;
> bias-disable;
> };
> +
> + sdc1_default: sdc1-default-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_sleep: sdc1-sleep-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc2_default: sdc2-default-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> + };
> +
> + sdc2_sleep: sdc2-sleep-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> };
>
> gcc: clock-controller@1800000 {
> @@ -1246,6 +1336,11 @@ sdhc_1: mmc@7824900 {
> <&gcc GCC_SDCC1_APPS_CLK>,
> <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "core", "xo";
> +
> + pinctrl-0 = <&sdc1_default>;
> + pinctrl-1 = <&sdc1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> status = "disabled";
> };
>
> @@ -1262,6 +1357,11 @@ sdhc_2: mmc@7864900 {
> <&gcc GCC_SDCC2_APPS_CLK>,
> <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "core", "xo";
> +
> + pinctrl-0 = <&sdc2_default>;
> + pinctrl-1 = <&sdc2_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> status = "disabled";
> };
>
> --
> 2.43.0
>
On 21/01/2024 20:41, Adam Skladowski wrote:
> During conversion 28nm-hpm-fam-b compat got lost, add it.
Please add Fixes tag and put this commit as first in your patchset or
even as separate one.
Best regards,
Krzysztof
On 21/01/2024 20:41, Adam Skladowski wrote:
> Adreno 506(MSM8953) and Adreno 510(MSM8976) require
> Always-on branch clock to be enabled, describe it.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index b019db954793..9e36f54a5caf 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -133,7 +133,7 @@ allOf:
> properties:
> clocks:
> minItems: 2
> - maxItems: 7
> + maxItems: 8
I would prefer we start enforcing the order. The initial flexibility was
because of conversion from the old bindings and dealing with some
technical debt, AFAIU.
This is requirement of new clock, so maybe better add dedicated if:then
case which will be enforcing the order with always-on at the end.
Best regards,
Krzysztof
On Mon, 22 Jan 2024 at 10:48, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 21/01/2024 20:41, Adam Skladowski wrote:
> > During conversion 28nm-hpm-fam-b compat got lost, add it.
>
> Please add Fixes tag and put this commit as first in your patchset or
> even as separate one.
Fixes: f7d46c5efee2 ("dt-bindings: display/msm: split qcom, mdss bindings")
Krzysztof, if that was the only issue, could you please ack this
patch, I can then merge it
--
With best wishes
Dmitry
On 21/01/2024 20:41, Adam Skladowski wrote:
> During conversion 28nm-hpm-fam-b compat got lost, add it.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add MDSS nodes to support displays on MSM8976 SoC.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 268 +++++++++++++++++++++++++-
> 1 file changed, 264 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 118174cfd4d3..2d71ce34f00e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -785,10 +785,10 @@ gcc: clock-controller@1800000 {
>
> clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
> - <0>,
> - <0>,
> - <0>,
> - <0>;
> + <&mdss_dsi0_phy 1>,
> + <&mdss_dsi0_phy 0>,
> + <&mdss_dsi1_phy 1>,
> + <&mdss_dsi1_phy 0>;
> clock-names = "xo",
> "xo_a",
> "dsi0pll",
> @@ -808,6 +808,266 @@ tcsr: syscon@1937000 {
> reg = <0x01937000 0x30000>;
> };
>
> + mdss: display-subsystem@1a00000 {
> + compatible = "qcom,mdss";
> +
> + reg = <0x01a00000 0x1000>,
> + <0x01ab0000 0x3000>;
> + reg-names = "mdss_phys", "vbif_phys";
> +
> + power-domains = <&gcc MDSS_GDSC>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + clocks = <&gcc GCC_MDSS_AHB_CLK>,
> + <&gcc GCC_MDSS_AXI_CLK>,
> + <&gcc GCC_MDSS_VSYNC_CLK>,
> + <&gcc GCC_MDSS_MDP_CLK>;
The last entry is misaligned
[...]
> + port@0 {
> + reg = <0>;
Please add a newline between properties and subnodes
And then the rest looks good, I think!
Konrad
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add Adreno GPU node.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 66 +++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 2d71ce34f00e..765c90ac14cb 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -1068,6 +1068,72 @@ mdss_dsi1_phy: phy@1a96a00 {
> };
> };
>
> + adreno_gpu: gpu@1c00000 {
> + compatible = "qcom,adreno-510.0", "qcom,adreno";
> +
> + reg = <0x01c00000 0x40000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "kgsl_3d0_irq";
> +
> + clock-names = "core",
> + "iface",
> + "mem",
> + "mem_iface",
> + "rbbmtimer",
> + "alwayson";
> +
> + clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
> + <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
> + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
> + <&gcc GCC_GFX3D_BIMC_CLK>,
> + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
> + <&gcc GCC_GFX3D_OXILI_AON_CLK>;
The entries are misaligned
property
property-names
(and without a separating newline, please)
> +
> + power-domains = <&rpmpd MSM8976_VDDCX>;
> +
> + iommus = <&gpu_iommu 0>;
> +
> + status = "disabled";
> +
> + operating-points-v2 = <&gpu_opp_table>;
> +
> + gpu_opp_table: opp-table {
> + compatible ="operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
A random downstream I took has:
19.2 MHz
266.6 MHz
300.0 MHz
432.0 MHz
480.0 MHz
550.0 MHz
600.0 MHz
> + opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
you want required-opps here instead
Konrad
On 21.01.2024 20:41, Adam Skladowski wrote:
> Add node describing wireless connectivity subsystem.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 96 +++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 5a7be93a0115..73ddfaecd3ad 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -861,6 +861,36 @@ data-pins {
> bias-pull-up;
> };
> };
> +
> + wcss_wlan_default: wcss-wlan-default-state {
> + wcss_wlan2-pins {
No underscores in node names
> + pins = "gpio40";
> + function = "wcss_wlan2";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss_wlan1-pins {
> + pins = "gpio41";
> + function = "wcss_wlan1";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss_wlan0-pins {
> + pins = "gpio42";
> + function = "wcss_wlan0";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss_wlan-pins {
> + pins = "gpio43", "gpio44";
> + function = "wcss_wlan";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> + };
> };
>
> gcc: clock-controller@1800000 {
> @@ -1540,6 +1570,72 @@ blsp2_i2c4: i2c@7af8000 {
> status = "disabled";
> };
>
> + wcnss: remoteproc@a204000 {
> + compatible = "qcom,pronto-v3-pil", "qcom,pronto";
> + reg = <0xa204000 0x2000>, <0xa202000 0x1000>, <0xa21b000 0x3000>;
> + reg-names = "ccu", "dxe", "pmu";
One a line, please
> +
> + memory-region = <&wcnss_fw_mem>;
> +
> + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
And here too
> +
> + power-domains = <&rpmpd MSM8976_VDDCX>,
> + <&rpmpd MSM8976_VDDMX>;
> + power-domain-names = "cx", "mx";
> +
> + qcom,smem-states = <&wcnss_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&wcss_wlan_default>;
rev order
Konrad
On Sun, 21 Jan 2024 20:40:58 +0100, Adam Skladowski wrote:
> This patch series provide support for display subsystem, gpu
> and also adds wireless connectivity subsystem support.
>
> Adam Skladowski (8):
> arm64: dts: qcom: msm8976: Add IOMMU nodes
> dt-bindings: dsi-controller-main: Document missing msm8976 compatible
> dt-bindings: msm: qcom,mdss: Include ommited fam-b compatible
> arm64: dts: qcom: msm8976: Add MDSS nodes
> dt-bindings: drm/msm/gpu: Document AON clock for A506/A510
> arm64: dts: qcom: msm8976: Add Adreno GPU
> arm64: dts: qcom: msm8976: Declare and wire SDC pins
> arm64: dts: qcom: msm8976: Add WCNSS node
>
> [...]
Applied, thanks!
[2/8] dt-bindings: dsi-controller-main: Document missing msm8976 compatible
https://gitlab.freedesktop.org/lumag/msm/-/commit/db36595c6889
[3/8] dt-bindings: msm: qcom,mdss: Include ommited fam-b compatible
https://gitlab.freedesktop.org/lumag/msm/-/commit/3b63880de42b
Best regards,
--
Dmitry Baryshkov <[email protected]>