Bring up the SM6125 DPU now that all preliminary series (such as INTF
TE) have been merged (for me to test the hardware properly), and most
other conflicting work (barring ongoing catalog *improvements*) has made
its way in as well or is still being discussed.
The second part of the series complements that by immediately utilizing
this hardware in DT, and even enabling the MDSS/DSI nodes complete with
a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II).
The last patch ("sm6125-seine: Configure MDSS, DSI and panel") depends
on (an impending v2 of) my Sony panel collection series [1].
[1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
---
Changes in v2:
- Moved dispcc DT clock reordering to the right patch (--fixup on the
wrong hash) (Dmitry, Konrad multiple times);
- Drop removal of GCC_DISP_AHB_CLK in dispcc bindings. While it is
unused in the current driver, it is likely used to ensure a guaranteed
probe order between GCC and DISPCC downstream, as well as currently
relying on the fact that GCC_DISP_AHB_CLK is CLK_IS_CRITICAL and never
turned off (Bjorn);
- Add GCC_DISP_GPLL0_DIV_CLK_SRC at the end of the dispcc clock list to
maintain some form of ABI stability (Krzysztof);
- Use SoC-prefix format for 14nm DSI PHY qcom,sm6125-dsi-phy-14nm
compatible (Dmitry, Krzysztof);
- Add patch to drop unused regulators from QCM2290 14nm DSI PHY (Konrad,
Dmitry);
- Reuse QCM2290 14nm DSI PHY config struct for SM6125 compatible
(Konrad);
- s/sde/mdss in pdx201.dts pinctrl node names and labels (Konrad);
- Use MX power domain in DSI PHY with SVS OPP (Dmitry);
- Use CX power domain with (already-existing) OPP table in DSI CTRL
(Konrad, Dmitry);
- Rebased on top of DPU catalog rework [1] by inlining macro
invocations, and validated by diffing stripped dpu_hw_catalog.o that
there are no unexpected changes;
- Unset min_llcc_ib because this platform has no LLCC (Konrad);
- Fix UBWC comment to mention "encoding" version (Dmitry);
- Reordered DT nodes to follow Konrad's requested sorting;
- Add power-domains and required-opps properties to dsi-phy-14nm.yaml;
- Link to v1: https://lore.kernel.org/r/[email protected]
The discussions and this list ran quite long, apologies if I missed or
mis-resolved anything in advance!
[1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
---
Marijn Suijten (15):
drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config
arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg
dt-bindings: clock: qcom,dispcc-sm6125: Require GCC PLL0 DIV clock
dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property
dt-bindings: display/msm: dsi-controller-main: Document SM6125
dt-bindings: display/msm: sc7180-dpu: Describe SM6125
dt-bindings: display/msm: Add SM6125 MDSS
drm/msm/dpu: Add SM6125 support
drm/msm/mdss: Add SM6125 support
dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant
drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125
arm64: dts: qcom: sm6125: Switch fixed xo_board clock to RPM XO clock
arm64: dts: qcom: sm6125: Add dispcc node
arm64: dts: qcom: sm6125: Add display hardware nodes
arm64: dts: qcom: sm6125-seine: Configure MDSS, DSI and panel
.../bindings/clock/qcom,dispcc-sm6125.yaml | 15 +-
.../bindings/display/msm/dsi-controller-main.yaml | 2 +
.../bindings/display/msm/dsi-phy-14nm.yaml | 11 +
.../bindings/display/msm/qcom,sc7180-dpu.yaml | 14 ++
.../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 ++++++++++++++++++
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 +++++
arch/arm64/boot/dts/qcom/sm6125.dtsi | 251 +++++++++++++++++++--
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -
drivers/gpu/drm/msm/msm_mdss.c | 8 +
14 files changed, 796 insertions(+), 23 deletions(-)
---
base-commit: e42c42a03fdf31deccaea2f44885dd6f8150eb32
change-id: 20230624-sm6125-dpu-aedc9637ee7b
Best regards,
--
Marijn Suijten <[email protected]>
The regulator setup was likely copied from other SoCs by mistake. Just
like SM6125 the DSI PHY on this platform is not getting power from a
regulator but from the MX power domain.
Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290")
Signed-off-by: Marijn Suijten <[email protected]>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index 3ce45b023e63..31deda1c664a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -1087,8 +1087,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
.has_phy_lane = true,
- .regulator_data = dsi_phy_14nm_17mA_regulators,
- .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
--
2.41.0
Document availability of the 14nm DSI PHY on SM6125. Note that this
compatible uses the SoC-suffix variant, intead of postfixing an
arbitrary number without the sm/sdm portion. The PHY is not powered by
a vcca regulator like on most SoCs, but by the MX power domain that is
provided via the power-domains property and a single corresponding
required-opps.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
.../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
index a43e11d3b00d..183a26f8a6dc 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -19,6 +19,7 @@ properties:
- qcom,dsi-phy-14nm-2290
- qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953
+ - qcom,sm6125-dsi-phy-14nm
reg:
items:
@@ -35,6 +36,16 @@ properties:
vcca-supply:
description: Phandle to vcca regulator device node.
+ power-domains:
+ description:
+ A phandle and PM domain specifier for an optional power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing an optional performance point.
+ maxItems: 1
+
required:
- compatible
- reg
--
2.41.0
On SM6125 the dispcc block is gated behind VDDCX: allow this domain to
be configured.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
index 8fd29915bf2c..9ab8ddad904b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
@@ -48,6 +48,11 @@ properties:
'#power-domain-cells':
const: 1
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the CX power domain.
+ maxItems: 1
+
reg:
maxItems: 1
@@ -65,6 +70,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x5f00000 0x20000>;
@@ -84,6 +90,7 @@ examples:
"dp_phy_pll_vco_div_clk",
"cfg_ahb_clk",
"gcc_disp_gpll0_div_clk_src";
+ power-domains = <&rpmpd SM6125_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.41.0
This node has always resided in the wrong spot, making it somewhat
harder to contribute new node entries while maintaining proper sorting
around it. Move the node up to sit after hsusb_phy1 where it maintains
proper numerical sorting on the (first of its many) reg address
property.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index a596baa6ce3e..722dde560bec 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -679,6 +679,24 @@ hsusb_phy1: phy@1613000 {
status = "disabled";
};
+ spmi_bus: spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x01c40000 0x1100>,
+ <0x01e00000 0x2000000>,
+ <0x03e00000 0x100000>,
+ <0x03f00000 0xa0000>,
+ <0x01c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x045f0000 0x7000>;
@@ -1184,27 +1202,9 @@ sram@4690000 {
reg = <0x04690000 0x10000>;
};
- spmi_bus: spmi@1c40000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x01c40000 0x1100>,
- <0x01e00000 0x2000000>,
- <0x03e00000 0x100000>,
- <0x03f00000 0xa0000>,
- <0x01c0a000 0x26000>;
- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
- interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- qcom,ee = <0>;
- qcom,channel = <0>;
- #address-cells = <2>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <4>;
- };
-
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
- reg = <0xc600000 0x80000>;
+ reg = <0x0c600000 0x80000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
--
2.41.0
SM6125 is identical to SM6375 except that while downstream also defines
a throttle clock, its presence results in timeouts whereas SM6375
requires it to not observe any timeouts. This is represented by
reducing the clock array length to 6 so that it cannot be passed. Note
that any SoC other than SM6375 (currently SC7180 and SM6350) are
unconstrained and could either pass or leave out this "throttle" clock.
Signed-off-by: Marijn Suijten <[email protected]>
---
.../devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
index 630b11480496..37f66940c5e3 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml
@@ -15,6 +15,7 @@ properties:
compatible:
enum:
- qcom,sc7180-dpu
+ - qcom,sm6125-dpu
- qcom,sm6350-dpu
- qcom,sm6375-dpu
@@ -73,6 +74,19 @@ allOf:
clock-names:
minItems: 7
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm6125-dpu
+
+ then:
+ properties:
+ clocks:
+ maxItems: 6
+
+ clock-names:
+ maxItems: 6
+
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
--
2.41.0
SM6125 features only a single PHY (despite a secondary PHY PLL source
being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
sources for this "trinket" SoC do not define the typical "vcca"
regulator to be available nor used. This, including the register offset
is identical to QCM2290, whose config struct can trivially be reused.
Signed-off-by: Marijn Suijten <[email protected]>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 9d5795c58a98..05621e5e7d63 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_14nm_660_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-8953",
.data = &dsi_phy_14nm_8953_cfgs },
+ { .compatible = "qcom,sm6125-dsi-phy-14nm",
+ .data = &dsi_phy_14nm_2290_cfgs },
#endif
#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
{ .compatible = "qcom,dsi-phy-10nm",
--
2.41.0
Document the SM6125 MDSS.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
.../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 +++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
new file mode 100644
index 000000000000..2525482424cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6125 Display MDSS
+
+maintainers:
+ - Marijn Suijten <[email protected]>
+
+description:
+ SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm6125-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6125-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6125-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6125-dsi-phy-14nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
+ #include <dt-bindings/clock/qcom,gcc-sm6125.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6125-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x400 0x0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6125-dpu";
+ reg = <0x05e01000 0x83208>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6125_VDDCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6125_VDDCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ phy@5e94400 {
+ compatible = "qcom,sm6125-dsi-phy-14nm";
+ reg = <0x05e94400 0x100>,
+ <0x05e94500 0x300>,
+ <0x05e94800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref";
+
+ required-opps = <&rpmpd_opp_svs>;
+ power-domains = <&rpmpd SM6125_VDDMX>;
+
+ status = "disabled";
+ };
+ };
+...
--
2.41.0
We have a working RPM XO clock; no other driver except rpmcc should be
parenting directly to the fixed-factor xo_board clock nor should it be
reachable by that global name. Remove the name to that effect, so that
every clock relation is explicitly defined in DTS.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 722dde560bec..edb03508dba3 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -22,7 +22,6 @@ xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
@@ -306,6 +305,8 @@ rpm_requests: rpm-requests {
rpmcc: clock-controller {
compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
rpmpd: power-controller {
@@ -713,7 +714,7 @@ sdhc_1: mmc@4744000 {
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
- <&xo_board>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x160 0x0>;
@@ -740,7 +741,7 @@ sdhc_2: mmc@4784000 {
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x180 0x0>;
--
2.41.0
Add definitions for the display hardware used on the Qualcomm SM6125
platform.
Signed-off-by: Marijn Suijten <[email protected]>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 238 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
new file mode 100644
index 000000000000..7ab64b0c18b5
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Marijn Suijten <[email protected]>. All rights reserved.
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_5_4_SM6125_H
+#define _DPU_5_4_SM6125_H
+
+static const struct dpu_caps sm6125_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x6,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
+static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_10,
+ .highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x1,
+};
+
+static const struct dpu_mdp_cfg sm6125_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x45c,
+ .features = 0,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6125_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x1800, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a00, .len = 0x1e0,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6125_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1f0,
+ .features = VIG_SM6125_MASK,
+ .sblk = &sm6125_vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1f0,
+ .features = DMA_SDM845_MASK,
+ .sblk = &sdm845_dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ },
+};
+
+static const struct dpu_lm_cfg sm6125_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ .lm_pair = LM_1,
+ }, {
+ .name = "lm_1", .id = LM_1,
+ .base = 0x45000, .len = 0x320,
+ .features = MIXER_QCM2290_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_1,
+ .dspp = 0,
+ .lm_pair = LM_0,
+ },
+};
+
+static const struct dpu_dspp_cfg sm6125_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .features = DSPP_SC7180_MASK,
+ .sblk = &sm8150_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg sm6125_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x70000, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .merge_3d = 0,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ .intr_rdptr = -1,
+ }, {
+ .name = "pingpong_1", .id = PINGPONG_1,
+ .base = 0x70800, .len = 0xd4,
+ .features = PINGPONG_SM8150_MASK,
+ .merge_3d = 0,
+ .sblk = &sdm845_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ .intr_rdptr = -1,
+ },
+};
+
+static const struct dpu_intf_cfg sm6125_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x6a000, .len = 0x280,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ .intr_tear_rd_ptr = -1,
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x6a800, .len = 0x2c0,
+ .features = INTF_SC7180_MASK,
+ .type = INTF_DSI,
+ .controller_id = 0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ },
+};
+
+static const struct dpu_perf_cfg sm6125_perf_data = {
+ .max_bw_low = 4100000,
+ .max_bw_high = 4100000,
+ .min_core_ib = 2400000,
+ .min_llcc_ib = 0, /* No LLCC on this SoC */
+ .min_dram_ib = 800000,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xf, 0xffff, 0x0},
+ .safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm8150_qos_linear),
+ .entries = sm8150_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6125_cfg = {
+ .caps = &sm6125_dpu_caps,
+ .ubwc = &sm6125_ubwc_cfg,
+ .mdp = &sm6125_mdp,
+ .ctl_count = ARRAY_SIZE(sm6125_ctl),
+ .ctl = sm6125_ctl,
+ .sspp_count = ARRAY_SIZE(sm6125_sspp),
+ .sspp = sm6125_sspp,
+ .mixer_count = ARRAY_SIZE(sm6125_lm),
+ .mixer = sm6125_lm,
+ .dspp_count = ARRAY_SIZE(sm6125_dspp),
+ .dspp = sm6125_dspp,
+ .pingpong_count = ARRAY_SIZE(sm6125_pp),
+ .pingpong = sm6125_pp,
+ .intf_count = ARRAY_SIZE(sm6125_intf),
+ .intf = sm6125_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6125_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 3efa22429e5f..f529d1b988e3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -33,6 +33,9 @@
#define VIG_SC7180_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
+#define VIG_SM6125_MASK \
+ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
+
#define VIG_SC7180_MASK_SDMA \
(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
@@ -332,6 +335,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4);
+static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
+ _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
@@ -632,6 +637,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_5_0_sm8150.h"
#include "catalog/dpu_5_1_sc8180x.h"
+#include "catalog/dpu_5_4_sm6125.h"
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 3b816e36d12d..1d150091da9c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -860,6 +860,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 882f20fc51cc..3b93b874394e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
--
2.41.0
Add the DT nodes that describe the MDSS hardware on SM6125, containing
one MDP (display controller) together with a single DSI and DSI PHY. No
DisplayPort support is added for now.
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 191 ++++++++++++++++++++++++++++++++++-
1 file changed, 189 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index a5cc0d43d2d9..b21fa1256f95 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1204,12 +1204,199 @@ sram@4690000 {
reg = <0x04690000 0x10000>;
};
+ mdss: display-subsystem@5e00000 {
+ compatible = "qcom,sm6125-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x400 0x0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@5e01000 {
+ compatible = "qcom,sm6125-dpu";
+ reg = <0x05e01000 0x83208>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6125_VDDCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-256000000 {
+ opp-hz = /bits/ 64 <256000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@5e94000 {
+ compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6125_VDDCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6125-dsi-phy-14nm";
+ reg = <0x05e94400 0x100>,
+ <0x05e94500 0x300>,
+ <0x05e94800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref";
+
+ required-opps = <&rpmpd_opp_svs>;
+ power-domains = <&rpmpd SM6125_VDDMX>;
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x05f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <0>,
- <0>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
<0>,
<0>,
<0>,
--
2.41.0
SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder.
Signed-off-by: Marijn Suijten <[email protected]>
---
drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 05648c910c68..bf68bae23264 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -559,6 +559,13 @@ static const struct msm_mdss_data sm6115_data = {
.ubwc_static = 0x11f,
};
+static const struct msm_mdss_data sm6125_data = {
+ .ubwc_version = UBWC_1_0,
+ .ubwc_dec_version = UBWC_3_0,
+ .ubwc_swizzle = 1,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sm8250_data = {
.ubwc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_0,
@@ -579,6 +586,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
{ .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
{ .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
+ { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
{ .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
{ .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
--
2.41.0
Document general compatibility of the DSI controller on SM6125.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index 01848bdd5873..23926c39407e 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
+ - qcom,sm6125-dsi-ctrl
- qcom,sm6350-dsi-ctrl
- qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
@@ -301,6 +302,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
+ - qcom,sm6125-dsi-ctrl
- qcom,sm6350-dsi-ctrl
then:
properties:
--
2.41.0
Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01
6.0" 1080x2520 panel.
Signed-off-by: Marijn Suijten <[email protected]>
---
.../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
index 9f8a9ef398a2..08d96d05da2e 100644
--- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
+++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
@@ -179,6 +179,43 @@ &i2c3 {
/* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm6125_l18>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "samsung,sofef01-m-ams597ut01";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&pm6125_l12>;
+
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active_sleep>;
+ pinctrl-1 = <&mdss_dsi_sleep &mdss_te_active_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
&pm6125_adc {
pinctrl-names = "default";
pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
@@ -469,6 +506,28 @@ vol_down_n: vol-down-n-state {
drive-strength = <2>;
bias-disable;
};
+
+ mdss_te_active_sleep: mdss-te-active-sleep-state {
+ pins = "gpio89";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdss_dsi_active: mdss-dsi-active-state {
+ pins = "gpio90";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdss_dsi_sleep: mdss-dsi-sleep-state {
+ pins = "gpio90";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
};
&usb3 {
--
2.41.0
On 27.06.2023 22:14, Marijn Suijten wrote:
> The regulator setup was likely copied from other SoCs by mistake. Just
> like SM6125 the DSI PHY on this platform is not getting power from a
> regulator but from the MX power domain.
>
> Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290")
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index 3ce45b023e63..31deda1c664a 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1087,8 +1087,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
>
> const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
> .has_phy_lane = true,
> - .regulator_data = dsi_phy_14nm_17mA_regulators,
> - .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
> .ops = {
> .enable = dsi_14nm_phy_enable,
> .disable = dsi_14nm_phy_disable,
>
On 27.06.2023 22:14, Marijn Suijten wrote:
> Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01
> 6.0" 1080x2520 panel.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> index 9f8a9ef398a2..08d96d05da2e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> @@ -179,6 +179,43 @@ &i2c3 {
> /* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
> };
>
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&pm6125_l18>;
> + status = "okay";
> +
> + panel@0 {
> + compatible = "samsung,sofef01-m-ams597ut01";
> + reg = <0>;
> +
> + reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>;
> +
> + vddio-supply = <&pm6125_l12>;
> +
> + pinctrl-0 = <&mdss_dsi_active &mdss_te_active_sleep>;
> + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_active_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> + };
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <&panel_in>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + status = "okay";
> +};
> +
> &pm6125_adc {
> pinctrl-names = "default";
> pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
> @@ -469,6 +506,28 @@ vol_down_n: vol-down-n-state {
> drive-strength = <2>;
> bias-disable;
> };
> +
> + mdss_te_active_sleep: mdss-te-active-sleep-state {
> + pins = "gpio89";
> + function = "mdp_vsync";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + mdss_dsi_active: mdss-dsi-active-state {
> + pins = "gpio90";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> +
> + mdss_dsi_sleep: mdss-dsi-sleep-state {
> + pins = "gpio90";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> };
>
> &usb3 {
>
On 27.06.2023 22:14, Marijn Suijten wrote:
> Add the DT nodes that describe the MDSS hardware on SM6125, containing
> one MDP (display controller) together with a single DSI and DSI PHY. No
> DisplayPort support is added for now.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 191 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 189 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index a5cc0d43d2d9..b21fa1256f95 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -1204,12 +1204,199 @@ sram@4690000 {
> reg = <0x04690000 0x10000>;
> };
>
> + mdss: display-subsystem@5e00000 {
> + compatible = "qcom,sm6125-mdss";
> + reg = <0x05e00000 0x1000>;
> + reg-names = "mdss";
> +
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "ahb",
> + "core";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + iommus = <&apps_smmu 0x400 0x0>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss_mdp: display-controller@5e01000 {
> + compatible = "qcom,sm6125-dpu";
> + reg = <0x05e01000 0x83208>,
> + <0x05eb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "iface",
> + "rot",
> + "lut",
> + "core",
> + "vsync";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmpd SM6125_VDDCX>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&mdss_dsi0_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-192000000 {
> + opp-hz = /bits/ 64 <192000000>;
> + required-opps = <&rpmpd_opp_low_svs>;
> + };
> +
> + opp-256000000 {
> + opp-hz = /bits/ 64 <256000000>;
> + required-opps = <&rpmpd_opp_svs>;
> + };
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + required-opps = <&rpmpd_opp_svs_plus>;
> + };
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmpd_opp_nom>;
> + };
> +
> + opp-400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + required-opps = <&rpmpd_opp_turbo>;
> + };
> + };
> + };
> +
> + mdss_dsi0: dsi@5e94000 {
> + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> + reg = <0x05e94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmpd SM6125_VDDCX>;
> +
> + phys = <&mdss_dsi0_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-164000000 {
> + opp-hz = /bits/ 64 <164000000>;
> + required-opps = <&rpmpd_opp_low_svs>;
> + };
> +
> + opp-187500000 {
> + opp-hz = /bits/ 64 <187500000>;
> + required-opps = <&rpmpd_opp_svs>;
> + };
> + };
> + };
> +
> + mdss_dsi0_phy: phy@5e94400 {
> + compatible = "qcom,sm6125-dsi-phy-14nm";
> + reg = <0x05e94400 0x100>,
> + <0x05e94500 0x300>,
> + <0x05e94800 0x188>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface",
> + "ref";
> +
> + required-opps = <&rpmpd_opp_svs>;
> + power-domains = <&rpmpd SM6125_VDDMX>;
> +
> + status = "disabled";
> + };
> + };
> +
> dispcc: clock-controller@5f00000 {
> compatible = "qcom,sm6125-dispcc";
> reg = <0x05f00000 0x20000>;
> clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> - <0>,
> - <0>,
> + <&mdss_dsi0_phy 0>,
> + <&mdss_dsi0_phy 1>,
> <0>,
> <0>,
> <0>,
>
Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index edb03508dba3..a5cc0d43d2d9 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2021, Martin Botka <[email protected]>
*/
+#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -1203,6 +1204,30 @@ sram@4690000 {
reg = <0x04690000 0x10000>;
};
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,sm6125-dispcc";
+ reg = <0x05f00000 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "cfg_ahb_clk",
+ "gcc_disp_gpll0_div_clk_src";
+ power-domains = <&rpmpd SM6125_VDDCX>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
apps_smmu: iommu@c600000 {
compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0c600000 0x80000>;
--
2.41.0
On 27.06.2023 22:14, Marijn Suijten wrote:
> SM6125 features only a single PHY (despite a secondary PHY PLL source
> being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
> sources for this "trinket" SoC do not define the typical "vcca"
> regulator to be available nor used. This, including the register offset
> is identical to QCM2290, whose config struct can trivially be reused.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 9d5795c58a98..05621e5e7d63 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> .data = &dsi_phy_14nm_660_cfgs },
> { .compatible = "qcom,dsi-phy-14nm-8953",
> .data = &dsi_phy_14nm_8953_cfgs },
> + { .compatible = "qcom,sm6125-dsi-phy-14nm",
> + .data = &dsi_phy_14nm_2290_cfgs },
> #endif
> #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
> { .compatible = "qcom,dsi-phy-10nm",
>
On Tue, 27 Jun 2023 22:14:22 +0200, Marijn Suijten wrote:
> Document the SM6125 MDSS.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 +++++++++++++++++++++
> 1 file changed, 217 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.example.dtb: dsi@5e94000: compatible: 'oneOf' conditional failed, one must be fixed:
['qcom,sm6125-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
'qcom,sm6125-dsi-ctrl' is not one of ['qcom,apq8064-dsi-ctrl', 'qcom,msm8916-dsi-ctrl', 'qcom,msm8953-dsi-ctrl', 'qcom,msm8974-dsi-ctrl', 'qcom,msm8996-dsi-ctrl', 'qcom,msm8998-dsi-ctrl', 'qcom,qcm2290-dsi-ctrl', 'qcom,sc7180-dsi-ctrl', 'qcom,sc7280-dsi-ctrl', 'qcom,sdm660-dsi-ctrl', 'qcom,sdm845-dsi-ctrl', 'qcom,sm6115-dsi-ctrl', 'qcom,sm8150-dsi-ctrl', 'qcom,sm8250-dsi-ctrl', 'qcom,sm8350-dsi-ctrl', 'qcom,sm8450-dsi-ctrl', 'qcom,sm8550-dsi-ctrl']
'qcom,sm6125-dsi-ctrl' is not one of ['qcom,dsi-ctrl-6g-qcm2290', 'qcom,mdss-dsi-ctrl']
from schema $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Tue, Jun 27, 2023 at 10:14:22PM +0200, Marijn Suijten wrote:
> Document the SM6125 MDSS.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 +++++++++++++++++++++
> 1 file changed, 217 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
> new file mode 100644
> index 000000000000..2525482424cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
> @@ -0,0 +1,217 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6125 Display MDSS
> +
> +maintainers:
> + - Marijn Suijten <[email protected]>
> +
> +description:
> + SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
> + like DPU display controller, DSI and DP interfaces etc.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,sm6125-mdss
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display AHB clock
> + - description: Display core clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: ahb
> + - const: core
> +
> + iommus:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + maxItems: 2
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sm6125-dpu
> +
> + "^dsi@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + items:
> + - const: qcom,sm6125-dsi-ctrl
> + - const: qcom,mdss-dsi-ctrl
> +
> + "^phy@[0-9a-f]+$":
> + type: object
> + properties:
> + compatible:
> + const: qcom,sm6125-dsi-phy-14nm
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> + #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> + #include <dt-bindings/clock/qcom,rpmcc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + display-subsystem@5e00000 {
> + compatible = "qcom,sm6125-mdss";
> + reg = <0x05e00000 0x1000>;
> + reg-names = "mdss";
> +
> + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> + "ahb",
> + "core";
> +
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + iommus = <&apps_smmu 0x400 0x0>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + status = "disabled";
Examples should not be disabled. Drop.
> +
> + display-controller@5e01000 {
> + compatible = "qcom,sm6125-dpu";
> + reg = <0x05e01000 0x83208>,
> + <0x05eb0000 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "iface",
> + "rot",
> + "lut",
> + "core",
> + "vsync";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdp_opp_table>;
> + power-domains = <&rpmpd SM6125_VDDCX>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&mdss_dsi0_in>;
> + };
> + };
> + };
> + };
> +
> + dsi@5e94000 {
> + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> + reg = <0x05e94000 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> +
> + operating-points-v2 = <&dsi_opp_table>;
> + power-domains = <&rpmpd SM6125_VDDCX>;
> +
> + phys = <&mdss_dsi0_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
Ditto.
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + phy@5e94400 {
> + compatible = "qcom,sm6125-dsi-phy-14nm";
> + reg = <0x05e94400 0x100>,
> + <0x05e94500 0x300>,
> + <0x05e94800 0x188>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface",
> + "ref";
> +
> + required-opps = <&rpmpd_opp_svs>;
> + power-domains = <&rpmpd SM6125_VDDMX>;
> +
> + status = "disabled";
Ditto
> + };
> + };
> +...
>
> --
> 2.41.0
>
On 2023-06-28 09:30:51, Rob Herring wrote:
> On Tue, Jun 27, 2023 at 10:14:22PM +0200, Marijn Suijten wrote:
> > Document the SM6125 MDSS.
> >
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
> > Signed-off-by: Marijn Suijten <[email protected]>
> > ---
> > .../bindings/display/msm/qcom,sm6125-mdss.yaml | 217 +++++++++++++++++++++
> > 1 file changed, 217 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
> > new file mode 100644
> > index 000000000000..2525482424cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml
> > @@ -0,0 +1,217 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM6125 Display MDSS
> > +
> > +maintainers:
> > + - Marijn Suijten <[email protected]>
> > +
> > +description:
> > + SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
> > + like DPU display controller, DSI and DP interfaces etc.
> > +
> > +$ref: /schemas/display/msm/mdss-common.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: qcom,sm6125-mdss
> > +
> > + clocks:
> > + items:
> > + - description: Display AHB clock from gcc
> > + - description: Display AHB clock
> > + - description: Display core clock
> > +
> > + clock-names:
> > + items:
> > + - const: iface
> > + - const: ahb
> > + - const: core
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + interconnects:
> > + maxItems: 2
> > +
> > + interconnect-names:
> > + maxItems: 2
> > +
> > +patternProperties:
> > + "^display-controller@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,sm6125-dpu
> > +
> > + "^dsi@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + items:
> > + - const: qcom,sm6125-dsi-ctrl
> > + - const: qcom,mdss-dsi-ctrl
> > +
> > + "^phy@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + compatible:
> > + const: qcom,sm6125-dsi-phy-14nm
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> > + #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> > + #include <dt-bindings/clock/qcom,rpmcc.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/power/qcom-rpmpd.h>
> > +
> > + display-subsystem@5e00000 {
> > + compatible = "qcom,sm6125-mdss";
> > + reg = <0x05e00000 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + clocks = <&gcc GCC_DISP_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface",
> > + "ahb",
> > + "core";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > +
> > + iommus = <&apps_smmu 0x400 0x0>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + status = "disabled";
>
> Examples should not be disabled. Drop.
Thanks, I think I missed this in the diff when importing the updated DT
bindings into this example.
Will drop for v3 pending other comments.
More importantly, why is your bot complaining the following about this
example:
['qcom,sm6125-dsi-ctrl', 'qcom,mdss-dsi-ctrl'] is too long
...
'qcom,sm6125-dsi-ctrl' is not one of ['qcom,dsi-ctrl-6g-qcm2290', 'qcom,mdss-dsi-ctrl']
This is patch 07/15, but that compatible was already added in 05/15.
- Marijn
> > +
> > + display-controller@5e01000 {
> > + compatible = "qcom,sm6125-dpu";
> > + reg = <0x05e01000 0x83208>,
> > + <0x05eb0000 0x2008>;
> > + reg-names = "mdp", "vbif";
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "iface",
> > + "rot",
> > + "lut",
> > + "core",
> > + "vsync";
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmpd SM6125_VDDCX>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dpu_intf1_out: endpoint {
> > + remote-endpoint = <&mdss_dsi0_in>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi@5e94000 {
> > + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> > + reg = <0x05e94000 0x400>;
> > + reg-names = "dsi_ctrl";
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <4>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> > + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>;
> > + clock-names = "byte",
> > + "byte_intf",
> > + "pixel",
> > + "core",
> > + "iface",
> > + "bus";
> > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> > + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
> > +
> > + operating-points-v2 = <&dsi_opp_table>;
> > + power-domains = <&rpmpd SM6125_VDDCX>;
> > +
> > + phys = <&mdss_dsi0_phy>;
> > + phy-names = "dsi";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + status = "disabled";
>
> Ditto.
>
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + mdss_dsi0_in: endpoint {
> > + remote-endpoint = <&dpu_intf1_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + mdss_dsi0_out: endpoint {
> > + };
> > + };
> > + };
> > + };
> > +
> > + phy@5e94400 {
> > + compatible = "qcom,sm6125-dsi-phy-14nm";
> > + reg = <0x05e94400 0x100>,
> > + <0x05e94500 0x300>,
> > + <0x05e94800 0x188>;
> > + reg-names = "dsi_phy",
> > + "dsi_phy_lane",
> > + "dsi_pll";
> > +
> > + #clock-cells = <1>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> > + clock-names = "iface",
> > + "ref";
> > +
> > + required-opps = <&rpmpd_opp_svs>;
> > + power-domains = <&rpmpd SM6125_VDDMX>;
> > +
> > + status = "disabled";
>
> Ditto
>
> > + };
> > + };
> > +...
> >
> > --
> > 2.41.0
> >
On 27/06/2023 23:14, Marijn Suijten wrote:
> The regulator setup was likely copied from other SoCs by mistake. Just
> like SM6125 the DSI PHY on this platform is not getting power from a
> regulator but from the MX power domain.
>
> Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290")
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> We have a working RPM XO clock; no other driver except rpmcc should be
> parenting directly to the fixed-factor xo_board clock nor should it be
> reachable by that global name. Remove the name to that effect, so that
> every clock relation is explicitly defined in DTS.
>
> Reviewed-by: Konrad Dybcio <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 722dde560bec..edb03508dba3 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -22,7 +22,6 @@ xo_board: xo-board {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <19200000>;
> - clock-output-names = "xo_board";
Why? I'd say, leave it.
With that fixed:
Reviewed-by: Dmitry Baryshkov <[email protected]>
> };
>
> sleep_clk: sleep-clk {
> @@ -306,6 +305,8 @@ rpm_requests: rpm-requests {
> rpmcc: clock-controller {
> compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
> #clock-cells = <1>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> };
>
> rpmpd: power-controller {
> @@ -713,7 +714,7 @@ sdhc_1: mmc@4744000 {
>
> clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> <&gcc GCC_SDCC1_APPS_CLK>,
> - <&xo_board>;
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "core", "xo";
> iommus = <&apps_smmu 0x160 0x0>;
>
> @@ -740,7 +741,7 @@ sdhc_2: mmc@4784000 {
>
> clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> <&gcc GCC_SDCC2_APPS_CLK>,
> - <&xo_board>;
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> clock-names = "iface", "core", "xo";
> iommus = <&apps_smmu 0x180 0x0>;
>
>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> SM6125 features only a single PHY (despite a secondary PHY PLL source
> being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
> sources for this "trinket" SoC do not define the typical "vcca"
> regulator to be available nor used. This, including the register offset
> is identical to QCM2290, whose config struct can trivially be reused.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> Add definitions for the display hardware used on the Qualcomm SM6125
> platform.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 238 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> Document general compatibility of the DSI controller on SM6125.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> Document availability of the 14nm DSI PHY on SM6125. Note that this
> compatible uses the SoC-suffix variant, intead of postfixing an
> arbitrary number without the sm/sdm portion. The PHY is not powered by
> a vcca regulator like on most SoCs, but by the MX power domain that is
> provided via the power-domains property and a single corresponding
> required-opps.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> .../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> index a43e11d3b00d..183a26f8a6dc 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -19,6 +19,7 @@ properties:
> - qcom,dsi-phy-14nm-2290
> - qcom,dsi-phy-14nm-660
> - qcom,dsi-phy-14nm-8953
> + - qcom,sm6125-dsi-phy-14nm
>
> reg:
> items:
> @@ -35,6 +36,16 @@ properties:
> vcca-supply:
> description: Phandle to vcca regulator device node.
>
> + power-domains:
> + description:
> + A phandle and PM domain specifier for an optional power domain.
> + maxItems: 1
> +
> + required-opps:
> + description:
> + A phandle to an OPP node describing an optional performance point.
I'd rephrase this to be something more exact, like 'desribing power
domain's performance point'.
> + maxItems: 1
> +
> required:
> - compatible
> - reg
>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> Enable and configure the dispcc node on SM6125 for consumption by MDSS
> later on.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index edb03508dba3..a5cc0d43d2d9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2021, Martin Botka <[email protected]>
> */
>
> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> #include <dt-bindings/clock/qcom,rpmcc.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> @@ -1203,6 +1204,30 @@ sram@4690000 {
> reg = <0x04690000 0x10000>;
> };
>
> + dispcc: clock-controller@5f00000 {
> + compatible = "qcom,sm6125-dispcc";
> + reg = <0x05f00000 0x20000>;
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk",
> + "cfg_ahb_clk",
> + "gcc_disp_gpll0_div_clk_src";
> + power-domains = <&rpmpd SM6125_VDDCX>;
Would it be logical to specify the required-opps too?
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> apps_smmu: iommu@c600000 {
> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> reg = <0x0c600000 0x80000>;
>
--
With best wishes
Dmitry
On 27/06/2023 23:14, Marijn Suijten wrote:
> Add the DT nodes that describe the MDSS hardware on SM6125, containing
> one MDP (display controller) together with a single DSI and DSI PHY. No
> DisplayPort support is added for now.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 191 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 189 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index a5cc0d43d2d9..b21fa1256f95 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -1204,12 +1204,199 @@ sram@4690000 {
> reg = <0x04690000 0x10000>;
> };
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 2023-06-29 13:55:28, Dmitry Baryshkov wrote:
> On 27/06/2023 23:14, Marijn Suijten wrote:
> > We have a working RPM XO clock; no other driver except rpmcc should be
> > parenting directly to the fixed-factor xo_board clock nor should it be
> > reachable by that global name. Remove the name to that effect, so that
> > every clock relation is explicitly defined in DTS.
> >
> > Reviewed-by: Konrad Dybcio <[email protected]>
> > Signed-off-by: Marijn Suijten <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > index 722dde560bec..edb03508dba3 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > @@ -22,7 +22,6 @@ xo_board: xo-board {
> > compatible = "fixed-clock";
> > #clock-cells = <0>;
> > clock-frequency = <19200000>;
> > - clock-output-names = "xo_board";
>
> Why? I'd say, leave it.
The exact reason is explained in the commit message.
>
> With that fixed:
Hence I don't think it makes sense to "fix" this.
- Marijn
> Reviewed-by: Dmitry Baryshkov <[email protected]>
On 2023-06-29 13:56:25, Dmitry Baryshkov wrote:
> On 27/06/2023 23:14, Marijn Suijten wrote:
> > Enable and configure the dispcc node on SM6125 for consumption by MDSS
> > later on.
> >
> > Signed-off-by: Marijn Suijten <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > index edb03508dba3..a5cc0d43d2d9 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > @@ -3,6 +3,7 @@
> > * Copyright (c) 2021, Martin Botka <[email protected]>
> > */
> >
> > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> > #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> > #include <dt-bindings/clock/qcom,rpmcc.h>
> > #include <dt-bindings/dma/qcom-gpi.h>
> > @@ -1203,6 +1204,30 @@ sram@4690000 {
> > reg = <0x04690000 0x10000>;
> > };
> >
> > + dispcc: clock-controller@5f00000 {
> > + compatible = "qcom,sm6125-dispcc";
> > + reg = <0x05f00000 0x20000>;
> > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <0>,
> > + <&gcc GCC_DISP_AHB_CLK>,
> > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> > + clock-names = "bi_tcxo",
> > + "dsi0_phy_pll_out_byteclk",
> > + "dsi0_phy_pll_out_dsiclk",
> > + "dsi1_phy_pll_out_dsiclk",
> > + "dp_phy_pll_link_clk",
> > + "dp_phy_pll_vco_div_clk",
> > + "cfg_ahb_clk",
> > + "gcc_disp_gpll0_div_clk_src";
> > + power-domains = <&rpmpd SM6125_VDDCX>;
>
> Would it be logical to specify the required-opps too?
Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc.
What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI
PHY despite not having a reference value downstream (it sets a range of
NOM-TURBO_NO_CPR, and RETENTION when it's off).
- Marijn
>
> > + #clock-cells = <1>;
> > + #power-domain-cells = <1>;
> > + };
> > +
> > apps_smmu: iommu@c600000 {
> > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> > reg = <0x0c600000 0x80000>;
> >
>
> --
> With best wishes
> Dmitry
>
On Thu, 29 Jun 2023 at 15:14, Marijn Suijten
<[email protected]> wrote:
>
> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote:
> > On 27/06/2023 23:14, Marijn Suijten wrote:
> > > Enable and configure the dispcc node on SM6125 for consumption by MDSS
> > > later on.
> > >
> > > Signed-off-by: Marijn Suijten <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
> > > 1 file changed, 25 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > index edb03508dba3..a5cc0d43d2d9 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > @@ -3,6 +3,7 @@
> > > * Copyright (c) 2021, Martin Botka <[email protected]>
> > > */
> > >
> > > +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
> > > #include <dt-bindings/clock/qcom,gcc-sm6125.h>
> > > #include <dt-bindings/clock/qcom,rpmcc.h>
> > > #include <dt-bindings/dma/qcom-gpi.h>
> > > @@ -1203,6 +1204,30 @@ sram@4690000 {
> > > reg = <0x04690000 0x10000>;
> > > };
> > >
> > > + dispcc: clock-controller@5f00000 {
> > > + compatible = "qcom,sm6125-dispcc";
> > > + reg = <0x05f00000 0x20000>;
> > > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> > > + <0>,
> > > + <0>,
> > > + <0>,
> > > + <0>,
> > > + <0>,
> > > + <&gcc GCC_DISP_AHB_CLK>,
> > > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> > > + clock-names = "bi_tcxo",
> > > + "dsi0_phy_pll_out_byteclk",
> > > + "dsi0_phy_pll_out_dsiclk",
> > > + "dsi1_phy_pll_out_dsiclk",
> > > + "dp_phy_pll_link_clk",
> > > + "dp_phy_pll_vco_div_clk",
> > > + "cfg_ahb_clk",
> > > + "gcc_disp_gpll0_div_clk_src";
> > > + power-domains = <&rpmpd SM6125_VDDCX>;
> >
> > Would it be logical to specify the required-opps too?
>
> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc.
> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI
> PHY despite not having a reference value downstream (it sets a range of
> NOM-TURBO_NO_CPR, and RETENTION when it's off).
Then for DSI PHY the required-opps should be rpmpd_opp_nom.
For the dispcc I think the rpmpd_opp_ret, the lowest possible vote,
should be enough.
>
> - Marijn
>
> >
> > > + #clock-cells = <1>;
> > > + #power-domain-cells = <1>;
> > > + };
> > > +
> > > apps_smmu: iommu@c600000 {
> > > compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> > > reg = <0x0c600000 0x80000>;
> > >
> >
> > --
> > With best wishes
> > Dmitry
> >
--
With best wishes
Dmitry
On Thu, 29 Jun 2023 at 15:09, Marijn Suijten
<[email protected]> wrote:
>
> On 2023-06-29 13:55:28, Dmitry Baryshkov wrote:
> > On 27/06/2023 23:14, Marijn Suijten wrote:
> > > We have a working RPM XO clock; no other driver except rpmcc should be
> > > parenting directly to the fixed-factor xo_board clock nor should it be
> > > reachable by that global name. Remove the name to that effect, so that
> > > every clock relation is explicitly defined in DTS.
> > >
> > > Reviewed-by: Konrad Dybcio <[email protected]>
> > > Signed-off-by: Marijn Suijten <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
> > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > index 722dde560bec..edb03508dba3 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > > @@ -22,7 +22,6 @@ xo_board: xo-board {
> > > compatible = "fixed-clock";
> > > #clock-cells = <0>;
> > > clock-frequency = <19200000>;
> > > - clock-output-names = "xo_board";
> >
> > Why? I'd say, leave it.
>
> The exact reason is explained in the commit message.
Usually we do no not kill the xo_board name for the sake of anybody
still looking for the old name. Weak argument, I know.
>
> >
> > With that fixed:
>
> Hence I don't think it makes sense to "fix" this.
>
> - Marijn
>
> > Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Tue, 27 Jun 2023 22:14:21 +0200, Marijn Suijten wrote:
> SM6125 is identical to SM6375 except that while downstream also defines
> a throttle clock, its presence results in timeouts whereas SM6375
> requires it to not observe any timeouts. This is represented by
> reducing the clock array length to 6 so that it cannot be passed. Note
> that any SoC other than SM6375 (currently SC7180 and SM6350) are
> unconstrained and could either pass or leave out this "throttle" clock.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> .../devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On 29.06.2023 14:26, Dmitry Baryshkov wrote:
> On Thu, 29 Jun 2023 at 15:09, Marijn Suijten
> <[email protected]> wrote:
>>
>> On 2023-06-29 13:55:28, Dmitry Baryshkov wrote:
>>> On 27/06/2023 23:14, Marijn Suijten wrote:
>>>> We have a working RPM XO clock; no other driver except rpmcc should be
>>>> parenting directly to the fixed-factor xo_board clock nor should it be
>>>> reachable by that global name. Remove the name to that effect, so that
>>>> every clock relation is explicitly defined in DTS.
>>>>
>>>> Reviewed-by: Konrad Dybcio <[email protected]>
>>>> Signed-off-by: Marijn Suijten <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
>>>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> index 722dde560bec..edb03508dba3 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> @@ -22,7 +22,6 @@ xo_board: xo-board {
>>>> compatible = "fixed-clock";
>>>> #clock-cells = <0>;
>>>> clock-frequency = <19200000>;
>>>> - clock-output-names = "xo_board";
>>>
>>> Why? I'd say, leave it.
>>
>> The exact reason is explained in the commit message.
>
> Usually we do no not kill the xo_board name for the sake of anybody
> still looking for the old name. Weak argument, I know.
The only users are (rg -l '"xo_board"' drivers):
drivers/clk/qcom/mmcc-msm8974.c
drivers/clk/qcom/a53-pll.c
drivers/clk/qcom/gcc-msm8974.c
drivers/clk/qcom/clk-smd-rpm.c
drivers/clk/qcom/mmcc-msm8996.c
drivers/clk/qcom/gcc-msm8916.c
drivers/clk/qcom/gcc-apq8084.c
drivers/clk/qcom/gcc-msm8996.c
drivers/clk/qcom/mmcc-apq8084.c
drivers/clk/qcom/clk-rpmh.c
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
This platform only binds clk-smd-rpm, but patch 11 provides a
direct reference in the DT.
Konrad
>
>>
>>>
>>> With that fixed:
>>
>> Hence I don't think it makes sense to "fix" this.
>>
>> - Marijn
>>
>>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>
>
>
On 29.06.2023 14:24, Dmitry Baryshkov wrote:
> On Thu, 29 Jun 2023 at 15:14, Marijn Suijten
> <[email protected]> wrote:
>>
>> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote:
>>> On 27/06/2023 23:14, Marijn Suijten wrote:
>>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS
>>>> later on.
>>>>
>>>> Signed-off-by: Marijn Suijten <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
>>>> 1 file changed, 25 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> index edb03508dba3..a5cc0d43d2d9 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>> @@ -3,6 +3,7 @@
>>>> * Copyright (c) 2021, Martin Botka <[email protected]>
>>>> */
>>>>
>>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
>>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h>
>>>> #include <dt-bindings/clock/qcom,rpmcc.h>
>>>> #include <dt-bindings/dma/qcom-gpi.h>
>>>> @@ -1203,6 +1204,30 @@ sram@4690000 {
>>>> reg = <0x04690000 0x10000>;
>>>> };
>>>>
>>>> + dispcc: clock-controller@5f00000 {
>>>> + compatible = "qcom,sm6125-dispcc";
>>>> + reg = <0x05f00000 0x20000>;
>>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <0>,
>>>> + <&gcc GCC_DISP_AHB_CLK>,
>>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
>>>> + clock-names = "bi_tcxo",
>>>> + "dsi0_phy_pll_out_byteclk",
>>>> + "dsi0_phy_pll_out_dsiclk",
>>>> + "dsi1_phy_pll_out_dsiclk",
>>>> + "dp_phy_pll_link_clk",
>>>> + "dp_phy_pll_vco_div_clk",
>>>> + "cfg_ahb_clk",
>>>> + "gcc_disp_gpll0_div_clk_src";
>>>> + power-domains = <&rpmpd SM6125_VDDCX>;
>>>
>>> Would it be logical to specify the required-opps too?
>>
>> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc.
>> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI
>> PHY despite not having a reference value downstream (it sets a range of
>> NOM-TURBO_NO_CPR, and RETENTION when it's off).
>
> Then for DSI PHY the required-opps should be rpmpd_opp_nom.
Yes
>
> For the dispcc I think the rpmpd_opp_ret, the lowest possible vote,
> should be enough.
I'm not 100% sure but not specifying an opp and turning on the domain
*******probably******* just sticks with the lowest vote
Konrad
>
>>
>> - Marijn
>>
>>>
>>>> + #clock-cells = <1>;
>>>> + #power-domain-cells = <1>;
>>>> + };
>>>> +
>>>> apps_smmu: iommu@c600000 {
>>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>>> reg = <0x0c600000 0x80000>;
>>>>
>>>
>>> --
>>> With best wishes
>>> Dmitry
>>>
>
>
>
On 29/06/2023 22:53, Konrad Dybcio wrote:
> On 29.06.2023 14:24, Dmitry Baryshkov wrote:
>> On Thu, 29 Jun 2023 at 15:14, Marijn Suijten
>> <[email protected]> wrote:
>>>
>>> On 2023-06-29 13:56:25, Dmitry Baryshkov wrote:
>>>> On 27/06/2023 23:14, Marijn Suijten wrote:
>>>>> Enable and configure the dispcc node on SM6125 for consumption by MDSS
>>>>> later on.
>>>>>
>>>>> Signed-off-by: Marijn Suijten <[email protected]>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++
>>>>> 1 file changed, 25 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>>> index edb03508dba3..a5cc0d43d2d9 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>>>> @@ -3,6 +3,7 @@
>>>>> * Copyright (c) 2021, Martin Botka <[email protected]>
>>>>> */
>>>>>
>>>>> +#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
>>>>> #include <dt-bindings/clock/qcom,gcc-sm6125.h>
>>>>> #include <dt-bindings/clock/qcom,rpmcc.h>
>>>>> #include <dt-bindings/dma/qcom-gpi.h>
>>>>> @@ -1203,6 +1204,30 @@ sram@4690000 {
>>>>> reg = <0x04690000 0x10000>;
>>>>> };
>>>>>
>>>>> + dispcc: clock-controller@5f00000 {
>>>>> + compatible = "qcom,sm6125-dispcc";
>>>>> + reg = <0x05f00000 0x20000>;
>>>>> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>>>>> + <0>,
>>>>> + <0>,
>>>>> + <0>,
>>>>> + <0>,
>>>>> + <0>,
>>>>> + <&gcc GCC_DISP_AHB_CLK>,
>>>>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
>>>>> + clock-names = "bi_tcxo",
>>>>> + "dsi0_phy_pll_out_byteclk",
>>>>> + "dsi0_phy_pll_out_dsiclk",
>>>>> + "dsi1_phy_pll_out_dsiclk",
>>>>> + "dp_phy_pll_link_clk",
>>>>> + "dp_phy_pll_vco_div_clk",
>>>>> + "cfg_ahb_clk",
>>>>> + "gcc_disp_gpll0_div_clk_src";
>>>>> + power-domains = <&rpmpd SM6125_VDDCX>;
>>>>
>>>> Would it be logical to specify the required-opps too?
>>>
>>> Perhaps, but barely any other SoC aside from sm8x50 sets it on dispcc.
>>> What should it be, rpmhpd_opp_low_svs? IIRC we used "svs" for the DSI
>>> PHY despite not having a reference value downstream (it sets a range of
>>> NOM-TURBO_NO_CPR, and RETENTION when it's off).
>>
>> Then for DSI PHY the required-opps should be rpmpd_opp_nom.
> Yes
>
>>
>> For the dispcc I think the rpmpd_opp_ret, the lowest possible vote,
>> should be enough.
> I'm not 100% sure but not specifying an opp and turning on the domain
> *******probably******* just sticks with the lowest vote
I think so too. But I think it might be better to be explicit rather
than being implicit here. Both of us are describing Linux behaviour
(=set lowest possible value), while DT should describe the hardware.
>
> Konrad
>>
>>>
>>> - Marijn
>>>
>>>>
>>>>> + #clock-cells = <1>;
>>>>> + #power-domain-cells = <1>;
>>>>> + };
>>>>> +
>>>>> apps_smmu: iommu@c600000 {
>>>>> compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>>>>> reg = <0x0c600000 0x80000>;
>>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>>
>>
>>
>>
--
With best wishes
Dmitry
On Tue, 27 Jun 2023 22:14:15 +0200, Marijn Suijten wrote:
> Bring up the SM6125 DPU now that all preliminary series (such as INTF
> TE) have been merged (for me to test the hardware properly), and most
> other conflicting work (barring ongoing catalog *improvements*) has made
> its way in as well or is still being discussed.
>
> The second part of the series complements that by immediately utilizing
> this hardware in DT, and even enabling the MDSS/DSI nodes complete with
> a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II).
>
> [...]
Applied, thanks!
[05/15] dt-bindings: display/msm: dsi-controller-main: Document SM6125
https://gitlab.freedesktop.org/lumag/msm/-/commit/4d125651038a
[06/15] dt-bindings: display/msm: sc7180-dpu: Describe SM6125
https://gitlab.freedesktop.org/lumag/msm/-/commit/6321c42645b2
[07/15] dt-bindings: display/msm: Add SM6125 MDSS
https://gitlab.freedesktop.org/lumag/msm/-/commit/a628b5b16872
[08/15] drm/msm/dpu: Add SM6125 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/01077e7c890f
[09/15] drm/msm/mdss: Add SM6125 support
https://gitlab.freedesktop.org/lumag/msm/-/commit/c6da55b771de
[10/15] dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant
https://gitlab.freedesktop.org/lumag/msm/-/commit/d44ddd646858
[11/15] drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125
https://gitlab.freedesktop.org/lumag/msm/-/commit/ac2f330f92f2
Best regards,
--
Dmitry Baryshkov <[email protected]>
On 6/27/2023 1:14 PM, Marijn Suijten wrote:
> The regulator setup was likely copied from other SoCs by mistake. Just
> like SM6125 the DSI PHY on this platform is not getting power from a
> regulator but from the MX power domain.
>
> Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290")
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 --
> 1 file changed, 2 deletions(-)
>
Reviewed-by: Abhinav Kumar <[email protected]>
On Tue, 27 Jun 2023 22:14:15 +0200, Marijn Suijten wrote:
> Bring up the SM6125 DPU now that all preliminary series (such as INTF
> TE) have been merged (for me to test the hardware properly), and most
> other conflicting work (barring ongoing catalog *improvements*) has made
> its way in as well or is still being discussed.
>
> The second part of the series complements that by immediately utilizing
> this hardware in DT, and even enabling the MDSS/DSI nodes complete with
> a 6.0" 1080x2520 panel for Sony's Seine PDX201 (Xperia 10 II).
>
> [...]
Applied, thanks!
[01/15] drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config
https://gitlab.freedesktop.org/drm/msm/-/commit/97368254a08e
Best regards,
--
Abhinav Kumar <[email protected]>
On 2023-06-29 21:14:47, Konrad Dybcio wrote:
> On 29.06.2023 14:26, Dmitry Baryshkov wrote:
> > On Thu, 29 Jun 2023 at 15:09, Marijn Suijten
> > <[email protected]> wrote:
> >>
> >> On 2023-06-29 13:55:28, Dmitry Baryshkov wrote:
> >>> On 27/06/2023 23:14, Marijn Suijten wrote:
> >>>> We have a working RPM XO clock; no other driver except rpmcc should be
> >>>> parenting directly to the fixed-factor xo_board clock nor should it be
> >>>> reachable by that global name. Remove the name to that effect, so that
> >>>> every clock relation is explicitly defined in DTS.
> >>>>
> >>>> Reviewed-by: Konrad Dybcio <[email protected]>
> >>>> Signed-off-by: Marijn Suijten <[email protected]>
> >>>> ---
> >>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++---
> >>>> 1 file changed, 4 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> >>>> index 722dde560bec..edb03508dba3 100644
> >>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> >>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> >>>> @@ -22,7 +22,6 @@ xo_board: xo-board {
> >>>> compatible = "fixed-clock";
> >>>> #clock-cells = <0>;
> >>>> clock-frequency = <19200000>;
> >>>> - clock-output-names = "xo_board";
> >>>
> >>> Why? I'd say, leave it.
> >>
> >> The exact reason is explained in the commit message.
> >
> > Usually we do no not kill the xo_board name for the sake of anybody
> > still looking for the old name. Weak argument, I know.
> The only users are (rg -l '"xo_board"' drivers):
>
> drivers/clk/qcom/mmcc-msm8974.c
> drivers/clk/qcom/a53-pll.c
> drivers/clk/qcom/gcc-msm8974.c
> drivers/clk/qcom/clk-smd-rpm.c
> drivers/clk/qcom/mmcc-msm8996.c
> drivers/clk/qcom/gcc-msm8916.c
> drivers/clk/qcom/gcc-apq8084.c
> drivers/clk/qcom/gcc-msm8996.c
> drivers/clk/qcom/mmcc-apq8084.c
> drivers/clk/qcom/clk-rpmh.c
> drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
>
> This platform only binds clk-smd-rpm, but patch 11 provides a
> direct reference in the DT.
And following a quick check, those occurrences all have
.fw_name="xo",.name="xo_board", allowing the clock to be provided via
DT. For sm6125, I'd like it to be required like that: all dt-bindings
require an "xo" board where relevant, after all.
- Marijn
>
> Konrad
>
> >
> >>
> >>>
> >>> With that fixed:
> >>
> >> Hence I don't think it makes sense to "fix" this.
> >>
> >> - Marijn
> >>
> >>> Reviewed-by: Dmitry Baryshkov <[email protected]>
> >
> >
> >
On 2023-06-29 13:54:13, Dmitry Baryshkov wrote:
> On 27/06/2023 23:14, Marijn Suijten wrote:
> > Document availability of the 14nm DSI PHY on SM6125. Note that this
> > compatible uses the SoC-suffix variant, intead of postfixing an
> > arbitrary number without the sm/sdm portion. The PHY is not powered by
> > a vcca regulator like on most SoCs, but by the MX power domain that is
> > provided via the power-domains property and a single corresponding
> > required-opps.
> >
> > Acked-by: Krzysztof Kozlowski <[email protected]>
> > Signed-off-by: Marijn Suijten <[email protected]>
> > ---
> > .../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > index a43e11d3b00d..183a26f8a6dc 100644
> > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> > @@ -19,6 +19,7 @@ properties:
> > - qcom,dsi-phy-14nm-2290
> > - qcom,dsi-phy-14nm-660
> > - qcom,dsi-phy-14nm-8953
> > + - qcom,sm6125-dsi-phy-14nm
> >
> > reg:
> > items:
> > @@ -35,6 +36,16 @@ properties:
> > vcca-supply:
> > description: Phandle to vcca regulator device node.
> >
> > + power-domains:
> > + description:
> > + A phandle and PM domain specifier for an optional power domain.
> > + maxItems: 1
> > +
> > + required-opps:
> > + description:
> > + A phandle to an OPP node describing an optional performance point.
>
> I'd rephrase this to be something more exact, like 'desribing power
> domain's performance point'.
Sure. I'll leave out the word "optional", that becomes obvious from
maxItems:1 without minItems, together with referencing a PM which itself
is already optional.
- Marijn
> > + maxItems: 1
> > +
> > required:
> > - compatible
> > - reg
> >
>
> --
> With best wishes
> Dmitry
>
On 19/07/2023 00:00, Marijn Suijten wrote:
> On 2023-06-29 13:54:13, Dmitry Baryshkov wrote:
>> On 27/06/2023 23:14, Marijn Suijten wrote:
>>> Document availability of the 14nm DSI PHY on SM6125. Note that this
>>> compatible uses the SoC-suffix variant, intead of postfixing an
>>> arbitrary number without the sm/sdm portion. The PHY is not powered by
>>> a vcca regulator like on most SoCs, but by the MX power domain that is
>>> provided via the power-domains property and a single corresponding
>>> required-opps.
>>>
>>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>> Signed-off-by: Marijn Suijten <[email protected]>
>>> ---
>>> .../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>> index a43e11d3b00d..183a26f8a6dc 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
>>> @@ -19,6 +19,7 @@ properties:
>>> - qcom,dsi-phy-14nm-2290
>>> - qcom,dsi-phy-14nm-660
>>> - qcom,dsi-phy-14nm-8953
>>> + - qcom,sm6125-dsi-phy-14nm
>>>
>>> reg:
>>> items:
>>> @@ -35,6 +36,16 @@ properties:
>>> vcca-supply:
>>> description: Phandle to vcca regulator device node.
>>>
>>> + power-domains:
>>> + description:
>>> + A phandle and PM domain specifier for an optional power domain.
>>> + maxItems: 1
>>> +
>>> + required-opps:
>>> + description:
>>> + A phandle to an OPP node describing an optional performance point.
>>
>> I'd rephrase this to be something more exact, like 'desribing power
>> domain's performance point'.
>
> Sure. I'll leave out the word "optional", that becomes obvious from
> maxItems:1 without minItems, together with referencing a PM which itself
> is already optional.
no, default minItems is equal to maxItems. It is not listing this
property under the required what makes it optional.
>
> - Marijn
>
>>> + maxItems: 1
>>> +
>>> required:
>>> - compatible
>>> - reg
>>>
>>
>> --
>> With best wishes
>> Dmitry
>>
--
With best wishes
Dmitry
On 2023-07-19 01:01:54, Dmitry Baryshkov wrote:
> On 19/07/2023 00:00, Marijn Suijten wrote:
> > On 2023-06-29 13:54:13, Dmitry Baryshkov wrote:
> >> On 27/06/2023 23:14, Marijn Suijten wrote:
> >>> Document availability of the 14nm DSI PHY on SM6125. Note that this
> >>> compatible uses the SoC-suffix variant, intead of postfixing an
> >>> arbitrary number without the sm/sdm portion. The PHY is not powered by
> >>> a vcca regulator like on most SoCs, but by the MX power domain that is
> >>> provided via the power-domains property and a single corresponding
> >>> required-opps.
> >>>
> >>> Acked-by: Krzysztof Kozlowski <[email protected]>
> >>> Signed-off-by: Marijn Suijten <[email protected]>
> >>> ---
> >>> .../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++
> >>> 1 file changed, 11 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> >>> index a43e11d3b00d..183a26f8a6dc 100644
> >>> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> >>> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> >>> @@ -19,6 +19,7 @@ properties:
> >>> - qcom,dsi-phy-14nm-2290
> >>> - qcom,dsi-phy-14nm-660
> >>> - qcom,dsi-phy-14nm-8953
> >>> + - qcom,sm6125-dsi-phy-14nm
> >>>
> >>> reg:
> >>> items:
> >>> @@ -35,6 +36,16 @@ properties:
> >>> vcca-supply:
> >>> description: Phandle to vcca regulator device node.
> >>>
> >>> + power-domains:
> >>> + description:
> >>> + A phandle and PM domain specifier for an optional power domain.
> >>> + maxItems: 1
> >>> +
> >>> + required-opps:
> >>> + description:
> >>> + A phandle to an OPP node describing an optional performance point.
> >>
> >> I'd rephrase this to be something more exact, like 'desribing power
> >> domain's performance point'.
> >
> > Sure. I'll leave out the word "optional", that becomes obvious from
> > maxItems:1 without minItems, together with referencing a PM which itself
> > is already optional.
>
> no, default minItems is equal to maxItems. It is not listing this
> property under the required what makes it optional.
I thought it was both.
Magic.
- Marijn