This patch series fixes introduce support for msm8976 pll,
also brings some adjustments and fixes domains setup and few dts nitpicks.
Adam Skladowski (7):
drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup
clk: qcom: clk-hfpll: Configure l_val in init when required
clk: qcom: hfpll: Allow matching pdata
dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles
clk: qcom: hfpll: Add MSM8976 PLL data
arm64: dts: qcom: msm8976: Split lpass region
arm64: dts: qcom: msm8976: Fix smsm ipc bit shifts
.../devicetree/bindings/clock/qcom,hfpll.txt | 3 +
arch/arm64/boot/dts/qcom/msm8976.dtsi | 11 +++-
drivers/clk/qcom/clk-hfpll.c | 4 ++
drivers/clk/qcom/clk-hfpll.h | 1 +
drivers/clk/qcom/hfpll.c | 59 ++++++++++++++++++-
drivers/soc/qcom/rpmpd.c | 25 +++-----
6 files changed, 82 insertions(+), 21 deletions(-)
--
2.41.0
Downstream kernel parses resource names based on pm8950-rpm-regulator.dtsi
in such file qcom,resource-name takes three values: smpa,ldoa and clk0.
First appearance of RWSC/RWSM point to msm-4.4 kernel
which is way newer than what this platform was shipped with (msm-3.10).
For the max_state downstream code limit value to TURBO inside dts
with only one turbo_high being placed in msm-thermal bindings.
One of effects of requesting TURBO_HIGH vote is rebooting of device
which happens during voting inside WCNSS/IRIS,
this behavior was observed on LeEco S2 smartphone.
Fix regulator setup and drop unused resources.
Signed-off-by: Adam Skladowski <[email protected]>
---
drivers/soc/qcom/rpmpd.c | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 3135dd1dafe0..69bc7c4d0ace 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -166,13 +166,6 @@ static struct rpmpd cx_rwcx0_vfl = {
.key = KEY_FLOOR_LEVEL,
};
-static struct rpmpd cx_rwsc2_vfl = {
- .pd = { .name = "cx_vfl", },
- .res_type = RPMPD_RWSC,
- .res_id = 2,
- .key = KEY_FLOOR_LEVEL,
-};
-
static struct rpmpd cx_s1a_vfc = {
.pd = { .name = "cx_vfc", },
.res_type = RPMPD_SMPA,
@@ -328,6 +321,12 @@ static struct rpmpd mx_s6a_lvl_ao = {
.res_id = 6,
.key = KEY_LEVEL,
};
+static struct rpmpd mx_s6a_vfl = {
+ .pd = { .name = "mx_vfl", },
+ .res_type = RPMPD_SMPA,
+ .res_id = 6,
+ .key = KEY_FLOOR_LEVEL,
+};
static struct rpmpd mx_s7a_lvl_ao;
static struct rpmpd mx_s7a_lvl = {
@@ -361,12 +360,6 @@ static struct rpmpd mx_rwmx0_vfl = {
.key = KEY_FLOOR_LEVEL,
};
-static struct rpmpd mx_rwsm6_vfl = {
- .pd = { .name = "mx_vfl", },
- .res_type = RPMPD_RWSM,
- .res_id = 6,
- .key = KEY_FLOOR_LEVEL,
-};
/* MD */
static struct rpmpd md_s1a_corner_ao;
@@ -591,16 +584,16 @@ static const struct rpmpd_desc msm8953_desc = {
static struct rpmpd *msm8976_rpmpds[] = {
[MSM8976_VDDCX] = &cx_s2a_lvl,
[MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao,
- [MSM8976_VDDCX_VFL] = &cx_rwsc2_vfl,
+ [MSM8976_VDDCX_VFL] = &cx_s2a_vfl,
[MSM8976_VDDMX] = &mx_s6a_lvl,
[MSM8976_VDDMX_AO] = &mx_s6a_lvl_ao,
- [MSM8976_VDDMX_VFL] = &mx_rwsm6_vfl,
+ [MSM8976_VDDMX_VFL] = &mx_s6a_vfl,
};
static const struct rpmpd_desc msm8976_desc = {
.rpmpds = msm8976_rpmpds,
.num_pds = ARRAY_SIZE(msm8976_rpmpds),
- .max_state = RPM_SMD_LEVEL_TURBO_HIGH,
+ .max_state = RPM_SMD_LEVEL_TURBO,
};
static struct rpmpd *msm8994_rpmpds[] = {
--
2.41.0
Add support for pre-configuring default frequency multiplier,
this appears to be required on some platforms like MSM8976.
Without configuring L_VAL device reboots when trying to bring PLL up.
Signed-off-by: Adam Skladowski <[email protected]>
---
drivers/clk/qcom/clk-hfpll.c | 4 ++++
drivers/clk/qcom/clk-hfpll.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
index 86f728dc69e5..a93b1493c882 100644
--- a/drivers/clk/qcom/clk-hfpll.c
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -44,6 +44,10 @@ static void __clk_hfpll_init_once(struct clk_hw *hw)
regmap_write(regmap, hd->user_reg, regval);
}
+ /* Write L_VAL from conf if it exist */
+ if (hd->l_val)
+ regmap_write(regmap, hd->l_reg, hd->l_val);
+
if (hd->droop_reg)
regmap_write(regmap, hd->droop_reg, hd->droop_val);
diff --git a/drivers/clk/qcom/clk-hfpll.h b/drivers/clk/qcom/clk-hfpll.h
index 2a57b2fb2f2f..27b9effcb3fd 100644
--- a/drivers/clk/qcom/clk-hfpll.h
+++ b/drivers/clk/qcom/clk-hfpll.h
@@ -18,6 +18,7 @@ struct hfpll_data {
u32 status_reg;
u8 lock_bit;
+ u32 l_val;
u32 droop_val;
u32 config_val;
u32 user_val;
--
2.41.0
Update bits to match downstream irq-bitmask values.
Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs")
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 7385d5edec04..5537ec049451 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -433,9 +433,9 @@ smsm {
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 12>;
+ qcom,ipc-1 = <&apcs 8 13>;
qcom,ipc-2 = <&apcs 8 9>;
- qcom,ipc-3 = <&apcs 8 18>;
+ qcom,ipc-3 = <&apcs 8 19>;
apps_smsm: apps@0 {
reg = <0>;
--
2.41.0
HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976
On MSM8976 each PLL gets it own different configuration,
add matching pdata to driver to support multiple configurations.
Signed-off-by: Adam Skladowski <[email protected]>
---
drivers/clk/qcom/hfpll.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index f4d78003d189..ec18bc8f0089 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -6,6 +6,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
@@ -32,7 +33,7 @@ static const struct hfpll_data hdata = {
};
static const struct of_device_id qcom_hfpll_match_table[] = {
- { .compatible = "qcom,hfpll" },
+ { .compatible = "qcom,hfpll", &hdata },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
@@ -83,7 +84,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
init.parent_data = &pdata;
- h->d = &hdata;
+ h->d = of_device_get_match_data(&pdev->dev);
h->clkr.hw.init = &init;
spin_lock_init(&h->lock);
--
2.41.0
Document MSM8976 HFPLL compatibles.
Signed-off-by: Adam Skladowski <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,hfpll.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
index ec02a024424c..855344957350 100644
--- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
@@ -11,6 +11,9 @@ PROPERTIES
"qcom,hfpll-ipq8064", "qcom,hfpll"
"qcom,hfpll-apq8064", "qcom,hfpll"
"qcom,hfpll-msm8974", "qcom,hfpll"
+ "qcom,hfpll-msm8976-a53", "qcom,hfpll"
+ "qcom,hfpll-msm8976-a72", "qcom,hfpll"
+ "qcom,hfpll-msm8976-cci", "qcom,hfpll"
"qcom,hfpll-msm8960", "qcom,hfpll"
- reg:
--
2.41.0
Some devices like Sony Loire uses Broadcom module over sdc3 however others
utilize qcom WCNSS, split shared region based on downstream pil-tz loader.
Signed-off-by: Adam Skladowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8976.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index ab76806317a7..7385d5edec04 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -338,7 +338,12 @@ mpss_mem: mpss@86c00000 {
};
lpass_mem: lpass@8c200000 {
- reg = <0x0 0x8c200000 0x0 0x1800000>;
+ reg = <0x0 0x8c200000 0x0 0x1000000>;
+ no-map;
+ };
+
+ wcnss_fw_mem: wcnss@8d200000 {
+ reg = <0x0 0x8d200000 0x0 0x800000>;
no-map;
};
--
2.41.0
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
For simplicity only add second range as smaller frequencies can be obtained
via apcs divider or safe parent this also saves us
a hassle of reconfiguring VCO bit and config_val.
A72 and CCI cluster only use single frequency range with their
outputs/post_dividers/vco_bits being static.
Signed-off-by: Adam Skladowski <[email protected]>
---
drivers/clk/qcom/hfpll.c | 54 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index ec18bc8f0089..a9c4c77e0f50 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -32,8 +32,62 @@ static const struct hfpll_data hdata = {
.max_rate = 2900000000UL,
};
+static const struct hfpll_data msm8976_a53 = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x341600,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x35,
+ .user_val = 0x109,
+ .min_rate = 902400000UL,
+ .max_rate = 1478400000UL,
+};
+
+static const struct hfpll_data msm8976_a72 = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x4e0405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x3e,
+ .user_val = 0x100109,
+ .min_rate = 940800000UL,
+ .max_rate = 1843200000UL,
+};
+
+static const struct hfpll_data msm8976_cci = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x141400,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x20,
+ .user_val = 0x100109,
+ .min_rate = 556800000UL,
+ .max_rate = 902400000UL,
+};
+
static const struct of_device_id qcom_hfpll_match_table[] = {
{ .compatible = "qcom,hfpll", &hdata },
+ { .compatible = "qcom,hfpll-msm8976-a53", &msm8976_a53 },
+ { .compatible = "qcom,hfpll-msm8976-a72", &msm8976_a72 },
+ { .compatible = "qcom,hfpll-msm8976-cci", &msm8976_cci },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
--
2.41.0
On 23/07/2023 16:06, Adam Skladowski wrote:
> Document MSM8976 HFPLL compatibles.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/qcom,hfpll.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
> index ec02a024424c..855344957350 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
> @@ -11,6 +11,9 @@ PROPERTIES
> "qcom,hfpll-ipq8064", "qcom,hfpll"
> "qcom,hfpll-apq8064", "qcom,hfpll"
> "qcom,hfpll-msm8974", "qcom,hfpll"
> + "qcom,hfpll-msm8976-a53", "qcom,hfpll"
> + "qcom,hfpll-msm8976-a72", "qcom,hfpll"
> + "qcom,hfpll-msm8976-cci", "qcom,hfpll"
Let's switch to proper format, because this is not getting mess, so:
qcom,msm8976-hfpll-a53
Best regards,
Krzysztof
On 2023-07-23 16:06:54, Adam Skladowski wrote:
> Update bits to match downstream irq-bitmask values.
> Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs")
>
This whitespace should be the other way around. And Fixes: patches
should typically be at the beginning of the series to show that they do
are independent of the rest of the series.
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 7385d5edec04..5537ec049451 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -433,9 +433,9 @@ smsm {
> #address-cells = <1>;
> #size-cells = <0>;
>
> - qcom,ipc-1 = <&apcs 8 12>;
> + qcom,ipc-1 = <&apcs 8 13>;
This now overlaps with smp2p-modem which also has 13, but should be 14
according to my downstream 8956 sources:
qcom,irq-bitmask = <0x4000>;
> qcom,ipc-2 = <&apcs 8 9>;
> - qcom,ipc-3 = <&apcs 8 18>;
> + qcom,ipc-3 = <&apcs 8 19>;
And for wcnss the smp2p-wcnss node in mainline currently has 17 but that
mask (0x20000) is used downstream for smd-wcnss; smp2p-wcnss downstream
has 0x40000 equalling a shift of 18. Perhaps more apcs ipc references
need to be fixed before this is complete?
- Marijn
>
> apps_smsm: apps@0 {
> reg = <0>;
> --
> 2.41.0
>
Il 23/07/23 16:06, Adam Skladowski ha scritto:
> Downstream kernel parses resource names based on pm8950-rpm-regulator.dtsi
> in such file qcom,resource-name takes three values: smpa,ldoa and clk0.
> First appearance of RWSC/RWSM point to msm-4.4 kernel
Are we sure that RWSC/RWSM being present isn't firmware-related?
What is the observed issue, why are you removing RWSC/RWSM and what did you
solve with that?
If it's just about dropping unused resources, that may be unused only on
firmware versions older than "X".
> which is way newer than what this platform was shipped with (msm-3.10).
> For the max_state downstream code limit value to TURBO inside dts
> with only one turbo_high being placed in msm-thermal bindings.
> One of effects of requesting TURBO_HIGH vote is rebooting of device
> which happens during voting inside WCNSS/IRIS,
> this behavior was observed on LeEco S2 smartphone.
> Fix regulator setup and drop unused resources.
That's fine, but you're missing a Fixes tag, which is required, being this a fix.
Regards,
Angelo
Il 23/07/23 16:06, Adam Skladowski ha scritto:
> HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976
> On MSM8976 each PLL gets it own different configuration,
> add matching pdata to driver to support multiple configurations.
>
> Signed-off-by: Adam Skladowski <[email protected]>
> ---
> drivers/clk/qcom/hfpll.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index f4d78003d189..ec18bc8f0089 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -6,6 +6,7 @@
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/regmap.h>
> @@ -32,7 +33,7 @@ static const struct hfpll_data hdata = {
> };
>
> static const struct of_device_id qcom_hfpll_match_table[] = {
> - { .compatible = "qcom,hfpll" },
> + { .compatible = "qcom,hfpll", &hdata },
This is supposed to be
{ .compatible = xxx, .data = &hdata }
Regards,
Angelo
> { }
> };
> MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
> @@ -83,7 +84,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>
> init.parent_data = &pdata;
>
> - h->d = &hdata;
> + h->d = of_device_get_match_data(&pdev->dev);
> h->clkr.hw.init = &init;
> spin_lock_init(&h->lock);
>
Il 23/07/23 16:06, Adam Skladowski ha scritto:
> Some devices like Sony Loire uses Broadcom module over sdc3 however others
> utilize qcom WCNSS, split shared region based on downstream pil-tz loader.
>
> Signed-off-by: Adam Skladowski <[email protected]>
That should go in board specific files, not in the SoC dtsi.
Regards,
Angelo