This series allows the CCU core and drivers to be loaded/unloaded as
modules. As part of this, patch 3 converts most of the early OF clock
providers to platform drivers.
Changes in v3:
- Also export helper functions.
Changes in v2:
- Export symbols to the SUNXI_CCU namespace.
Changes in v1:
- Patches 1-3 of 8 were merged.
- Name modules using Makefile logic, not by renaming the source files.
(Drop patch 4 of 8.)
Samuel Holland (4):
clk: sunxi-ng: Export symbols used by CCU drivers
clk: sunxi-ng: Allow drivers to be built as modules
clk: sunxi-ng: Convert early providers to platform drivers
clk: sunxi-ng: Allow the CCU core to be built as a module
drivers/clk/Makefile | 2 +-
drivers/clk/sunxi-ng/Kconfig | 39 +++++-----
drivers/clk/sunxi-ng/Makefile | 97 +++++++++++++++---------
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 ++++++++------
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 4 +-
drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 4 +-
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 7 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 +++++++++-----
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 7 +-
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 +++++---
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++---
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 ++++++---
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 7 +-
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 9 ++-
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++-----
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 +++++++++-------
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 6 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 ++++++++------
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 7 +-
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 7 +-
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 7 +-
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 +++++++---
drivers/clk/sunxi-ng/ccu_common.c | 6 ++
drivers/clk/sunxi-ng/ccu_div.c | 1 +
drivers/clk/sunxi-ng/ccu_frac.c | 6 ++
drivers/clk/sunxi-ng/ccu_gate.c | 4 +
drivers/clk/sunxi-ng/ccu_mp.c | 2 +
drivers/clk/sunxi-ng/ccu_mult.c | 1 +
drivers/clk/sunxi-ng/ccu_mux.c | 6 ++
drivers/clk/sunxi-ng/ccu_nk.c | 1 +
drivers/clk/sunxi-ng/ccu_nkm.c | 1 +
drivers/clk/sunxi-ng/ccu_nkmp.c | 1 +
drivers/clk/sunxi-ng/ccu_nm.c | 1 +
drivers/clk/sunxi-ng/ccu_phase.c | 1 +
drivers/clk/sunxi-ng/ccu_reset.c | 1 +
drivers/clk/sunxi-ng/ccu_sdm.c | 6 ++
drivers/mmc/host/Kconfig | 1 +
include/linux/clk/sunxi-ng.h | 15 ----
39 files changed, 490 insertions(+), 251 deletions(-)
--
2.32.0
For the individual CCU drivers to be built as modules, the ops structs,
helper functions, and callback registration functions must be exported.
These symbols are intended for use only by the adjacent CCU drivers, so
export them into the SUNXI_CCU namespace.
of_sunxi_ccu_probe is not exported because it is only used by built-in
OF clock providers.
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v3:
- Also export helper functions.
Changes in v2:
- Export symbols to the SUNXI_CCU namespace.
drivers/clk/sunxi-ng/ccu_common.c | 3 +++
drivers/clk/sunxi-ng/ccu_div.c | 1 +
drivers/clk/sunxi-ng/ccu_frac.c | 6 ++++++
drivers/clk/sunxi-ng/ccu_gate.c | 4 ++++
drivers/clk/sunxi-ng/ccu_mp.c | 2 ++
drivers/clk/sunxi-ng/ccu_mult.c | 1 +
drivers/clk/sunxi-ng/ccu_mux.c | 6 ++++++
drivers/clk/sunxi-ng/ccu_nk.c | 1 +
drivers/clk/sunxi-ng/ccu_nkm.c | 1 +
drivers/clk/sunxi-ng/ccu_nkmp.c | 1 +
drivers/clk/sunxi-ng/ccu_nm.c | 1 +
drivers/clk/sunxi-ng/ccu_phase.c | 1 +
drivers/clk/sunxi-ng/ccu_reset.c | 1 +
drivers/clk/sunxi-ng/ccu_sdm.c | 6 ++++++
14 files changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 31af8b6b5286..6afdedbce6a2 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -36,6 +36,7 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
}
+EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU);
/*
* This clock notifier is called when the frequency of a PLL clock is
@@ -83,6 +84,7 @@ int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
return clk_notifier_register(pll_nb->common->hw.clk,
&pll_nb->clk_nb);
}
+EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev,
struct device_node *node, void __iomem *reg,
@@ -194,6 +196,7 @@ int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg,
return 0;
}
+EXPORT_SYMBOL_NS_GPL(devm_sunxi_ccu_probe, SUNXI_CCU);
void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
const struct sunxi_ccu_desc *desc)
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 4c297089483c..cb10a3ea23f9 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -141,3 +141,4 @@ const struct clk_ops ccu_div_ops = {
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_div_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_div_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
index 44fcded8b354..b31f3ad946d6 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.c
+++ b/drivers/clk/sunxi-ng/ccu_frac.c
@@ -18,6 +18,7 @@ bool ccu_frac_helper_is_enabled(struct ccu_common *common,
return !(readl(common->base + common->reg) & cf->enable);
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_is_enabled, SUNXI_CCU);
void ccu_frac_helper_enable(struct ccu_common *common,
struct ccu_frac_internal *cf)
@@ -33,6 +34,7 @@ void ccu_frac_helper_enable(struct ccu_common *common,
writel(reg & ~cf->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_enable, SUNXI_CCU);
void ccu_frac_helper_disable(struct ccu_common *common,
struct ccu_frac_internal *cf)
@@ -48,6 +50,7 @@ void ccu_frac_helper_disable(struct ccu_common *common,
writel(reg | cf->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_disable, SUNXI_CCU);
bool ccu_frac_helper_has_rate(struct ccu_common *common,
struct ccu_frac_internal *cf,
@@ -58,6 +61,7 @@ bool ccu_frac_helper_has_rate(struct ccu_common *common,
return (cf->rates[0] == rate) || (cf->rates[1] == rate);
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_has_rate, SUNXI_CCU);
unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
struct ccu_frac_internal *cf)
@@ -79,6 +83,7 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_read_rate, SUNXI_CCU);
int ccu_frac_helper_set_rate(struct ccu_common *common,
struct ccu_frac_internal *cf,
@@ -107,3 +112,4 @@ int ccu_frac_helper_set_rate(struct ccu_common *common,
return 0;
}
+EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_set_rate, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_gate.c
index 3d5ca092b08f..a2115a21807d 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.c
+++ b/drivers/clk/sunxi-ng/ccu_gate.c
@@ -24,6 +24,7 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
spin_unlock_irqrestore(common->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_disable, SUNXI_CCU);
static void ccu_gate_disable(struct clk_hw *hw)
{
@@ -49,6 +50,7 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
return 0;
}
+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_enable, SUNXI_CCU);
static int ccu_gate_enable(struct clk_hw *hw)
{
@@ -64,6 +66,7 @@ int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate)
return readl(common->base + common->reg) & gate;
}
+EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_is_enabled, SUNXI_CCU);
static int ccu_gate_is_enabled(struct clk_hw *hw)
{
@@ -124,3 +127,4 @@ const struct clk_ops ccu_gate_ops = {
.set_rate = ccu_gate_set_rate,
.recalc_rate = ccu_gate_recalc_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_gate_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 9d3a76604d94..57cf2d615148 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -245,6 +245,7 @@ const struct clk_ops ccu_mp_ops = {
.recalc_rate = ccu_mp_recalc_rate,
.set_rate = ccu_mp_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, SUNXI_CCU);
/*
* Support for MMC timing mode switching
@@ -325,3 +326,4 @@ const struct clk_ops ccu_mp_mmc_ops = {
.recalc_rate = ccu_mp_mmc_recalc_rate,
.set_rate = ccu_mp_mmc_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 7c8cf2e04e94..7bee217ef111 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -170,3 +170,4 @@ const struct clk_ops ccu_mult_ops = {
.recalc_rate = ccu_mult_recalc_rate,
.set_rate = ccu_mult_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_mult_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 7d75da9a1f2e..2306a1cd83e4 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -64,6 +64,7 @@ unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
{
return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
}
+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_apply_prediv, SUNXI_CCU);
static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
@@ -152,6 +153,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
req->rate = best_rate;
return 0;
}
+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_determine_rate, SUNXI_CCU);
u8 ccu_mux_helper_get_parent(struct ccu_common *common,
struct ccu_mux_internal *cm)
@@ -174,6 +176,7 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
return parent;
}
+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_get_parent, SUNXI_CCU);
int ccu_mux_helper_set_parent(struct ccu_common *common,
struct ccu_mux_internal *cm,
@@ -195,6 +198,7 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
return 0;
}
+EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_set_parent, SUNXI_CCU);
static void ccu_mux_disable(struct clk_hw *hw)
{
@@ -251,6 +255,7 @@ const struct clk_ops ccu_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.recalc_rate = ccu_mux_recalc_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
/*
* This clock notifier is called when the frequency of the of the parent
@@ -285,3 +290,4 @@ int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
return clk_notifier_register(clk, &mux_nb->clk_nb);
}
+EXPORT_SYMBOL_NS_GPL(ccu_mux_notifier_register, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index aee68b00f3b2..c4fb82af97e8 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -157,3 +157,4 @@ const struct clk_ops ccu_nk_ops = {
.round_rate = ccu_nk_round_rate,
.set_rate = ccu_nk_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_nk_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index b9cfee0276ea..67da2c189b53 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -206,3 +206,4 @@ const struct clk_ops ccu_nkm_ops = {
.recalc_rate = ccu_nkm_recalc_rate,
.set_rate = ccu_nkm_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_nkm_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index bda87b38c45c..39413cb0985c 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -230,3 +230,4 @@ const struct clk_ops ccu_nkmp_ops = {
.round_rate = ccu_nkmp_round_rate,
.set_rate = ccu_nkmp_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_nkmp_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index e6bcc0a7170c..9ca9257f4426 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -238,3 +238,4 @@ const struct clk_ops ccu_nm_ops = {
.round_rate = ccu_nm_round_rate,
.set_rate = ccu_nm_set_rate,
};
+EXPORT_SYMBOL_NS_GPL(ccu_nm_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/clk/sunxi-ng/ccu_phase.c
index 92ab8bd66427..e4cae2afe9db 100644
--- a/drivers/clk/sunxi-ng/ccu_phase.c
+++ b/drivers/clk/sunxi-ng/ccu_phase.c
@@ -121,3 +121,4 @@ const struct clk_ops ccu_phase_ops = {
.get_phase = ccu_phase_get_phase,
.set_phase = ccu_phase_set_phase,
};
+EXPORT_SYMBOL_NS_GPL(ccu_phase_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_reset.c b/drivers/clk/sunxi-ng/ccu_reset.c
index 483100e45df3..6577aa18cb01 100644
--- a/drivers/clk/sunxi-ng/ccu_reset.c
+++ b/drivers/clk/sunxi-ng/ccu_reset.c
@@ -75,3 +75,4 @@ const struct reset_control_ops ccu_reset_ops = {
.reset = ccu_reset_reset,
.status = ccu_reset_status,
};
+EXPORT_SYMBOL_NS_GPL(ccu_reset_ops, SUNXI_CCU);
diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c
index 79581a1c649a..41937ed0766d 100644
--- a/drivers/clk/sunxi-ng/ccu_sdm.c
+++ b/drivers/clk/sunxi-ng/ccu_sdm.c
@@ -20,6 +20,7 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, SUNXI_CCU);
void ccu_sdm_helper_enable(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
@@ -49,6 +50,7 @@ void ccu_sdm_helper_enable(struct ccu_common *common,
writel(reg | sdm->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, SUNXI_CCU);
void ccu_sdm_helper_disable(struct ccu_common *common,
struct ccu_sdm_internal *sdm)
@@ -69,6 +71,7 @@ void ccu_sdm_helper_disable(struct ccu_common *common,
writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
spin_unlock_irqrestore(common->lock, flags);
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, SUNXI_CCU);
/*
* Sigma delta modulation provides a way to do fractional-N frequency
@@ -102,6 +105,7 @@ bool ccu_sdm_helper_has_rate(struct ccu_common *common,
return false;
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_has_rate, SUNXI_CCU);
unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
@@ -132,6 +136,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
/* We can't calculate the effective clock rate, so just fail. */
return 0;
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_read_rate, SUNXI_CCU);
int ccu_sdm_helper_get_factors(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
@@ -153,3 +158,4 @@ int ccu_sdm_helper_get_factors(struct ccu_common *common,
/* nothing found */
return -EINVAL;
}
+EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_get_factors, SUNXI_CCU);
--
2.32.0
While it is useful to build all of the CCU drivers at once, only 1-3 of
them will be loaded at a time, or possibly none of them if the kernel is
booted on a non-sunxi platform. These CCU drivers are relatively large;
32-bit drivers have 30-50k of data each, while the 64-bit ones are
50-75k due to the increased pointer overhead. About half of that data
comes from relocations. Let's allow the user to build these drivers as
modules so only the necessary data is loaded.
As a first step, convert the CCUs that are already platform drivers.
When the drivers are built as modules, normally the file name becomes
the module name. However, the current file names are inconsistent with
the <platform>-<peripheral> name used everywhere else: the devicetree
bindings, the platform driver names, and the Kconfig symbols. Use
Makfile logic to rename the modules so they follow the usual pattern.
Signed-off-by: Samuel Holland <[email protected]>
---
(no changes since v1)
drivers/clk/sunxi-ng/Kconfig | 16 +++---
drivers/clk/sunxi-ng/Makefile | 64 ++++++++++++++++--------
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 4 +-
drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 4 +-
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 7 ++-
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 7 ++-
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 7 ++-
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 9 ++--
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 6 ++-
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 7 ++-
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 7 ++-
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 7 ++-
12 files changed, 98 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index e76e1676f0f0..c004ffc10ef7 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -13,22 +13,22 @@ config SUNIV_F1C100S_CCU
depends on MACH_SUNIV || COMPILE_TEST
config SUN50I_A64_CCU
- bool "Support for the Allwinner A64 CCU"
+ tristate "Support for the Allwinner A64 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_A100_CCU
- bool "Support for the Allwinner A100 CCU"
+ tristate "Support for the Allwinner A100 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_A100_R_CCU
- bool "Support for the Allwinner A100 PRCM CCU"
+ tristate "Support for the Allwinner A100 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_CCU
- bool "Support for the Allwinner H6 CCU"
+ tristate "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
@@ -69,7 +69,7 @@ config SUN8I_A33_CCU
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_A83T_CCU
- bool "Support for the Allwinner A83T CCU"
+ tristate "Support for the Allwinner A83T CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
@@ -84,16 +84,16 @@ config SUN8I_V3S_CCU
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_DE2_CCU
- bool "Support for the Allwinner SoCs DE2 CCU"
+ tristate "Support for the Allwinner SoCs DE2 CCU"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
config SUN8I_R40_CCU
- bool "Support for the Allwinner R40 CCU"
+ tristate "Support for the Allwinner R40 CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
config SUN9I_A80_CCU
- bool "Support for the Allwinner A80 CCU"
+ tristate "Support for the Allwinner A80 CCU"
default MACH_SUN9I
depends on MACH_SUN9I || COMPILE_TEST
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 96c324306d97..1020ed49a588 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -21,24 +21,46 @@ obj-y += ccu_nm.o
obj-y += ccu_mp.o
# SoC support
-obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
-obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
-obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
-obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
-obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
-obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
-obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
-obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
-obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
-obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
-obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
-obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
-obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
-obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
-obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
-obj-$(CONFIG_SUN8I_DE2_CCU) += ccu-sun8i-de2.o
-obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
-obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o
-obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
-obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
-obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
+obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
+obj-$(CONFIG_SUN50I_A64_CCU) += sun50i-a64-ccu.o
+obj-$(CONFIG_SUN50I_A100_CCU) += sun50i-a100-ccu.o
+obj-$(CONFIG_SUN50I_A100_R_CCU) += sun50i-a100-r-ccu.o
+obj-$(CONFIG_SUN50I_H6_CCU) += sun50i-h6-ccu.o
+obj-$(CONFIG_SUN50I_H6_R_CCU) += sun50i-h6-r-ccu.o
+obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
+obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
+obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
+obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
+obj-$(CONFIG_SUN8I_A23_CCU) += sun8i-a23-ccu.o
+obj-$(CONFIG_SUN8I_A33_CCU) += sun8i-a33-ccu.o
+obj-$(CONFIG_SUN8I_A83T_CCU) += sun8i-a83t-ccu.o
+obj-$(CONFIG_SUN8I_H3_CCU) += sun8i-h3-ccu.o
+obj-$(CONFIG_SUN8I_R40_CCU) += sun8i-r40-ccu.o
+obj-$(CONFIG_SUN8I_V3S_CCU) += sun8i-v3s-ccu.o
+obj-$(CONFIG_SUN8I_DE2_CCU) += sun8i-de2-ccu.o
+obj-$(CONFIG_SUN8I_R_CCU) += sun8i-r-ccu.o
+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-ccu.o
+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-de-ccu.o
+obj-$(CONFIG_SUN9I_A80_CCU) += sun9i-a80-usb-ccu.o
+
+suniv-f1c100s-ccu-y += ccu-suniv-f1c100s.o
+sun50i-a64-ccu-y += ccu-sun50i-a64.o
+sun50i-a100-ccu-y += ccu-sun50i-a100.o
+sun50i-a100-r-ccu-y += ccu-sun50i-a100-r.o
+sun50i-h6-ccu-y += ccu-sun50i-h6.o
+sun50i-h6-r-ccu-y += ccu-sun50i-h6-r.o
+sun50i-h616-ccu-y += ccu-sun50i-h616.o
+sun4i-a10-ccu-y += ccu-sun4i-a10.o
+sun5i-ccu-y += ccu-sun5i.o
+sun6i-a31-ccu-y += ccu-sun6i-a31.o
+sun8i-a23-ccu-y += ccu-sun8i-a23.o
+sun8i-a33-ccu-y += ccu-sun8i-a33.o
+sun8i-a83t-ccu-y += ccu-sun8i-a83t.o
+sun8i-h3-ccu-y += ccu-sun8i-h3.o
+sun8i-r40-ccu-y += ccu-sun8i-r40.o
+sun8i-v3s-ccu-y += ccu-sun8i-v3s.o
+sun8i-de2-ccu-y += ccu-sun8i-de2.o
+sun8i-r-ccu-y += ccu-sun8i-r.o
+sun9i-a80-ccu-y += ccu-sun9i-a80.o
+sun9i-a80-de-ccu-y += ccu-sun9i-a80-de.o
+sun9i-a80-usb-ccu-y += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
index 804729e0a208..fddd6c877cec 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
@@ -5,7 +5,6 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
-#include <linux/of_address.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -213,3 +212,6 @@ static struct platform_driver sun50i_a100_r_ccu_driver = {
},
};
module_platform_driver(sun50i_a100_r_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
index 1d475d5a3d91..5f93b5526e13 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
@@ -6,7 +6,6 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/of_address.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -1275,3 +1274,6 @@ static struct platform_driver sun50i_a100_ccu_driver = {
},
};
module_platform_driver(sun50i_a100_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index a8c5a92b7d0c..41519185600a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -980,4 +980,7 @@ static struct platform_driver sun50i_a64_ccu_driver = {
.of_match_table = sun50i_a64_ccu_ids,
},
};
-builtin_platform_driver(sun50i_a64_ccu_driver);
+module_platform_driver(sun50i_a64_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index e5672c10d065..1a5e418923f6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -1254,4 +1254,7 @@ static struct platform_driver sun50i_h6_ccu_driver = {
.of_match_table = sun50i_h6_ccu_ids,
},
};
-builtin_platform_driver(sun50i_h6_ccu_driver);
+module_platform_driver(sun50i_h6_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 3c310aea8cfa..76cbd9e9e89f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -920,4 +920,7 @@ static struct platform_driver sun8i_a83t_ccu_driver = {
.of_match_table = sun8i_a83t_ccu_ids,
},
};
-builtin_platform_driver(sun8i_a83t_ccu_driver);
+module_platform_driver(sun8i_a83t_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 573b5051d305..e7e3ddf4a227 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -5,8 +5,8 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
@@ -394,4 +394,7 @@ static struct platform_driver sunxi_de2_clk_driver = {
.of_match_table = sunxi_de2_clk_ids,
},
};
-builtin_platform_driver(sunxi_de2_clk_driver);
+module_platform_driver(sunxi_de2_clk_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 8bb18d9add05..31eca0d3bc1e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -5,6 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -1371,4 +1372,7 @@ static struct platform_driver sun8i_r40_ccu_driver = {
.of_match_table = sun8i_r40_ccu_ids,
},
};
-builtin_platform_driver(sun8i_r40_ccu_driver);
+module_platform_driver(sun8i_r40_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
index 3cde2610f467..f2fe0e1cc3c0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
@@ -5,7 +5,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
@@ -270,4 +270,7 @@ static struct platform_driver sun9i_a80_de_clk_driver = {
.of_match_table = sun9i_a80_de_clk_ids,
},
};
-builtin_platform_driver(sun9i_a80_de_clk_driver);
+module_platform_driver(sun9i_a80_de_clk_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
index 0740e8978ae8..575ae4ccc65f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
@@ -5,7 +5,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -138,4 +138,7 @@ static struct platform_driver sun9i_a80_usb_clk_driver = {
.of_match_table = sun9i_a80_usb_clk_ids,
},
};
-builtin_platform_driver(sun9i_a80_usb_clk_driver);
+module_platform_driver(sun9i_a80_usb_clk_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index d416af29e0d3..730fd8e28014 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -5,7 +5,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -1245,4 +1245,7 @@ static struct platform_driver sun9i_a80_ccu_driver = {
.of_match_table = sun9i_a80_ccu_ids,
},
};
-builtin_platform_driver(sun9i_a80_ccu_driver);
+module_platform_driver(sun9i_a80_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
--
2.32.0
The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
the SoC's main CCU.
However, sun8i-r-ccu is an early OF clock provider, and many of the
main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
the consumer clocks will be orphaned until the supplier driver is bound.
This can be avoided by converting the remaining CCUs to use platform
drivers. Then fw_devlink will ensure the drivers are bound in the
optimal order.
The sun5i CCU is the only one which actually needs to be an early clock
provider, because it provides the clock for the system timer. That one
is left alone.
Signed-off-by: Samuel Holland <[email protected]>
---
(no changes since v1)
drivers/clk/sunxi-ng/Kconfig | 20 ++++----
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
11 files changed, 332 insertions(+), 172 deletions(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index c004ffc10ef7..de88b6e0ec69 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -8,7 +8,7 @@ config SUNXI_CCU
if SUNXI_CCU
config SUNIV_F1C100S_CCU
- bool "Support for the Allwinner newer F1C100s CCU"
+ tristate "Support for the Allwinner newer F1C100s CCU"
default MACH_SUNIV
depends on MACH_SUNIV || COMPILE_TEST
@@ -33,17 +33,17 @@ config SUN50I_H6_CCU
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H616_CCU
- bool "Support for the Allwinner H616 CCU"
+ tristate "Support for the Allwinner H616 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_R_CCU
- bool "Support for the Allwinner H6 and H616 PRCM CCU"
+ tristate "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN4I_A10_CCU
- bool "Support for the Allwinner A10/A20 CCU"
+ tristate "Support for the Allwinner A10/A20 CCU"
default MACH_SUN4I
default MACH_SUN7I
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
@@ -54,17 +54,17 @@ config SUN5I_CCU
depends on MACH_SUN5I || COMPILE_TEST
config SUN6I_A31_CCU
- bool "Support for the Allwinner A31/A31s CCU"
+ tristate "Support for the Allwinner A31/A31s CCU"
default MACH_SUN6I
depends on MACH_SUN6I || COMPILE_TEST
config SUN8I_A23_CCU
- bool "Support for the Allwinner A23 CCU"
+ tristate "Support for the Allwinner A23 CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_A33_CCU
- bool "Support for the Allwinner A33 CCU"
+ tristate "Support for the Allwinner A33 CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
@@ -74,12 +74,12 @@ config SUN8I_A83T_CCU
depends on MACH_SUN8I || COMPILE_TEST
config SUN8I_H3_CCU
- bool "Support for the Allwinner H3 CCU"
+ tristate "Support for the Allwinner H3 CCU"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN8I_V3S_CCU
- bool "Support for the Allwinner V3s CCU"
+ tristate "Support for the Allwinner V3s CCU"
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
@@ -98,7 +98,7 @@ config SUN9I_A80_CCU
depends on MACH_SUN9I || COMPILE_TEST
config SUN8I_R_CCU
- bool "Support for Allwinner SoCs' PRCM CCUs"
+ tristate "Support for Allwinner SoCs' PRCM CCUs"
default MACH_SUN8I || (ARCH_SUNXI && ARM64)
endif
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index bd9a8782fec3..c19828f1aa0f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -7,7 +7,9 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -1425,18 +1427,19 @@ static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
.num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
};
-static void __init sun4i_ccu_init(struct device_node *node,
- const struct sunxi_ccu_desc *desc)
+static int sun4i_a10_ccu_probe(struct platform_device *pdev)
{
+ const struct sunxi_ccu_desc *desc;
void __iomem *reg;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
- return;
- }
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
val = readl(reg + SUN4I_PLL_AUDIO_REG);
@@ -1464,19 +1467,30 @@ static void __init sun4i_ccu_init(struct device_node *node,
val &= ~GENMASK(7, 6);
writel(val | (2 << 6), reg + SUN4I_AHB_REG);
- of_sunxi_ccu_probe(node, reg, desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
-static void __init sun4i_a10_ccu_setup(struct device_node *node)
-{
- sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
-}
-CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
- sun4i_a10_ccu_setup);
+static const struct of_device_id sun4i_a10_ccu_ids[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-ccu",
+ .data = &sun4i_a10_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun7i-a20-ccu",
+ .data = &sun7i_a20_ccu_desc,
+ },
+ { }
+};
-static void __init sun7i_a20_ccu_setup(struct device_node *node)
-{
- sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
-}
-CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
- sun7i_a20_ccu_setup);
+static struct platform_driver sun4i_a10_ccu_driver = {
+ .probe = sun4i_a10_ccu_probe,
+ .driver = {
+ .name = "sun4i-a10-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun4i_a10_ccu_ids,
+ },
+};
+module_platform_driver(sun4i_a10_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index f30d7eb5424d..712e103382d8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -4,7 +4,8 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -221,30 +222,43 @@ static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
};
-static void __init sunxi_r_ccu_init(struct device_node *node,
- const struct sunxi_ccu_desc *desc)
+static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
{
+ const struct sunxi_ccu_desc *desc;
void __iomem *reg;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
- of_sunxi_ccu_probe(node, reg, desc);
-}
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
-static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
-{
- sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
-CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
- sun50i_h6_r_ccu_setup);
-static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
-{
- sunxi_r_ccu_init(node, &sun50i_h616_r_ccu_desc);
-}
-CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
- sun50i_h616_r_ccu_setup);
+static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
+ {
+ .compatible = "allwinner,sun50i-h6-r-ccu",
+ .data = &sun50i_h6_r_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun50i-h616-r-ccu",
+ .data = &sun50i_h616_r_ccu_desc,
+ },
+ { }
+};
+
+static struct platform_driver sun50i_h6_r_ccu_driver = {
+ .probe = sun50i_h6_r_ccu_probe,
+ .driver = {
+ .name = "sun50i-h6-r-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun50i_h6_r_ccu_ids,
+ },
+};
+module_platform_driver(sun50i_h6_r_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
index 22eb18079a15..49a2474cf314 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -7,7 +7,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -1082,17 +1082,15 @@ static const u32 usb2_clk_regs[] = {
SUN50I_H616_USB3_CLK_REG,
};
-static void __init sun50i_h616_ccu_setup(struct device_node *node)
+static int sun50i_h616_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map clock registers\n", node);
- return;
- }
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Enable the lock bits and the output enable bits on all PLLs */
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
@@ -1141,8 +1139,23 @@ static void __init sun50i_h616_ccu_setup(struct device_node *node)
val |= BIT(24);
writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
- of_sunxi_ccu_probe(node, reg, &sun50i_h616_ccu_desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
}
-CLK_OF_DECLARE(sun50i_h616_ccu, "allwinner,sun50i-h616-ccu",
- sun50i_h616_ccu_setup);
+static const struct of_device_id sun50i_h616_ccu_ids[] = {
+ { .compatible = "allwinner,sun50i-h616-ccu" },
+ { }
+};
+
+static struct platform_driver sun50i_h616_ccu_driver = {
+ .probe = sun50i_h616_ccu_probe,
+ .driver = {
+ .name = "sun50i-h616-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun50i_h616_ccu_ids,
+ },
+};
+module_platform_driver(sun50i_h616_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 3df5c0b41580..0762deffb33c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -9,7 +9,8 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -1226,16 +1227,15 @@ static struct ccu_mux_nb sun6i_a31_cpu_nb = {
.bypass_index = 1, /* index of 24 MHz oscillator */
};
-static void __init sun6i_a31_ccu_setup(struct device_node *node)
+static int sun6i_a31_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
+ int ret;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
@@ -1257,10 +1257,30 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
val |= 0x3 << 12;
writel(val, reg + SUN6I_A31_AHB1_REG);
- of_sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc);
+ if (ret)
+ return ret;
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
&sun6i_a31_cpu_nb);
+
+ return 0;
}
-CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
- sun6i_a31_ccu_setup);
+
+static const struct of_device_id sun6i_a31_ccu_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-ccu" },
+ { }
+};
+
+static struct platform_driver sun6i_a31_ccu_driver = {
+ .probe = sun6i_a31_ccu_probe,
+ .driver = {
+ .name = "sun6i-a31-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun6i_a31_ccu_ids,
+ },
+};
+module_platform_driver(sun6i_a31_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 577bb235d658..e80cc3864e44 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -5,7 +5,8 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -724,16 +725,14 @@ static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
.num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
};
-static void __init sun8i_a23_ccu_setup(struct device_node *node)
+static int sun8i_a23_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
@@ -745,7 +744,23 @@ static void __init sun8i_a23_ccu_setup(struct device_node *node)
val &= ~BIT(16);
writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
- of_sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc);
}
-CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
- sun8i_a23_ccu_setup);
+
+static const struct of_device_id sun8i_a23_ccu_ids[] = {
+ { .compatible = "allwinner,sun8i-a23-ccu" },
+ { }
+};
+
+static struct platform_driver sun8i_a23_ccu_driver = {
+ .probe = sun8i_a23_ccu_probe,
+ .driver = {
+ .name = "sun8i-a23-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun8i_a23_ccu_ids,
+ },
+};
+module_platform_driver(sun8i_a23_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 8f65cd03f5ac..d12878a1ba9e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -5,7 +5,8 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -784,16 +785,15 @@ static struct ccu_mux_nb sun8i_a33_cpu_nb = {
.bypass_index = 1, /* index of 24 MHz oscillator */
};
-static void __init sun8i_a33_ccu_setup(struct device_node *node)
+static int sun8i_a33_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
+ int ret;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
@@ -805,7 +805,9 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
val &= ~BIT(16);
writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
- of_sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc);
+ if (ret)
+ return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
@@ -813,6 +815,24 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_a33_cpu_nb);
+
+ return 0;
}
-CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
- sun8i_a33_ccu_setup);
+
+static const struct of_device_id sun8i_a33_ccu_ids[] = {
+ { .compatible = "allwinner,sun8i-a33-ccu" },
+ { }
+};
+
+static struct platform_driver sun8i_a33_ccu_driver = {
+ .probe = sun8i_a33_ccu_probe,
+ .driver = {
+ .name = "sun8i-a33-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun8i_a33_ccu_ids,
+ },
+};
+module_platform_driver(sun8i_a33_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index d2fc2903787d..e058cf691aea 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -5,7 +5,9 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -1137,24 +1139,29 @@ static struct ccu_mux_nb sun8i_h3_cpu_nb = {
.bypass_index = 1, /* index of 24 MHz oscillator */
};
-static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
- const struct sunxi_ccu_desc *desc)
+static int sun8i_h3_ccu_probe(struct platform_device *pdev)
{
+ const struct sunxi_ccu_desc *desc;
void __iomem *reg;
+ int ret;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
- of_sunxi_ccu_probe(node, reg, desc);
+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
+ if (ret)
+ return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
@@ -1162,18 +1169,31 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_h3_cpu_nb);
-}
-static void __init sun8i_h3_ccu_setup(struct device_node *node)
-{
- sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
+ return 0;
}
-CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
- sun8i_h3_ccu_setup);
-static void __init sun50i_h5_ccu_setup(struct device_node *node)
-{
- sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
-}
-CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
- sun50i_h5_ccu_setup);
+static const struct of_device_id sun8i_h3_ccu_ids[] = {
+ {
+ .compatible = "allwinner,sun8i-h3-ccu",
+ .data = &sun8i_h3_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun50i-h5-ccu",
+ .data = &sun50i_h5_ccu_desc,
+ },
+ { }
+};
+
+static struct platform_driver sun8i_h3_ccu_driver = {
+ .probe = sun8i_h3_ccu_probe,
+ .driver = {
+ .name = "sun8i-h3-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun8i_h3_ccu_ids,
+ },
+};
+module_platform_driver(sun8i_h3_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 9e754d1f754a..5b7fab832a52 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -4,7 +4,8 @@
*/
#include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
@@ -254,37 +255,47 @@ static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
};
-static void __init sunxi_r_ccu_init(struct device_node *node,
- const struct sunxi_ccu_desc *desc)
+static int sun8i_r_ccu_probe(struct platform_device *pdev)
{
+ const struct sunxi_ccu_desc *desc;
void __iomem *reg;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
- of_sunxi_ccu_probe(node, reg, desc);
-}
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
-static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
-{
- sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
-CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
- sun8i_a83t_r_ccu_setup);
-static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
-{
- sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
-}
-CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
- sun8i_h3_r_ccu_setup);
+static const struct of_device_id sun8i_r_ccu_ids[] = {
+ {
+ .compatible = "allwinner,sun8i-a83t-r-ccu",
+ .data = &sun8i_a83t_r_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-r-ccu",
+ .data = &sun8i_h3_r_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun50i-a64-r-ccu",
+ .data = &sun50i_a64_r_ccu_desc,
+ },
+ { }
+};
-static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
-{
- sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
-}
-CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
- sun50i_a64_r_ccu_setup);
+static struct platform_driver sun8i_r_ccu_driver = {
+ .probe = sun8i_r_ccu_probe,
+ .driver = {
+ .name = "sun8i-r-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun8i_r_ccu_ids,
+ },
+};
+module_platform_driver(sun8i_r_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index ce150f83ab54..87f87d6ea3ad 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -8,7 +8,9 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -805,38 +807,49 @@ static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
.num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
};
-static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
- const struct sunxi_ccu_desc *ccu_desc)
+static int sun8i_v3s_ccu_probe(struct platform_device *pdev)
{
+ const struct sunxi_ccu_desc *desc;
void __iomem *reg;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
- of_sunxi_ccu_probe(node, reg, ccu_desc);
-}
-
-static void __init sun8i_v3s_ccu_setup(struct device_node *node)
-{
- sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
+ return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
-static void __init sun8i_v3_ccu_setup(struct device_node *node)
-{
- sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
-}
+static const struct of_device_id sun8i_v3s_ccu_ids[] = {
+ {
+ .compatible = "allwinner,sun8i-v3-ccu",
+ .data = &sun8i_v3_ccu_desc,
+ },
+ {
+ .compatible = "allwinner,sun8i-v3s-ccu",
+ .data = &sun8i_v3s_ccu_desc,
+ },
+ { }
+};
-CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
- sun8i_v3s_ccu_setup);
+static struct platform_driver sun8i_v3s_ccu_driver = {
+ .probe = sun8i_v3s_ccu_probe,
+ .driver = {
+ .name = "sun8i-v3s-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = sun8i_v3s_ccu_ids,
+ },
+};
+module_platform_driver(sun8i_v3s_ccu_driver);
-CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
- sun8i_v3_ccu_setup);
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index 61ad7ee91c11..a36dcab517e3 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -6,7 +6,8 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
-#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
@@ -525,20 +526,21 @@ static struct ccu_mux_nb suniv_cpu_nb = {
static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
{
void __iomem *reg;
+ int ret;
u32 val;
- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
- if (IS_ERR(reg)) {
- pr_err("%pOF: Could not map the clock registers\n", node);
- return;
- }
+ reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUNIV_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
- of_sunxi_ccu_probe(node, reg, &suniv_ccu_desc);
+ ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc);
+ if (ret)
+ return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&suniv_pll_cpu_nb);
@@ -546,6 +548,24 @@ static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
&suniv_cpu_nb);
+
+ return 0;
}
-CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu",
- suniv_f1c100s_ccu_setup);
+
+static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
+ { .compatible = "allwinner,suniv-f1c100s-ccu" },
+ { }
+};
+
+static struct platform_driver suniv_f1c100s_ccu_driver = {
+ .probe = suniv_f1c100s_ccu_probe,
+ .driver = {
+ .name = "suniv-f1c100s-ccu",
+ .suppress_bind_attrs = true,
+ .of_match_table = suniv_f1c100s_ccu_ids,
+ },
+};
+module_platform_driver(suniv_f1c100s_ccu_driver);
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
--
2.32.0
Like the individual CCU drivers, it can be beneficial for memory
consumption of cross-platform configurations to only load the CCU core
on the relevant platform. For example, a generic arm64 kernel sees the
following improvement when building the CCU core and drivers as modules:
before:
text data bss dec hex filename
13882360 5251670 360800 19494830 12977ae vmlinux
after:
text data bss dec hex filename
13734787 5086442 360800 19182029 124b1cd vmlinux
So the result is a 390KB total reduction in kernel image size.
The one early clock provider (sun5i) requires the core to be built in.
Now that loading the MMC driver will trigger loading the CCU core, the
MMC timing mode functions do not need a compile-time fallback.
Signed-off-by: Samuel Holland <[email protected]>
---
(no changes since v1)
drivers/clk/Makefile | 2 +-
drivers/clk/sunxi-ng/Kconfig | 3 ++-
drivers/clk/sunxi-ng/Makefile | 33 +++++++++++++++++--------------
drivers/clk/sunxi-ng/ccu_common.c | 3 +++
drivers/mmc/host/Kconfig | 1 +
include/linux/clk/sunxi-ng.h | 15 --------------
6 files changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e42312121e51..6afe36bd2c0a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -110,7 +110,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_ARCH_STI) += st/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/
+obj-y += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index de88b6e0ec69..727ff755eca4 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
config SUNXI_CCU
- bool "Clock support for Allwinner SoCs"
+ tristate "Clock support for Allwinner SoCs"
depends on ARCH_SUNXI || COMPILE_TEST
select RESET_CONTROLLER
default ARCH_SUNXI
@@ -52,6 +52,7 @@ config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
depends on MACH_SUN5I || COMPILE_TEST
+ depends on SUNXI_CCU=y
config SUN6I_A31_CCU
tristate "Support for the Allwinner A31/A31s CCU"
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 1020ed49a588..659d55150c32 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -1,24 +1,27 @@
# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_SUNXI_CCU) += sunxi-ccu.o
+
# Common objects
-obj-y += ccu_common.o
-obj-y += ccu_mmc_timing.o
-obj-y += ccu_reset.o
+sunxi-ccu-y += ccu_common.o
+sunxi-ccu-y += ccu_mmc_timing.o
+sunxi-ccu-y += ccu_reset.o
# Base clock types
-obj-y += ccu_div.o
-obj-y += ccu_frac.o
-obj-y += ccu_gate.o
-obj-y += ccu_mux.o
-obj-y += ccu_mult.o
-obj-y += ccu_phase.o
-obj-y += ccu_sdm.o
+sunxi-ccu-y += ccu_div.o
+sunxi-ccu-y += ccu_frac.o
+sunxi-ccu-y += ccu_gate.o
+sunxi-ccu-y += ccu_mux.o
+sunxi-ccu-y += ccu_mult.o
+sunxi-ccu-y += ccu_phase.o
+sunxi-ccu-y += ccu_sdm.o
# Multi-factor clocks
-obj-y += ccu_nk.o
-obj-y += ccu_nkm.o
-obj-y += ccu_nkmp.o
-obj-y += ccu_nm.o
-obj-y += ccu_mp.o
+sunxi-ccu-y += ccu_nk.o
+sunxi-ccu-y += ccu_nkm.o
+sunxi-ccu-y += ccu_nkmp.o
+sunxi-ccu-y += ccu_nm.o
+sunxi-ccu-y += ccu_mp.o
# SoC support
obj-$(CONFIG_SUNIV_F1C100S_CCU) += suniv-f1c100s-ccu.o
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 6afdedbce6a2..8d28a7a079d0 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/iopoll.h>
+#include <linux/module.h>
#include <linux/slab.h>
#include "ccu_common.h"
@@ -214,3 +215,5 @@ void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
kfree(ccu);
}
}
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5af8494c31b5..52b0b27a6839 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -966,6 +966,7 @@ config MMC_REALTEK_USB
config MMC_SUNXI
tristate "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI || COMPILE_TEST
+ depends on SUNXI_CCU
help
This selects support for the SD/MMC Host Controller on
Allwinner sunxi SoCs.
diff --git a/include/linux/clk/sunxi-ng.h b/include/linux/clk/sunxi-ng.h
index 3cd14acde0a1..cf32123b39f5 100644
--- a/include/linux/clk/sunxi-ng.h
+++ b/include/linux/clk/sunxi-ng.h
@@ -6,22 +6,7 @@
#ifndef _LINUX_CLK_SUNXI_NG_H_
#define _LINUX_CLK_SUNXI_NG_H_
-#include <linux/errno.h>
-
-#ifdef CONFIG_SUNXI_CCU
int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode);
int sunxi_ccu_get_mmc_timing_mode(struct clk *clk);
-#else
-static inline int sunxi_ccu_set_mmc_timing_mode(struct clk *clk,
- bool new_mode)
-{
- return -ENOTSUPP;
-}
-
-static inline int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)
-{
- return -ENOTSUPP;
-}
-#endif
#endif
--
2.32.0
On Thu, 18 Nov 2021 21:33:33 -0600, Samuel Holland wrote:
> This series allows the CCU core and drivers to be loaded/unloaded as
> modules. As part of this, patch 3 converts most of the early OF clock
> providers to platform drivers.
>
> Changes in v3:
> - Also export helper functions.
>
> [...]
Applied to sunxi/linux.git (sunxi/clk-for-5.17).
Thanks!
Maxime
Samuel Holland <[email protected]> writes:
> The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
> example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
> the SoC's main CCU.
>
> However, sun8i-r-ccu is an early OF clock provider, and many of the
> main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
> the consumer clocks will be orphaned until the supplier driver is bound.
> This can be avoided by converting the remaining CCUs to use platform
> drivers. Then fw_devlink will ensure the drivers are bound in the
> optimal order.
>
> The sun5i CCU is the only one which actually needs to be an early clock
> provider, because it provides the clock for the system timer. That one
> is left alone.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> (no changes since v1)
>
> drivers/clk/sunxi-ng/Kconfig | 20 ++++----
> drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
> drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
> drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
> drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
> drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
> drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
> drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
> 11 files changed, 332 insertions(+), 172 deletions(-)
This broke the hstimer clocksource on A20 since it requires a clock
provided by the sun4i ccu driver.
--
M?ns Rullg?rd
On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
> Samuel Holland <[email protected]> writes:
>
> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
> > the SoC's main CCU.
> >
> > However, sun8i-r-ccu is an early OF clock provider, and many of the
> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
> > the consumer clocks will be orphaned until the supplier driver is bound.
> > This can be avoided by converting the remaining CCUs to use platform
> > drivers. Then fw_devlink will ensure the drivers are bound in the
> > optimal order.
> >
> > The sun5i CCU is the only one which actually needs to be an early clock
> > provider, because it provides the clock for the system timer. That one
> > is left alone.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > (no changes since v1)
> >
> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
> > 11 files changed, 332 insertions(+), 172 deletions(-)
>
> This broke the hstimer clocksource on A20 since it requires a clock
> provided by the sun4i ccu driver.
The A10 is probably broken by this, but the A20 should be able to use
the arch timers just like all the other Cortex-A7-based SoCs.
Do you have a dmesg log that could help debug why it's not working?
Maxime
Maxime Ripard <[email protected]> writes:
> On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
>> Samuel Holland <[email protected]> writes:
>>
>> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
>> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
>> > the SoC's main CCU.
>> >
>> > However, sun8i-r-ccu is an early OF clock provider, and many of the
>> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
>> > the consumer clocks will be orphaned until the supplier driver is bound.
>> > This can be avoided by converting the remaining CCUs to use platform
>> > drivers. Then fw_devlink will ensure the drivers are bound in the
>> > optimal order.
>> >
>> > The sun5i CCU is the only one which actually needs to be an early clock
>> > provider, because it provides the clock for the system timer. That one
>> > is left alone.
>> >
>> > Signed-off-by: Samuel Holland <[email protected]>
>> > ---
>> >
>> > (no changes since v1)
>> >
>> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
>> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
>> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
>> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
>> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
>> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
>> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
>> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
>> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
>> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
>> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
>> > 11 files changed, 332 insertions(+), 172 deletions(-)
>>
>> This broke the hstimer clocksource on A20 since it requires a clock
>> provided by the sun4i ccu driver.
>
> The A10 is probably broken by this, but the A20 should be able to use
> the arch timers just like all the other Cortex-A7-based SoCs.
>
> Do you have a dmesg log that could help debug why it's not working?
The A20 works as such since, as you say, it has other clocksources.
However, the hstimer has become unusable. If anyone was using, for
whatever reason, it won't be working for them now.
Before this change, the kernel log used include this line:
clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns
Now there is only a cryptic "Can't get timer clock" in its place.
As it is now, the hstimer driver is nothing but a waste of space.
I figure it ought to be fixed one way or another.
--
M?ns Rullg?rd
On Wed, Jun 28, 2023 at 12:07:56PM +0100, M?ns Rullg?rd wrote:
> Maxime Ripard <[email protected]> writes:
>
> > On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
> >> Samuel Holland <[email protected]> writes:
> >>
> >> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
> >> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
> >> > the SoC's main CCU.
> >> >
> >> > However, sun8i-r-ccu is an early OF clock provider, and many of the
> >> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
> >> > the consumer clocks will be orphaned until the supplier driver is bound.
> >> > This can be avoided by converting the remaining CCUs to use platform
> >> > drivers. Then fw_devlink will ensure the drivers are bound in the
> >> > optimal order.
> >> >
> >> > The sun5i CCU is the only one which actually needs to be an early clock
> >> > provider, because it provides the clock for the system timer. That one
> >> > is left alone.
> >> >
> >> > Signed-off-by: Samuel Holland <[email protected]>
> >> > ---
> >> >
> >> > (no changes since v1)
> >> >
> >> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
> >> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
> >> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
> >> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
> >> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
> >> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
> >> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
> >> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
> >> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
> >> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
> >> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
> >> > 11 files changed, 332 insertions(+), 172 deletions(-)
> >>
> >> This broke the hstimer clocksource on A20 since it requires a clock
> >> provided by the sun4i ccu driver.
> >
> > The A10 is probably broken by this, but the A20 should be able to use
> > the arch timers just like all the other Cortex-A7-based SoCs.
> >
> > Do you have a dmesg log that could help debug why it's not working?
>
> The A20 works as such since, as you say, it has other clocksources.
> However, the hstimer has become unusable. If anyone was using, for
> whatever reason, it won't be working for them now.
>
> Before this change, the kernel log used include this line:
>
> clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns
>
> Now there is only a cryptic "Can't get timer clock" in its place.
>
> As it is now, the hstimer driver is nothing but a waste of space.
> I figure it ought to be fixed one way or another.
Yeah, definitely.
IIRC, the situation is:
- A10 has just the "regular", old, timer
- A10s/A13/GR8 has the A10 timer + hstimer
- A20 has the A13 timers + arch timers
We also default to the hstimer only for the A10s/A13 which aren't
affected by this patch series afaics.
We also enable the HS timer for the A31, but just like the A20 it
doesn't use it by default, so it's probably been broken there too.
I guess one way to fix it would be to switch the HS timer driver to a
lower priority than the A10 timer, so we pick that up by default instead
for the A10s/A13, and then convert the HS timer driver to a proper
platform_device driver that will be able to get its clock.
The downside is that the A13 will lose some precision over its default
timer, but I don't think it's a big deal.
Maxime
Maxime Ripard <[email protected]> writes:
> On Wed, Jun 28, 2023 at 12:07:56PM +0100, M?ns Rullg?rd wrote:
>> Maxime Ripard <[email protected]> writes:
>>
>> > On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
>> >> Samuel Holland <[email protected]> writes:
>> >>
>> >> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
>> >> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
>> >> > the SoC's main CCU.
>> >> >
>> >> > However, sun8i-r-ccu is an early OF clock provider, and many of the
>> >> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
>> >> > the consumer clocks will be orphaned until the supplier driver is bound.
>> >> > This can be avoided by converting the remaining CCUs to use platform
>> >> > drivers. Then fw_devlink will ensure the drivers are bound in the
>> >> > optimal order.
>> >> >
>> >> > The sun5i CCU is the only one which actually needs to be an early clock
>> >> > provider, because it provides the clock for the system timer. That one
>> >> > is left alone.
>> >> >
>> >> > Signed-off-by: Samuel Holland <[email protected]>
>> >> > ---
>> >> >
>> >> > (no changes since v1)
>> >> >
>> >> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
>> >> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
>> >> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
>> >> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
>> >> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
>> >> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
>> >> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
>> >> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
>> >> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
>> >> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
>> >> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
>> >> > 11 files changed, 332 insertions(+), 172 deletions(-)
>> >>
>> >> This broke the hstimer clocksource on A20 since it requires a clock
>> >> provided by the sun4i ccu driver.
>> >
>> > The A10 is probably broken by this, but the A20 should be able to use
>> > the arch timers just like all the other Cortex-A7-based SoCs.
>> >
>> > Do you have a dmesg log that could help debug why it's not working?
>>
>> The A20 works as such since, as you say, it has other clocksources.
>> However, the hstimer has become unusable. If anyone was using, for
>> whatever reason, it won't be working for them now.
>>
>> Before this change, the kernel log used include this line:
>>
>> clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns
>>
>> Now there is only a cryptic "Can't get timer clock" in its place.
>>
>> As it is now, the hstimer driver is nothing but a waste of space.
>> I figure it ought to be fixed one way or another.
>
> Yeah, definitely.
>
> IIRC, the situation is:
>
> - A10 has just the "regular", old, timer
> - A10s/A13/GR8 has the A10 timer + hstimer
> - A20 has the A13 timers + arch timers
>
> We also default to the hstimer only for the A10s/A13 which aren't
> affected by this patch series afaics.
>
> We also enable the HS timer for the A31, but just like the A20 it
> doesn't use it by default, so it's probably been broken there too.
>
> I guess one way to fix it would be to switch the HS timer driver to a
> lower priority than the A10 timer, so we pick that up by default instead
> for the A10s/A13, and then convert the HS timer driver to a proper
> platform_device driver that will be able to get its clock.
>
> The downside is that the A13 will lose some precision over its default
> timer, but I don't think it's a big deal.
The options I see are converting the hstimer to a platform device or
reverting the change to the sun4i ccu driver.
I don't personally have much of an opinion on this since my systems
aren't affected. The only reason I looked at it was that I noticed
a new error message in the kernel logs.
--
M?ns Rullg?rd
On Wed, Jun 28, 2023 at 07:33:35PM +0100, M?ns Rullg?rd wrote:
> Maxime Ripard <[email protected]> writes:
>
> > On Wed, Jun 28, 2023 at 12:07:56PM +0100, M?ns Rullg?rd wrote:
> >> Maxime Ripard <[email protected]> writes:
> >>
> >> > On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
> >> >> Samuel Holland <[email protected]> writes:
> >> >>
> >> >> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
> >> >> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
> >> >> > the SoC's main CCU.
> >> >> >
> >> >> > However, sun8i-r-ccu is an early OF clock provider, and many of the
> >> >> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
> >> >> > the consumer clocks will be orphaned until the supplier driver is bound.
> >> >> > This can be avoided by converting the remaining CCUs to use platform
> >> >> > drivers. Then fw_devlink will ensure the drivers are bound in the
> >> >> > optimal order.
> >> >> >
> >> >> > The sun5i CCU is the only one which actually needs to be an early clock
> >> >> > provider, because it provides the clock for the system timer. That one
> >> >> > is left alone.
> >> >> >
> >> >> > Signed-off-by: Samuel Holland <[email protected]>
> >> >> > ---
> >> >> >
> >> >> > (no changes since v1)
> >> >> >
> >> >> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
> >> >> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
> >> >> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
> >> >> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
> >> >> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
> >> >> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
> >> >> > 11 files changed, 332 insertions(+), 172 deletions(-)
> >> >>
> >> >> This broke the hstimer clocksource on A20 since it requires a clock
> >> >> provided by the sun4i ccu driver.
> >> >
> >> > The A10 is probably broken by this, but the A20 should be able to use
> >> > the arch timers just like all the other Cortex-A7-based SoCs.
> >> >
> >> > Do you have a dmesg log that could help debug why it's not working?
> >>
> >> The A20 works as such since, as you say, it has other clocksources.
> >> However, the hstimer has become unusable. If anyone was using, for
> >> whatever reason, it won't be working for them now.
> >>
> >> Before this change, the kernel log used include this line:
> >>
> >> clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns
> >>
> >> Now there is only a cryptic "Can't get timer clock" in its place.
> >>
> >> As it is now, the hstimer driver is nothing but a waste of space.
> >> I figure it ought to be fixed one way or another.
> >
> > Yeah, definitely.
> >
> > IIRC, the situation is:
> >
> > - A10 has just the "regular", old, timer
> > - A10s/A13/GR8 has the A10 timer + hstimer
> > - A20 has the A13 timers + arch timers
> >
> > We also default to the hstimer only for the A10s/A13 which aren't
> > affected by this patch series afaics.
> >
> > We also enable the HS timer for the A31, but just like the A20 it
> > doesn't use it by default, so it's probably been broken there too.
> >
> > I guess one way to fix it would be to switch the HS timer driver to a
> > lower priority than the A10 timer, so we pick that up by default instead
> > for the A10s/A13, and then convert the HS timer driver to a proper
> > platform_device driver that will be able to get its clock.
> >
> > The downside is that the A13 will lose some precision over its default
> > timer, but I don't think it's a big deal.
>
> The options I see are converting the hstimer to a platform device or
> reverting the change to the sun4i ccu driver.
>
> I don't personally have much of an opinion on this since my systems
> aren't affected. The only reason I looked at it was that I noticed
> a new error message in the kernel logs.
Thanks for the report then. I'm not really working on that anymore, so I
won't submit a fix for this either.
Maxime
Maxime Ripard <[email protected]> writes:
> On Wed, Jun 28, 2023 at 07:33:35PM +0100, M?ns Rullg?rd wrote:
>> Maxime Ripard <[email protected]> writes:
>>
>> > On Wed, Jun 28, 2023 at 12:07:56PM +0100, M?ns Rullg?rd wrote:
>> >> Maxime Ripard <[email protected]> writes:
>> >>
>> >> > On Mon, Jun 26, 2023 at 01:21:33PM +0100, M?ns Rullg?rd wrote:
>> >> >> Samuel Holland <[email protected]> writes:
>> >> >>
>> >> >> > The PRCM CCU drivers depend on clocks provided by other CCU drivers. For
>> >> >> > example, the sun8i-r-ccu driver uses the "pll-periph" clock provided by
>> >> >> > the SoC's main CCU.
>> >> >> >
>> >> >> > However, sun8i-r-ccu is an early OF clock provider, and many of the
>> >> >> > main CCUs (e.g. sun50i-a64-ccu) use platform drivers. This means that
>> >> >> > the consumer clocks will be orphaned until the supplier driver is bound.
>> >> >> > This can be avoided by converting the remaining CCUs to use platform
>> >> >> > drivers. Then fw_devlink will ensure the drivers are bound in the
>> >> >> > optimal order.
>> >> >> >
>> >> >> > The sun5i CCU is the only one which actually needs to be an early clock
>> >> >> > provider, because it provides the clock for the system timer. That one
>> >> >> > is left alone.
>> >> >> >
>> >> >> > Signed-off-by: Samuel Holland <[email protected]>
>> >> >> > ---
>> >> >> >
>> >> >> > (no changes since v1)
>> >> >> >
>> >> >> > drivers/clk/sunxi-ng/Kconfig | 20 ++++----
>> >> >> > drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 58 +++++++++++++--------
>> >> >> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 56 ++++++++++++--------
>> >> >> > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 ++++++++----
>> >> >> > drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 40 +++++++++++----
>> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 35 +++++++++----
>> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 40 +++++++++++----
>> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 62 ++++++++++++++--------
>> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-r.c | 65 ++++++++++++++----------
>> >> >> > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 57 +++++++++++++--------
>> >> >> > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 38 ++++++++++----
>> >> >> > 11 files changed, 332 insertions(+), 172 deletions(-)
>> >> >>
>> >> >> This broke the hstimer clocksource on A20 since it requires a clock
>> >> >> provided by the sun4i ccu driver.
>> >> >
>> >> > The A10 is probably broken by this, but the A20 should be able to use
>> >> > the arch timers just like all the other Cortex-A7-based SoCs.
>> >> >
>> >> > Do you have a dmesg log that could help debug why it's not working?
>> >>
>> >> The A20 works as such since, as you say, it has other clocksources.
>> >> However, the hstimer has become unusable. If anyone was using, for
>> >> whatever reason, it won't be working for them now.
>> >>
>> >> Before this change, the kernel log used include this line:
>> >>
>> >> clocksource: hstimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370868154 ns
>> >>
>> >> Now there is only a cryptic "Can't get timer clock" in its place.
>> >>
>> >> As it is now, the hstimer driver is nothing but a waste of space.
>> >> I figure it ought to be fixed one way or another.
>> >
>> > Yeah, definitely.
>> >
>> > IIRC, the situation is:
>> >
>> > - A10 has just the "regular", old, timer
>> > - A10s/A13/GR8 has the A10 timer + hstimer
>> > - A20 has the A13 timers + arch timers
>> >
>> > We also default to the hstimer only for the A10s/A13 which aren't
>> > affected by this patch series afaics.
>> >
>> > We also enable the HS timer for the A31, but just like the A20 it
>> > doesn't use it by default, so it's probably been broken there too.
>> >
>> > I guess one way to fix it would be to switch the HS timer driver to a
>> > lower priority than the A10 timer, so we pick that up by default instead
>> > for the A10s/A13, and then convert the HS timer driver to a proper
>> > platform_device driver that will be able to get its clock.
>> >
>> > The downside is that the A13 will lose some precision over its default
>> > timer, but I don't think it's a big deal.
>>
>> The options I see are converting the hstimer to a platform device or
>> reverting the change to the sun4i ccu driver.
>>
>> I don't personally have much of an opinion on this since my systems
>> aren't affected. The only reason I looked at it was that I noticed
>> a new error message in the kernel logs.
>
> Thanks for the report then. I'm not really working on that anymore, so I
> won't submit a fix for this either.
I can have a go at converting it to a platform device if you think
that's the right approach. I don't have anything other than A20 to
test it on, though.
--
M?ns Rullg?rd