2024-06-12 17:33:23

by Sebastian Reichel

[permalink] [raw]
Subject: [PATCH v5 4/5] arm64: dts: rockchip: Add VEPU121 to RK3588

From: Emmanuel Gil Peyrot <[email protected]>

RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
but can be used as a cluster (i.e. sharing work between the cores).
These cores are called VEPU121 in the TRM. The TRM describes one more
VEPU121, but that is combined with a Hantro H1. That one will be handled
using the VPU binding instead.

Signed-off-by: Emmanuel Gil Peyrot <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 6ac5ac8b48ab..9edbcfe778ca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1159,6 +1159,86 @@ power-domain@RK3588_PD_SDMMC {
};
};

+ jpeg_enc0: video-codec@fdba0000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba0000 0x0 0x800>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc0_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc0_mmu: iommu@fdba0800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba0800 0x0 0x40>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc1: video-codec@fdba4000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba4000 0x0 0x800>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc1_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc1_mmu: iommu@fdba4800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba4800 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc2: video-codec@fdba8000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba8000 0x0 0x800>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc2_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc2_mmu: iommu@fdba8800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdba8800 0x0 0x40>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
+ jpeg_enc3: video-codec@fdbac000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdbac000 0x0 0x800>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "hclk";
+ iommus = <&jpeg_enc3_mmu>;
+ power-domains = <&power RK3588_PD_VDPU>;
+ };
+
+ jpeg_enc3_mmu: iommu@fdbac800 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdbac800 0x0 0x40>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VDPU>;
+ #iommu-cells = <0>;
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
2.43.0



2024-06-12 20:21:18

by Nicolas Dufresne

[permalink] [raw]
Subject: Re: [PATCH v5 4/5] arm64: dts: rockchip: Add VEPU121 to RK3588

Hi Sebastian,

Le mercredi 12 juin 2024 à 19:15 +0200, Sebastian Reichel a écrit :
> From: Emmanuel Gil Peyrot <[email protected]>
>
> RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
> but can be used as a cluster (i.e. sharing work between the cores).
> These cores are called VEPU121 in the TRM. The TRM describes one more
> VEPU121, but that is combined with a Hantro H1. That one will be handled
> using the VPU binding instead.
>
> Signed-off-by: Emmanuel Gil Peyrot <[email protected]>
> Signed-off-by: Sebastian Reichel <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 6ac5ac8b48ab..9edbcfe778ca 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -1159,6 +1159,86 @@ power-domain@RK3588_PD_SDMMC {
> };
> };
>
> + jpeg_enc0: video-codec@fdba0000 {
> + compatible = "rockchip,rk3588-vepu121";

As discussed earlier, VEPU121 is an modifier Hantro H1 encoder core that also
supports VP8 and H.264 encoding (even though RK vendor kernel only expose them
for jpeg encoding). The compatible follow this idea, shall we change the alias
now ?

Nicolas

> + reg = <0x0 0xfdba0000 0x0 0x800>;
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> + clock-names = "aclk", "hclk";
> + iommus = <&jpeg_enc0_mmu>;
> + power-domains = <&power RK3588_PD_VDPU>;
> + };
> +
> + jpeg_enc0_mmu: iommu@fdba0800 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdba0800 0x0 0x40>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_VDPU>;
> + #iommu-cells = <0>;
> + };
> +
> + jpeg_enc1: video-codec@fdba4000 {
> + compatible = "rockchip,rk3588-vepu121";
> + reg = <0x0 0xfdba4000 0x0 0x800>;
> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> + clock-names = "aclk", "hclk";
> + iommus = <&jpeg_enc1_mmu>;
> + power-domains = <&power RK3588_PD_VDPU>;
> + };
> +
> + jpeg_enc1_mmu: iommu@fdba4800 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdba4800 0x0 0x40>;
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_VDPU>;
> + #iommu-cells = <0>;
> + };
> +
> + jpeg_enc2: video-codec@fdba8000 {
> + compatible = "rockchip,rk3588-vepu121";
> + reg = <0x0 0xfdba8000 0x0 0x800>;
> + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> + clock-names = "aclk", "hclk";
> + iommus = <&jpeg_enc2_mmu>;
> + power-domains = <&power RK3588_PD_VDPU>;
> + };
> +
> + jpeg_enc2_mmu: iommu@fdba8800 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdba8800 0x0 0x40>;
> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_VDPU>;
> + #iommu-cells = <0>;
> + };
> +
> + jpeg_enc3: video-codec@fdbac000 {
> + compatible = "rockchip,rk3588-vepu121";
> + reg = <0x0 0xfdbac000 0x0 0x800>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> + clock-names = "aclk", "hclk";
> + iommus = <&jpeg_enc3_mmu>;
> + power-domains = <&power RK3588_PD_VDPU>;
> + };
> +
> + jpeg_enc3_mmu: iommu@fdbac800 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdbac800 0x0 0x40>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_VDPU>;
> + #iommu-cells = <0>;
> + };
> +
> av1d: video-codec@fdc70000 {
> compatible = "rockchip,rk3588-av1-vpu";
> reg = <0x0 0xfdc70000 0x0 0x800>;


2024-06-12 22:50:33

by Sebastian Reichel

[permalink] [raw]
Subject: Re: [PATCH v5 4/5] arm64: dts: rockchip: Add VEPU121 to RK3588

Hi,

On Wed, Jun 12, 2024 at 04:20:57PM GMT, Nicolas Dufresne wrote:
> Hi Sebastian,
>
> Le mercredi 12 juin 2024 ? 19:15 +0200, Sebastian Reichel a ?crit?:
> > From: Emmanuel Gil Peyrot <[email protected]>
> >
> > RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
> > but can be used as a cluster (i.e. sharing work between the cores).
> > These cores are called VEPU121 in the TRM. The TRM describes one more
> > VEPU121, but that is combined with a Hantro H1. That one will be handled
> > using the VPU binding instead.
> >
> > Signed-off-by: Emmanuel Gil Peyrot <[email protected]>
> > Signed-off-by: Sebastian Reichel <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
> > 1 file changed, 80 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > index 6ac5ac8b48ab..9edbcfe778ca 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> > @@ -1159,6 +1159,86 @@ power-domain@RK3588_PD_SDMMC {
> > };
> > };
> >
> > + jpeg_enc0: video-codec@fdba0000 {
> > + compatible = "rockchip,rk3588-vepu121";
>
> As discussed earlier, VEPU121 is an modifier Hantro H1 encoder core that also
> supports VP8 and H.264 encoding (even though RK vendor kernel only expose them
> for jpeg encoding). The compatible follow this idea, shall we change the alias
> now?

Makes sense. Do you have any preference for the alias Heiko?
Maybe vepu121_0 / vepu121_0_mmu?

-- Sebastian

>
> Nicolas
>
> > + reg = <0x0 0xfdba0000 0x0 0x800>;
> > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> > + clock-names = "aclk", "hclk";
> > + iommus = <&jpeg_enc0_mmu>;
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + };
> > +
> > + jpeg_enc0_mmu: iommu@fdba0800 {
> > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> > + reg = <0x0 0xfdba0800 0x0 0x40>;
> > + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> > + clock-names = "aclk", "iface";
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + #iommu-cells = <0>;
> > + };
> > +
> > + jpeg_enc1: video-codec@fdba4000 {
> > + compatible = "rockchip,rk3588-vepu121";
> > + reg = <0x0 0xfdba4000 0x0 0x800>;
> > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> > + clock-names = "aclk", "hclk";
> > + iommus = <&jpeg_enc1_mmu>;
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + };
> > +
> > + jpeg_enc1_mmu: iommu@fdba4800 {
> > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> > + reg = <0x0 0xfdba4800 0x0 0x40>;
> > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> > + clock-names = "aclk", "iface";
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + #iommu-cells = <0>;
> > + };
> > +
> > + jpeg_enc2: video-codec@fdba8000 {
> > + compatible = "rockchip,rk3588-vepu121";
> > + reg = <0x0 0xfdba8000 0x0 0x800>;
> > + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> > + clock-names = "aclk", "hclk";
> > + iommus = <&jpeg_enc2_mmu>;
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + };
> > +
> > + jpeg_enc2_mmu: iommu@fdba8800 {
> > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> > + reg = <0x0 0xfdba8800 0x0 0x40>;
> > + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> > + clock-names = "aclk", "iface";
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + #iommu-cells = <0>;
> > + };
> > +
> > + jpeg_enc3: video-codec@fdbac000 {
> > + compatible = "rockchip,rk3588-vepu121";
> > + reg = <0x0 0xfdbac000 0x0 0x800>;
> > + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> > + clock-names = "aclk", "hclk";
> > + iommus = <&jpeg_enc3_mmu>;
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + };
> > +
> > + jpeg_enc3_mmu: iommu@fdbac800 {
> > + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> > + reg = <0x0 0xfdbac800 0x0 0x40>;
> > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> > + clock-names = "aclk", "iface";
> > + power-domains = <&power RK3588_PD_VDPU>;
> > + #iommu-cells = <0>;
> > + };
> > +
> > av1d: video-codec@fdc70000 {
> > compatible = "rockchip,rk3588-av1-vpu";
> > reg = <0x0 0xfdc70000 0x0 0x800>;
>

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