SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
Update configure SGMII function with rx clk divider programming.
Fixes: 463120c31c58 ("net: stmmac: dwmac-qcom-ethqos: add support for SGMII")
Signed-off-by: Sneh Shah <[email protected]>
---
v2 changelog:
- Use FIELD_PREP to prepare bifield values in place of GENMASK
- Add fixes tag
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index d3bf42d0fceb..df6ff8bcdb5c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -34,6 +34,7 @@
#define RGMII_CONFIG_LOOPBACK_EN BIT(2)
#define RGMII_CONFIG_PROG_SWAP BIT(1)
#define RGMII_CONFIG_DDR_MODE BIT(0)
+#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
/* SDCC_HC_REG_DLL_CONFIG fields */
#define SDCC_DLL_CONFIG_DLL_RST BIT(30)
@@ -617,6 +618,9 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
case SPEED_10:
val |= ETHQOS_MAC_CTRL_PORT_SEL;
val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
+ rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
+ FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31),
+ RGMII_IO_MACRO_CONFIG);
break;
}
--
2.17.1
On Fri, Dec 01, 2023 at 03:35:48PM +0530, Sneh Shah wrote:
> SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
> Update configure SGMII function with rx clk divider programming.
> [PATCH v2] net: stmmac: update Rx clk divider for 10M SGMII
It would be better to add "dwmac-qcom-ethqos" prefix to the subject
since the patch concerns the Qualcomm Eth MAC only.
-Serge(y)
>
> Fixes: 463120c31c58 ("net: stmmac: dwmac-qcom-ethqos: add support for SGMII")
> Signed-off-by: Sneh Shah <[email protected]>
> ---
> v2 changelog:
> - Use FIELD_PREP to prepare bifield values in place of GENMASK
> - Add fixes tag
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index d3bf42d0fceb..df6ff8bcdb5c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -34,6 +34,7 @@
> #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
> #define RGMII_CONFIG_PROG_SWAP BIT(1)
> #define RGMII_CONFIG_DDR_MODE BIT(0)
> +#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
>
> /* SDCC_HC_REG_DLL_CONFIG fields */
> #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
> @@ -617,6 +618,9 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
> case SPEED_10:
> val |= ETHQOS_MAC_CTRL_PORT_SEL;
> val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
> + rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
> + FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31),
> + RGMII_IO_MACRO_CONFIG);
> break;
> }
>
> --
> 2.17.1
>
>
On Fri, Dec 01, 2023 at 03:35:48PM +0530, Sneh Shah wrote:
> SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
> Update configure SGMII function with rx clk divider programming.
>
> Fixes: 463120c31c58 ("net: stmmac: dwmac-qcom-ethqos: add support for SGMII")
> Signed-off-by: Sneh Shah <[email protected]>
Tested-by: Andrew Halaney <[email protected]> # sa8775p-ride
I can confirm that without this patch traffic doesn't seem to work when
I force things in to SPEED_10 with ethtool (which required another
change to this driver in stmmac_ethtool.c to do so, which as far as I
understand Sarosh from your group will be upstreaming soon and is an
independent issue).
I am curious, I expected to see some dropped/errors output in ip link
when things weren't working. I guess the sgmii phy in the soc is
rejecting these prior to handing them to the mac? Or am I
misunderstanding how that works?
> ---
> v2 changelog:
> - Use FIELD_PREP to prepare bifield values in place of GENMASK
> - Add fixes tag
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index d3bf42d0fceb..df6ff8bcdb5c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -34,6 +34,7 @@
> #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
> #define RGMII_CONFIG_PROG_SWAP BIT(1)
> #define RGMII_CONFIG_DDR_MODE BIT(0)
> +#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
>
> /* SDCC_HC_REG_DLL_CONFIG fields */
> #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
> @@ -617,6 +618,9 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
> case SPEED_10:
> val |= ETHQOS_MAC_CTRL_PORT_SEL;
> val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
> + rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
> + FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31),
> + RGMII_IO_MACRO_CONFIG);
Russell requested a comment about why you must program this every time,
I think it's a good idea too: https://lore.kernel.org/netdev/[email protected]/
Also on my wishlist is making 0x31 less magic, but Santa might not bring
that for me :)
> break;
> }
>
> --
> 2.17.1
>
>