2016-03-23 22:05:49

by Matthew McClintock

Subject: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

CC: [email protected]
CC: [email protected]
Signed-off-by: Matthew McClintock <[email protected]>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb9f16a..b68ae42 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
qca_mux_##f14 \
}, \
.nfuncs = 15, \
- .ctl_reg = 0x1000 + 0x10 * id, \
- .io_reg = 0x1004 + 0x10 * id, \
- .intr_cfg_reg = 0x1008 + 0x10 * id, \
- .intr_status_reg = 0x100c + 0x10 * id, \
- .intr_target_reg = 0x400 + 0x4 * id, \
+ .ctl_reg = 0x0 + 0x1000 * id, \
+ .io_reg = 0x4 + 0x1000 * id, \
+ .intr_cfg_reg = 0x8 + 0x1000 * id, \
+ .intr_status_reg = 0xc + 0x1000 * id, \
+ .intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2016-03-25 21:31:18

by Bjorn Andersson

Subject: Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote:

> For this SoC the register offsets changed from previous versions to be
> separated by a larger amount.
>
> CC: [email protected]

So the HW guys changed the register layout of the TLMM block? Matches
the layout of contemporary MSMs, so I see no problems with this.

Acked-by: [email protected]

Regards,
Bjorn

> Signed-off-by: Matthew McClintock <[email protected]>
> ---
> drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index cb9f16a..b68ae42 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
> qca_mux_##f14 \
> }, \
> .nfuncs = 15, \
> - .ctl_reg = 0x1000 + 0x10 * id, \
> - .io_reg = 0x1004 + 0x10 * id, \
> - .intr_cfg_reg = 0x1008 + 0x10 * id, \
> - .intr_status_reg = 0x100c + 0x10 * id, \
> - .intr_target_reg = 0x400 + 0x4 * id, \
> + .ctl_reg = 0x0 + 0x1000 * id, \
> + .io_reg = 0x4 + 0x1000 * id, \
> + .intr_cfg_reg = 0x8 + 0x1000 * id, \
> + .intr_status_reg = 0xc + 0x1000 * id, \
> + .intr_target_reg = 0x8 + 0x1000 * id, \
> .mux_bit = 2, \
> .pull_bit = 0, \
> .drv_bit = 6, \
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

2016-03-31 09:57:11

by Linus Walleij

Subject: Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets

On Wed, Mar 23, 2016 at 11:04 PM, Matthew McClintock
<[email protected]> wrote:

> For this SoC the register offsets changed from previous versions to be
> separated by a larger amount.
>
> CC: [email protected]
> CC: [email protected]
> Signed-off-by: Matthew McClintock <[email protected]>

Patch applied for fixes with Björn's ACK.

Yours,
Linus Walleij