2018-10-25 11:07:00

by Maxim Uvarov

Subject: [PATCH] dp83867: fix speed 10 in sgmii mode

For support 10Mps sped in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit
of DP83867_10M_SGMII_CFG register has to be cleared by software.
That does not affect speeds 100 and 1000 so can be done on init.

Signed-off-by: Max Uvarov <[email protected]>
---
http://www.ti.com/lit/ds/symlink/dp83867e.pdf
page 87 for register bits
and
page 23 last sentance that bit needs to be cleared.

drivers/net/phy/dp83867.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index ab58224f897f..1df4da3f70a9 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -37,6 +37,7 @@
#define DP83867_STRAP_STS1 0x006E
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
+#define DP83867_10M_SGMII_CFG 0x016F

#define DP83867_SW_RESET BIT(15)
#define DP83867_SW_RESTART BIT(14)
@@ -79,6 +80,9 @@
/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)

+/* 10M_SGMII_CFG bits */
+#define DP83867_10M_SGMII_RATE_ADAPT BIT(7)
+
enum {
DP83867_PORT_MIRROING_KEEP,
DP83867_PORT_MIRROING_EN,
@@ -285,6 +289,24 @@ static int dp83867_config_init(struct phy_device *phydev)
}
}

+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ /* For support SPEED_10 in SGMII mode
+ * DP83867_10M_SGMII_RATE_ADAPT bit
+ * has to be cleared by software. That
+ * does not affect SPEED_100 and
+ * SPEED_1000.
+ */
+ val = phy_read_mmd(phydev, DP83867_DEVADDR,
+ DP83867_10M_SGMII_CFG);
+ val &= ~DP83867_10M_SGMII_RATE_ADAPT;
+ ret = phy_write_mmd(phydev, DP83867_DEVADDR,
+ DP83867_10M_SGMII_CFG, val);
+ if (ret) {
+ WARN_ONCE(1, "dp83867: error DP83867_10M_SGMII_CFG read\n");
+ return ret;
+ }
+ }
+
/* Enable Interrupt output INT_OE in CFG3 register */
if (phy_interrupt_is_valid(phydev)) {
val = phy_read(phydev, DP83867_CFG3);
--
2.17.1

2018-10-25 23:06:52

by Andrew Lunn

Subject: Re: [PATCH] dp83867: fix speed 10 in sgmii mode

On Thu, Oct 25, 2018 at 02:05:30PM +0300, Max Uvarov wrote:

Hi Max

> For support 10Mps sped in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit

speed.

> of DP83867_10M_SGMII_CFG register has to be cleared by software.
> That does not affect speeds 100 and 1000 so can be done on init.

It would be good to add a Fixes: tag. Has this always been broken?

Thanks
Andrew

2018-12-06 18:29:04

by Maxim Uvarov

Subject: Re: [PATCH] dp83867: fix speed 10 in sgmii mode

пт, 26 окт. 2018 г. в 02:06, Andrew Lunn <[email protected]>:
>
> On Thu, Oct 25, 2018 at 02:05:30PM +0300, Max Uvarov wrote:
>
> Hi Max
>
> > For support 10Mps sped in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit
>
> speed.
>
> > of DP83867_10M_SGMII_CFG register has to be cleared by software.
> > That does not affect speeds 100 and 1000 so can be done on init.
>
> It would be good to add a Fixes: tag. Has this always been broken?
>

I somehow skipped this reply. I guess that was always broken. More
likely 10M is not the speed what people use nowadays. But anyway it
will be great to fix anyway.

Max.

> Thanks
> Andrew