This patch series adds support for Qualcomm's On Chip MEMory (OCMEM)
that is needed in order to support some a3xx and a4xx-based GPUs
upstream. This is based on Rob Clark's patch series that he submitted
in October 2015 and I am resubmitting updated patches with his
permission. See the individual patches for the changelog.
This was tested with the GPU on a LG Nexus 5 (hammerhead) phone and
this will work on other msm8974-based systems. For a summary of what
currently works upstream on the Nexus 5, see my status page at
https://masneyb.github.io/nexus-5-upstream/.
Changes since v6:
- link to gmu-sram child node in device tree
- add ranges property to ocmem example in adreno GMU example (patch 2)
to match bindings in patch 1
See individual patches for changelogs for previous versions.
Brian Masney (5):
dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings
dt-bindings: display: msm: gmu: add optional ocmem property
soc: qcom: add OCMEM driver
drm/msm/gpu: add ocmem init/cleanup functions
ARM: qcom_defconfig: add ocmem support
Rob Clark (2):
firmware: qcom: scm: add OCMEM lock/unlock interface
firmware: qcom: scm: add support to restore secure config to
qcm_scm-32
.../devicetree/bindings/display/msm/gmu.txt | 51 +++
.../devicetree/bindings/sram/qcom,ocmem.yaml | 96 ++++
arch/arm/configs/qcom_defconfig | 1 +
drivers/firmware/qcom_scm-32.c | 52 ++-
drivers/firmware/qcom_scm-64.c | 12 +
drivers/firmware/qcom_scm.c | 53 +++
drivers/firmware/qcom_scm.h | 9 +
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 28 +-
drivers/gpu/drm/msm/adreno/a3xx_gpu.h | 3 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 25 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.h | 3 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 40 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +
drivers/soc/qcom/Kconfig | 10 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/ocmem.c | 433 ++++++++++++++++++
include/linux/qcom_scm.h | 26 ++
include/soc/qcom/ocmem.h | 62 +++
19 files changed, 871 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
create mode 100644 drivers/soc/qcom/ocmem.c
create mode 100644 include/soc/qcom/ocmem.h
--
2.21.0
Add device tree bindings for the On Chip Memory (OCMEM) that is present
on some Qualcomm Snapdragon SoCs.
Signed-off-by: Brian Masney <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since v6:
- None
Changes since v5:
- None
Changes since v4:
- remove qcom from path in $id
Changes since v3:
- add ranges property
- remove unnecessary literal block |
- add #address-cells and #size-cells to binding
- rename path devicetree/bindings/sram/qcom/ to devicetree/bindings/sram/ since
this is the only qcom binding in the sram namespace. That was a holdover from
when I originally put this in the soc namespace.
Changes since v2:
- Add *-sram node and gmu-sram to example.
Changes since v1:
- Rename qcom,ocmem-msm8974 to qcom,msm8974-ocmem
- Renamed reg-names to ctrl and mem
- update hardware description
- moved from soc to sram namespace in the device tree bindings
.../devicetree/bindings/sram/qcom,ocmem.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
new file mode 100644
index 000000000000..222990f9923c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs.
+
+maintainers:
+ - Brian Masney <[email protected]>
+
+description: |
+ The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and
+ audio components on some Snapdragon SoCs.
+
+properties:
+ compatible:
+ const: qcom,msm8974-ocmem
+
+ reg:
+ items:
+ - description: Control registers
+ - description: OCMEM address range
+
+ reg-names:
+ items:
+ - const: ctrl
+ - const: mem
+
+ clocks:
+ items:
+ - description: Core clock
+ - description: Interface clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#address-cells'
+ - '#size-cells'
+
+patternProperties:
+ "^.+-sram$":
+ type: object
+ description: A region of reserved memory.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ ranges:
+ maxItems: 1
+
+ required:
+ - reg
+ - ranges
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
+
+ ocmem: ocmem@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl",
+ "mem";
+
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core",
+ "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu-sram@0 {
+ reg = <0x0 0x100000>;
+ ranges = <0 0 0xfec00000 0x100000>;
+ };
+ };
--
2.21.0
Add ocmem driver that's needed for some a3xx and a4xx based systems.
Signed-off-by: Brian Masney <[email protected]>
---
Changes since v6:
- None
Changes since v5:
- None
This patch was introduced in v5.
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 34433bf5885d..595e1910ba78 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -225,6 +225,7 @@ CONFIG_QCOM_WCNSS_PIL=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_OCMEM=y
CONFIG_QCOM_PM=y
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMD_RPM=y
--
2.21.0
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
must use the On Chip MEMory (OCMEM) in order to be functional. Add the
optional ocmem property to the Adreno Graphics Management Unit bindings.
Signed-off-by: Brian Masney <[email protected]>
---
Changes since v6:
- link to gmu-sram in example
- add ranges property to ocmem example to match bindings
Changes since v5:
- rename ocmem property to sram to match what TI currently has.
Changes since v4:
- None
Changes since v3:
- correct link to qcom,ocmem.yaml
Changes since v2:
- Add a3xx example with OCMEM
Changes since v1:
- None
.../devicetree/bindings/display/msm/gmu.txt | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
index 90af5b0a56a9..bf9c7a2a495c 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -31,6 +31,10 @@ Required properties:
- iommus: phandle to the adreno iommu
- operating-points-v2: phandle to the OPP operating points
+Optional properties:
+- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
+ SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
+
Example:
/ {
@@ -63,3 +67,50 @@ Example:
operating-points-v2 = <&gmu_opp_table>;
};
};
+
+a3xx example with OCMEM support:
+
+/ {
+ ...
+
+ gpu: adreno@fdb00000 {
+ compatible = "qcom,adreno-330.2",
+ "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names = "core",
+ "iface",
+ "mem_iface";
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ sram = <&gmu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+ iommus = <&gpu_iommu 0>;
+ };
+
+ ocmem@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl",
+ "mem";
+
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core",
+ "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x100000>;
+ ranges = <0 0 0xfec00000 0x100000>;
+ };
+ };
+};
--
2.21.0
On Fri, Aug 23, 2019 at 7:16 AM Brian Masney <[email protected]> wrote:
>
> Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
> must use the On Chip MEMory (OCMEM) in order to be functional. Add the
> optional ocmem property to the Adreno Graphics Management Unit bindings.
>
> Signed-off-by: Brian Masney <[email protected]>
> ---
> Changes since v6:
> - link to gmu-sram in example
> - add ranges property to ocmem example to match bindings
>
> Changes since v5:
> - rename ocmem property to sram to match what TI currently has.
>
> Changes since v4:
> - None
>
> Changes since v3:
> - correct link to qcom,ocmem.yaml
>
> Changes since v2:
> - Add a3xx example with OCMEM
>
> Changes since v1:
> - None
>
> .../devicetree/bindings/display/msm/gmu.txt | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
Reviewed-by: Rob Herring <[email protected]>
Hi Rob C / Sean P,
On Fri, Aug 23, 2019 at 05:16:30AM -0700, Brian Masney wrote:
> This patch series adds support for Qualcomm's On Chip MEMory (OCMEM)
> that is needed in order to support some a3xx and a4xx-based GPUs
> upstream. This is based on Rob Clark's patch series that he submitted
> in October 2015 and I am resubmitting updated patches with his
> permission. See the individual patches for the changelog.
I talked to Bjorn in person at the Embedded Linux Conference over a
week ago about this series. He thinks that this series should go through
your tree. I assume it's too late for the upcoming merge window, which
is fine. I just want to make sure that this series gets picked up for
the following merge window.
I just sent out a fix for a compiler error on MIPS as a separate patch:
https://lore.kernel.org/lkml/[email protected]/
Brian