On 07/12/2022 07.38, Janne Grunau wrote:
> The t8103 CPU nodes are missing the cache hierarchy information. The
> cache hierarchy on Arm can not be detected and needs to be described in
> DT. The OS scheduler can make use of this information for scheduling
> decisions.
>
> The cache size information is based on various articles about the
> processors. There's also an L3 system level cache (SLC). It's not
> described here because SLCs typically have some MMIO interface which
> would need to be described.
>
> Based on Rob Herring's patch adding cache properties and nodes for
> t600x.
>
> Link: https://lore.kernel.org/asahi/[email protected]/
>
> Signed-off-by: Janne Grunau <[email protected]>
Acked-by: Hector Martin <[email protected]>
Thanks! Applied to asahi-soc/dt.
- Hector