The WKUP_PADCONFIG register region in J7200 has multiple non-addressable
regions, split the existing wkup_pmx region as follows to avoid the
non-addressable regions and include all valid WKUP_PADCONFIG registers.
Also update references to old nodes with new ones.
wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15)
wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84)
wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)
J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
https://www.ti.com/lit/ds/symlink/dra821u.pdf
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vaishnav Achath <[email protected]>
---
.../dts/ti/k3-j7200-common-proc-board.dts | 2 +-
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 29 ++++++++++++++++++-
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6240856e4863..0d39d6b8cc0c 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -80,7 +80,7 @@
};
};
-&wkup_pmx0 {
+&wkup_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index fe669deba489..de56a0165bd0 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -56,7 +56,34 @@
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x4301c000 0x00 0x178>;
+ reg = <0x00 0x4301c000 0x00 0x34>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx1: pinctrl@0x4301c038 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c038 0x00 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx2: pinctrl@0x4301c068 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c068 0x00 0xec>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_pmx3: pinctrl@0x4301c174 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c174 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
--
2.17.1
On 19/01/23 09:56, Vaishnav Achath wrote:
> The WKUP_PADCONFIG register region in J7200 has multiple non-addressable
> regions, split the existing wkup_pmx region as follows to avoid the
> non-addressable regions and include all valid WKUP_PADCONFIG registers.
> Also update references to old nodes with new ones.
>
> wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
> wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15)
> wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84)
> wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)
>
> J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
> https://www.ti.com/lit/ds/symlink/dra821u.pdf
>
> Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
>
> Signed-off-by: Vaishnav Achath <[email protected]>
Reviewed-by: Jayesh Choudhary <[email protected]>
> ---
> .../dts/ti/k3-j7200-common-proc-board.dts | 2 +-
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 29 ++++++++++++++++++-
> 2 files changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6240856e4863..0d39d6b8cc0c 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -80,7 +80,7 @@
> };
> };
>
> -&wkup_pmx0 {
> +&wkup_pmx2 {
> mcu_cpsw_pins_default: mcu-cpsw-pins-default {
> pinctrl-single,pins = <
> J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index fe669deba489..de56a0165bd0 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -56,7 +56,34 @@
> wkup_pmx0: pinctrl@4301c000 {
> compatible = "pinctrl-single";
> /* Proxy 0 addressing */
> - reg = <0x00 0x4301c000 0x00 0x178>;
> + reg = <0x00 0x4301c000 0x00 0x34>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + wkup_pmx1: pinctrl@0x4301c038 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x4301c038 0x00 0x8>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + wkup_pmx2: pinctrl@0x4301c068 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x4301c068 0x00 0xec>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + wkup_pmx3: pinctrl@0x4301c174 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x4301c174 0x00 0x20>;
> #pinctrl-cells = <1>;
> pinctrl-single,register-width = <32>;
> pinctrl-single,function-mask = <0xffffffff>;
Hi Vaishnav Achath,
On Thu, 19 Jan 2023 09:56:22 +0530, Vaishnav Achath wrote:
> The WKUP_PADCONFIG register region in J7200 has multiple non-addressable
> regions, split the existing wkup_pmx region as follows to avoid the
> non-addressable regions and include all valid WKUP_PADCONFIG registers.
> Also update references to old nodes with new ones.
>
> wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
> wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15)
> wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84)
> wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/1] arm64: dts: ti: k3-j7200: Fix wakeup pinmux range
commit: 9ae21ac445e911e3541985c20052fc05d60f6879
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh