Hello,
This series adds missing device id property in mcu_navss device-tree node.
Also, the device-tree support for enabling MCU CPSW2G is added.
---
NOTE: While this series does not depend on any other series for being,
merged it depends on the following series for MCU CPSW2G functionality:
1. https://lore.kernel.org/r/[email protected]/
2. https://lore.kernel.org/r/[email protected]/
Siddharth Vadapalli (2):
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add device id property for
mcu_navss
arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 +++++++++++++++++++
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +
2 files changed, 49 insertions(+)
--
2.25.1
Add device tree support to enable MCU CPSW with J784S4 EVM.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 8cd4a7ecc121..05db64ed0706 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
};
};
+&wkup_pmx0 {
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
+ J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
+ J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
+ J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
+ J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
+ J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
+ J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
+ J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
+ J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
+ J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
+ J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
+ J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio-pins-default {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
+ J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
+ >;
+ };
+};
+
&main_uart8 {
status = "okay";
pinctrl-names = "default";
@@ -194,3 +220,24 @@ &main_sdhci1 {
&main_gpio0 {
status = "okay";
};
+
+&mcu_cpsw {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+ mcu_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&mcu_cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&mcu_phy0>;
+};
--
2.25.1
The "ti,sci-dev-id" property used to indicate the Device ID is missing
for mcu_navss device-tree node. Add it.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 93952af618f6..52311da15579 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -212,6 +212,8 @@ mcu_navss: bus@28380000{
dma-coherent;
dma-ranges;
+ ti,sci-dev-id = <323>;
+
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
--
2.25.1
Hello,
On 14-03-2023 16:10, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds missing device id property in mcu_navss device-tree node.
> Also, the device-tree support for enabling MCU CPSW2G is added.
>
> ---
> NOTE: While this series does not depend on any other series for being,
> merged it depends on the following series for MCU CPSW2G functionality:
> 1. https://lore.kernel.org/r/[email protected]/
> 2. https://lore.kernel.org/r/[email protected]/
Please do not merge this series until the above two series have been
merged. Otherwise, it will result in an indefinite probe deferral during
boot. By saying that this series does not depend on other series for
being merged, I meant to say that this series will apply cleanly without
any dependencies.
Regards,
Siddharth.
>
> Siddharth Vadapalli (2):
> arm64: dts: ti: k3-j784s4-mcu-wakeup: Add device id property for
> mcu_navss
> arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
>
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 +++++++++++++++++++
> .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +
> 2 files changed, 49 insertions(+)
>
On 3/14/23 5:40 AM, Siddharth Vadapalli wrote:
> Add device tree support to enable MCU CPSW with J784S4 EVM.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 ++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 8cd4a7ecc121..05db64ed0706 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
> };
> };
>
> +&wkup_pmx0 {
> + mcu_cpsw_pins_default: mcu-cpsw-pins-default {
> + pinctrl-single,pins = <
> + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
> + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
> + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
> + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
> + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
> + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
> + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
> + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
> + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
> + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
> + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
> + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
> + >;
> + };
> +
> + mcu_mdio_pins_default: mcu-mdio-pins-default {
> + pinctrl-single,pins = <
> + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
> + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
> + >;
> + };
> +};
> +
> &main_uart8 {
> status = "okay";
> pinctrl-names = "default";
> @@ -194,3 +220,24 @@ &main_sdhci1 {
> &main_gpio0 {
> status = "okay";
> };
> +
> +&mcu_cpsw {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
Move the mcu_mdio_pins_default pinctrl to the mdio node below.
Andrew
> +};
> +
> +&davinci_mdio {
> + mcu_phy0: ethernet-phy@0 {
> + reg = <0>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,min-output-impedance;
> + };
> +};
> +
> +&mcu_cpsw_port1 {
> + status = "okay";
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&mcu_phy0>;
> +};
Hello Andrew,
On 15/03/23 03:40, Andrew Davis wrote:
> On 3/14/23 5:40 AM, Siddharth Vadapalli wrote:
>> Add device tree support to enable MCU CPSW with J784S4 EVM.
>>
>> Signed-off-by: Siddharth Vadapalli <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 ++++++++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> index 8cd4a7ecc121..05db64ed0706 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35)
>> MCAN15_RX.GPIO0_8 */
>> };
>> };
>> +&wkup_pmx0 {
>> + mcu_cpsw_pins_default: mcu-cpsw-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
>> + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
>> + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
>> + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
>> + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
>> + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
>> + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
>> + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
>> + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
>> + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
>> + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
>> + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38)
>> MCU_RGMII1_TX_CTL */
>> + >;
>> + };
>> +
>> + mcu_mdio_pins_default: mcu-mdio-pins-default {
>> + pinctrl-single,pins = <
>> + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
>> + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
>> + >;
>> + };
>> +};
>> +
>> &main_uart8 {
>> status = "okay";
>> pinctrl-names = "default";
>> @@ -194,3 +220,24 @@ &main_sdhci1 {
>> &main_gpio0 {
>> status = "okay";
>> };
>> +
>> +&mcu_cpsw {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
>
> Move the mcu_mdio_pins_default pinctrl to the mdio node below.
Thank you for reviewing the patch. I will fix it and post the v2 patch.
Regards,
Siddharth.