This series modify the dts file to add the slink addresses,
make entry of slink in clock tables, defines SLINK addressed,
enable slink controller in Tegra30 based platform cardhu.
Laxman Dewangan (5):
ARM: tegra: Add slink controller base address
ARM: tegra: dts: add slink controller dt entry
ARM: tegra: fix clock entry of slink controller
ARM: tegra: dts: cardhu: enable SLINK4
ARM: tegra: config: enable spi driver for Tegra SLINK controller
arch/arm/boot/dts/tegra20.dtsi | 40 +++++++++++++++++++
arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 ++
arch/arm/boot/dts/tegra30.dtsi | 60 +++++++++++++++++++++++++++++
arch/arm/configs/tegra_defconfig | 2 +-
arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++
arch/arm/mach-tegra/board-dt-tegra30.c | 12 ++++++
arch/arm/mach-tegra/include/mach/iomap.h | 22 +++++++----
arch/arm/mach-tegra/tegra20_clocks_data.c | 16 ++++----
arch/arm/mach-tegra/tegra30_clocks_data.c | 36 +++++++++---------
9 files changed, 166 insertions(+), 35 deletions(-)
Add slink controller details in the dts file of
Tegra20 and Tegra30.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/boot/dts/tegra20.dtsi | 40 ++++++++++++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6934bca..d12a310 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -186,6 +186,46 @@
status = "disabled";
};
+ slink@7000d400 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-req-sel = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000d600 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-req-sel = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000d800 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-req-sel = <17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000da00 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-req-sel = <18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 81f5df4..f898911 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -191,6 +191,66 @@
status = "disabled";
};
+ slink@7000d400 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-req-sel = <15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000d600 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-req-sel = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000d800 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-req-sel = <17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000da00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-req-sel = <18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000dc00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-req-sel = <27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ slink@7000de00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-req-sel = <28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
pmc {
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
--
1.7.1.1
Add base address of all slink controller of Tegra20
and tegra30.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/mach-tegra/include/mach/iomap.h | 22 ++++++++++++++--------
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index fee3a94..0f46765 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -206,17 +206,23 @@
#define TEGRA_DVC_BASE 0x7000D000
#define TEGRA_DVC_SIZE SZ_512
-#define TEGRA_SPI1_BASE 0x7000D400
-#define TEGRA_SPI1_SIZE SZ_512
+#define TEGRA_SLINK1_BASE 0x7000D400
+#define TEGRA_SLINK1_SIZE SZ_512
-#define TEGRA_SPI2_BASE 0x7000D600
-#define TEGRA_SPI2_SIZE SZ_512
+#define TEGRA_SLINK2_BASE 0x7000D600
+#define TEGRA_SLINK2_SIZE SZ_512
-#define TEGRA_SPI3_BASE 0x7000D800
-#define TEGRA_SPI3_SIZE SZ_512
+#define TEGRA_SLINK3_BASE 0x7000D800
+#define TEGRA_SLINK3_SIZE SZ_512
-#define TEGRA_SPI4_BASE 0x7000DA00
-#define TEGRA_SPI4_SIZE SZ_512
+#define TEGRA_SLINK4_BASE 0x7000DA00
+#define TEGRA_SLINK4_SIZE SZ_512
+
+#define TEGRA_SLINK5_BASE 0x7000DC00
+#define TEGRA_SLINK5_SIZE SZ_512
+
+#define TEGRA_SLINK6_BASE 0x7000DE00
+#define TEGRA_SLINK6_SIZE SZ_512
#define TEGRA_RTC_BASE 0x7000E000
#define TEGRA_RTC_SIZE SZ_256
--
1.7.1.1
Enable SLINK4 in Tegra30 based platform Cardhu.
Setting maximum spi frequency to 25MHz.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index b245e6c..1bd73ea 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -275,6 +275,11 @@
};
};
+ slink@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
ahub {
i2s@70080400 {
status = "okay";
--
1.7.1.1
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/configs/tegra_defconfig | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fb29680..60e1b2e 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -117,7 +117,7 @@ CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_TEGRA=y
CONFIG_SPI=y
-CONFIG_SPI_TEGRA=y
+CONFIG_SPI_TEGRA20_SLINK=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
--
1.7.1.1
Fix the driver name, connection name and clock name
for slink controller clocks in clock table of
Tegra20 and Tegra30.
Signed-off-by: Laxman Dewangan <[email protected]>
---
arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++++
arch/arm/mach-tegra/board-dt-tegra30.c | 12 +++++++++
arch/arm/mach-tegra/tegra20_clocks_data.c | 16 ++++++------
arch/arm/mach-tegra/tegra30_clocks_data.c | 36 ++++++++++++++--------------
4 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 2053f74..2d6915e 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -90,6 +90,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
&tegra_ehci3_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK2_BASE, "spi-tegra-slink.1", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK3_BASE, "spi-tegra-slink.2", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK4_BASE, "spi-tegra-slink.3", NULL),
{}
};
@@ -109,6 +113,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
+ { "slink1", "pll_p", 100000000, false },
+ { "slink2", "pll_p", 100000000, false },
+ { "slink3", "pll_p", 100000000, false },
+ { "slink4", "pll_p", 100000000, false },
{ NULL, NULL, 0, 0},
};
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 9e6f79a..cf2defd 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -52,6 +52,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK2_BASE, "spi-tegra-slink.1", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK3_BASE, "spi-tegra-slink.2", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK4_BASE, "spi-tegra-slink.3", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK5_BASE, "spi-tegra-slink.4", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK6_BASE, "spi-tegra-slink.5", NULL),
{}
};
@@ -71,6 +77,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
+ { "slink1", "pll_p", 100000000, false},
+ { "slink2", "pll_p", 100000000, false},
+ { "slink3", "pll_p", 100000000, false},
+ { "slink4", "pll_p", 100000000, false},
+ { "slink5", "pll_p", 100000000, false},
+ { "slink6", "pll_p", 100000000, false},
{ NULL, NULL, 0, 0},
};
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 9615ee3..b23c99f 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -894,10 +894,10 @@ PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_c
PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
-PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink1, "spi-tegra-slink.0", "slink", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink2, "spi-tegra-slink.1", "slink", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink3, "spi-tegra-slink.2", "slink", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(slink4, "spi-tegra-slink.3", "slink", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
@@ -960,10 +960,10 @@ static struct clk *tegra_list_clks[] = {
&tegra_spi,
&tegra_xio,
&tegra_twc,
- &tegra_sbc1,
- &tegra_sbc2,
- &tegra_sbc3,
- &tegra_sbc4,
+ &tegra_slink1,
+ &tegra_slink2,
+ &tegra_slink3,
+ &tegra_slink4,
&tegra_ide,
&tegra_ndflash,
&tegra_vfir,
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 3d2e553..8fe2da8 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1046,12 +1046,12 @@ PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pll
PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
-PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
-PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink1, "spi-tegra-slink.0", "slink", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink2, "spi-tegra-slink.1", "slink", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink3, "spi-tegra-slink.2", "slink", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink4, "spi-tegra-slink.3", "slink", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink5, "spi-tegra-slink.4", "slink", 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(slink6, "spi-tegra-slink.5", "slink", 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
@@ -1163,12 +1163,12 @@ struct clk *tegra_list_clks[] = {
&tegra_hda,
&tegra_hda2codec_2x,
&tegra_hda2hdmi,
- &tegra_sbc1,
- &tegra_sbc2,
- &tegra_sbc3,
- &tegra_sbc4,
- &tegra_sbc5,
- &tegra_sbc6,
+ &tegra_slink1,
+ &tegra_slink2,
+ &tegra_slink3,
+ &tegra_slink4,
+ &tegra_slink5,
+ &tegra_slink6,
&tegra_sata_oob,
&tegra_sata,
&tegra_sata_cold,
@@ -1271,12 +1271,12 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
- CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
- CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
- CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
- CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
- CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
- CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+ CLK_DUPLICATE("slink1", "spi_slave_tegra.0", NULL),
+ CLK_DUPLICATE("slink2", "spi_slave_tegra.1", NULL),
+ CLK_DUPLICATE("slink3", "spi_slave_tegra.2", NULL),
+ CLK_DUPLICATE("slink4", "spi_slave_tegra.3", NULL),
+ CLK_DUPLICATE("slink5", "spi_slave_tegra.4", NULL),
+ CLK_DUPLICATE("slink6", "spi_slave_tegra.5", NULL),
CLK_DUPLICATE("twd", "smp_twd", NULL),
CLK_DUPLICATE("vcp", "nvavp", "vcp"),
CLK_DUPLICATE("i2s0", NULL, "i2s0"),
--
1.7.1.1
On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
> Add base address of all slink controller of Tegra20
> and tegra30.
Lets not add anything to iomap.h; we're trying to remove it. Instead,
just put the raw address in the AUXDATA; I assume that's the only place
these defines end up being used...
On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
> Add slink controller details in the dts file of
> Tegra20 and Tegra30.
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> + slink@7000d400 {
> + compatible = "nvidia,tegra20-slink";
> + reg = <0x7000d400 0x200>;
> + interrupts = <0 59 0x04>;
> + nvidia,dma-req-sel = <15>;
I thought the common DT DMA bindings were going to be in 3.7, and hence
we could just use them here rather than inventing another custom
property for this purpose?
On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
> Fix the driver name, connection name and clock name
> for slink controller clocks in clock table of
> Tegra20 and Tegra30.
The patch subject isn't entirely accurate here; this patch isn't just
about fixing clock entries.
> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
> @@ -90,6 +90,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
> &tegra_ehci3_pdata),
> OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
> OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
> + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
Here, can't we just use the existing device names in the clock files...
So we can completely drop the changes to these two files:
> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
> diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
The device names will hopefully be irrelevant once we're able to use
DT-based clock lookups.
On Friday 19 October 2012 04:09 AM, Stephen Warren wrote:
> On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
>> Add base address of all slink controller of Tegra20
>> and tegra30.
> Lets not add anything to iomap.h; we're trying to remove it. Instead,
> just put the raw address in the AUXDATA; I assume that's the only place
> these defines end up being used...
OK, I will drop this change and add the base address definition in the
AUXDATA file only.
On Friday 19 October 2012 04:11 AM, Stephen Warren wrote:
> On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
>> Add slink controller details in the dts file of
>> Tegra20 and Tegra30.
>> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
>> + slink@7000d400 {
>> + compatible = "nvidia,tegra20-slink";
>> + reg =<0x7000d400 0x200>;
>> + interrupts =<0 59 0x04>;
>> + nvidia,dma-req-sel =<15>;
> I thought the common DT DMA bindings were going to be in 3.7, and hence
> we could just use them here rather than inventing another custom
> property for this purpose?
Adding Vinod here.
I looked the dma devicetree bingind document and did not found the
generic binding name. Howvere, for arm-pl330.txt, it is explained as
Example:
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <99>;
};
Client drivers (device nodes requiring dma transfers from dev-to-mem or
mem-to-dev) should specify the DMA channel numbers using a two-value pair
as shown below.
[property name] = <[phandle of the dma controller] [dma request id]>;
where 'dma request id' is the dma request number which is connected
to the client controller. The 'property name' is recommended to be
of the form <name>-dma-channel.
Example: tx-dma-channel = <&pdma0 12>;
So here I can also add the name like same.
Vinod,
Do you see any issue in follow the above mechanism for Tegra dma client
driver?
Thanks,
Laxman
On Friday 19 October 2012 04:13 AM, Stephen Warren wrote:
>
> The patch subject isn't entirely accurate here; this patch isn't just
> about fixing clock entries.
>
OK, then will break in two patches.
>
>> + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE, "spi-tegra-slink.0", NULL),
> Here, can't we just use the existing device names in the clock files...
>
> So we can completely drop the changes to these two files:
>
I want to name the driver as spi-tegra-slink. When we add the sflash spi
driver for tegra20, the driver name will be spi-tegra-sflash.
Also current name is "spi_tegra" I do not want to name with "_". So it
is require to convert as "-".
>> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
>> diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
> The device names will hopefully be irrelevant once we're able to use
> DT-based clock lookups.
Agree, but currently we can add this to have progress.
On 10/19/2012 03:10 AM, Laxman Dewangan wrote:
> On Friday 19 October 2012 04:11 AM, Stephen Warren wrote:
>> On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
>>> Add slink controller details in the dts file of
>>> Tegra20 and Tegra30.
>>> diff --git a/arch/arm/boot/dts/tegra20.dtsi
>>> b/arch/arm/boot/dts/tegra20.dtsi
>>> + slink@7000d400 {
>>> + compatible = "nvidia,tegra20-slink";
>>> + reg =<0x7000d400 0x200>;
>>> + interrupts =<0 59 0x04>;
>>> + nvidia,dma-req-sel =<15>;
>
(Oh, you need a space before and after the = in all the lines above)
>> I thought the common DT DMA bindings were going to be in 3.7, and hence
>> we could just use them here rather than inventing another custom
>> property for this purpose?
>
> Adding Vinod here.
>
> I looked the dma devicetree bingind document and did not found the
> generic binding name. Howvere, for arm-pl330.txt, it is explained as ...
That's not the generic bindings. I guess they didn't get merged then. I
guess we can continue with custom bindings until they are.
On 10/19/2012 03:13 AM, Laxman Dewangan wrote:
> On Friday 19 October 2012 04:13 AM, Stephen Warren wrote:
>>> + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE,
>>> "spi-tegra-slink.0", NULL),
>> Here, can't we just use the existing device names in the clock files...
>>
>> So we can completely drop the changes to these two files:
>
> I want to name the driver as spi-tegra-slink. When we add the sflash spi
> driver for tegra20, the driver name will be spi-tegra-sflash.
> Also current name is "spi_tegra" I do not want to name with "_". So it
> is require to convert as "-".
The driver name is whatever you put into the driver file. The AUXDATA
only affects the device name. There should be no conflict with the
"sflash" driver, since that clock is set up to expect driver name "spi"
which doesn't conflict with "spi_tegra.*".
So, there's really no point in churning the clock names any more,
especially since it's temporary. If you feel strongly about this, the
best thing to do is help push Tegra's support of DT clock bindings forward.
On Fri, 2012-10-19 at 09:56 -0600, Stephen Warren wrote:
> On 10/19/2012 03:10 AM, Laxman Dewangan wrote:
> > On Friday 19 October 2012 04:11 AM, Stephen Warren wrote:
> >> On 10/18/2012 04:56 AM, Laxman Dewangan wrote:
> >>> Add slink controller details in the dts file of
> >>> Tegra20 and Tegra30.
> >>> diff --git a/arch/arm/boot/dts/tegra20.dtsi
> >>> b/arch/arm/boot/dts/tegra20.dtsi
> >>> + slink@7000d400 {
> >>> + compatible = "nvidia,tegra20-slink";
> >>> + reg =<0x7000d400 0x200>;
> >>> + interrupts =<0 59 0x04>;
> >>> + nvidia,dma-req-sel =<15>;
> >
>
> (Oh, you need a space before and after the = in all the lines above)
>
> >> I thought the common DT DMA bindings were going to be in 3.7, and hence
> >> we could just use them here rather than inventing another custom
> >> property for this purpose?
> >
> > Adding Vinod here.
> >
> > I looked the dma devicetree bingind document and did not found the
> > generic binding name. Howvere, for arm-pl330.txt, it is explained as ...
>
> That's not the generic bindings. I guess they didn't get merged then. I
> guess we can continue with custom bindings until they are.
Yes they are in topic topic/dmaengine_dt in my tree. Will be merged once
we sort out slave apis.
--
Vinod Koul
Intel Corp.