2024-04-16 05:35:34

by Pankaj Gupta

Subject: [PATCH v3 0/2] caam: init-clk based on caam-page0-access

v3:
- Splitting the patch into two.
- Disposed-off comments received on v2.

v2:
- Considering the OPTEE enablement check too, for setting the
variable 'reg_access'.

Pankaj Gupta (2):
caam: init-clk based on caam-page0-access
drivers: crypto: caam: i.MX8ULP donot have CAAM page0 access

drivers/crypto/caam/ctrl.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)

--
2.34.1

2024-04-16 05:35:59

by Pankaj Gupta

Subject: [PATCH v3 2/2] drivers: crypto: caam: i.MX8ULP donot have CAAM page0 access

iMX8ULP have a secure-enclave hardware IP called EdgeLock Enclave(ELE),
that control access to caam controller's register page, i.e., page0.

At all, if the ELE release access to CAAM controller's register page,
it will release to secure-world only.

Clocks are turned on automatically for iMX8ULP. There exists the caam
clock gating bit, but it is not advised to gate the clock at linux, as
optee-os or any other entity might be using it.

Signed-off-by: Pankaj Gupta <[email protected]>
---
drivers/crypto/caam/ctrl.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 247d42aa32df..f0f87fe8ef92 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -563,11 +563,14 @@ static const struct caam_imx_data caam_vf610_data = {
.num_clks = ARRAY_SIZE(caam_vf610_clks),
};

+static const struct caam_imx_data caam_imx8ulp_data;
+
static const struct soc_device_attribute caam_imx_soc_table[] = {
{ .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
{ .soc_id = "i.MX6*", .data = &caam_imx6_data },
{ .soc_id = "i.MX7*", .data = &caam_imx7_data },
{ .soc_id = "i.MX8M*", .data = &caam_imx7_data },
+ { .soc_id = "i.MX8ULP", .data = &caam_imx8ulp_data },
{ .soc_id = "VF*", .data = &caam_vf610_data },
{ .family = "Freescale i.MX" },
{ /* sentinel */ }
--
2.34.1

2024-04-18 14:54:01

by Horia Geanta

Subject: Re: [PATCH v3 2/2] drivers: crypto: caam: i.MX8ULP donot have CAAM page0 access

On 4/16/2024 8:35 AM, Pankaj Gupta wrote:
> iMX8ULP have a secure-enclave hardware IP called EdgeLock Enclave(ELE),
> that control access to caam controller's register page, i.e., page0.
>
> At all, if the ELE release access to CAAM controller's register page,
> it will release to secure-world only.
>
> Clocks are turned on automatically for iMX8ULP. There exists the caam
> clock gating bit, but it is not advised to gate the clock at linux, as
> optee-os or any other entity might be using it.
>
> Signed-off-by: Pankaj Gupta <[email protected]>
Reviewed-by: Horia Geantă <[email protected]>

Thanks,
Horia