This adds support for the Imagination Technologies hash accelerator which
provides hardware acceleration for SHA1 SHA244 SHA256 and MD5 hashes.
Tested on silicon, using testmgr.
Changes from V4:
* Moved clk_prepare_enable for both clocks into the probe function to
match the remove function, and avoid inflated prepare/enable counts.
Changes from V3:
* Standardised the cra_priorities to 300, sufficient to be chosen
ahead of software / assembly implementations.
* Addressed Andrew Bresticker's review comments, except for two items
that I will leave for when I have some more bandwidth if possible as
I don't think they are required:
->Runtime PM
->Threaded IRQ handler instead of a tasklet
Changes from V2:
* This hardware does not support importing a partial hash state,
so the init, update, final and finup have been reworked to use
a fallback driver; only digest remains as hardware accelerated.
* Simplified the driver as a result of the above rework
Changes from V1:
* Addressed review comments from Andrew Bresticker and
Vladimir Zapolskiy
* rebased to current linux-next
James Hartley (2):
This adds support for the Imagination Technologies hash accelerator
which provides hardware acceleration for SHA1 SHA224 SHA256 and
MD5 hashes.
This adds the binding documentation for the Imagination Technologies
hash accelerator that provides hardware acceleration for
SHA1/SHA224/SHA256/MD5 hashes. This hardware will be present
in the upcoming pistachio SoC.
.../devicetree/bindings/crypto/img-hash.txt | 27 +
drivers/crypto/Kconfig | 14 +
drivers/crypto/Makefile | 1 +
drivers/crypto/img-hash.c | 1030 ++++++++++++++++++++
4 files changed, 1072 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/img-hash.txt
create mode 100644 drivers/crypto/img-hash.c
--
1.7.9.5
This adds the binding documentation for the Imagination Technologies hash
accelerator that provides hardware acceleration for SHA1/SHA224/SHA256/MD5
hashes. This hardware will be present in the upcoming pistachio SoC.
Signed-off-by: James Hartley <[email protected]>
Reviewed-by: Andrew Bresticker <[email protected]>
---
.../devicetree/bindings/crypto/img-hash.txt | 27 ++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/img-hash.txt
diff --git a/Documentation/devicetree/bindings/crypto/img-hash.txt b/Documentation/devicetree/bindings/crypto/img-hash.txt
new file mode 100644
index 0000000..91a3d75
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/img-hash.txt
@@ -0,0 +1,27 @@
+Imagination Technologies hardware hash accelerator
+
+The hash accelerator provides hardware hashing acceleration for
+SHA1, SHA224, SHA256 and MD5 hashes
+
+Required properties:
+
+- compatible : "img,hash-accelerator"
+- reg : Offset and length of the register set for the module, and the DMA port
+- interrupts : The designated IRQ line for the hashing module.
+- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
+- dma-names : Should be "tx"
+- clocks : Clock specifiers
+- clock-names : "sys" Used to clock the hash block registers
+ "hash" Used to clock data through the accelerator
+
+Example:
+
+ hash: hash@18149600 {
+ compatible = "img,hash-accelerator";
+ reg = <0x18149600 0x100>, <0x18101100 0x4>;
+ interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 8 0xffffffff 0>;
+ dma-names = "tx";
+ clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
+ clock-names = "sys", "hash";
+ };
--
1.7.9.5
On Thu, Mar 12, 2015 at 11:17:25PM +0000, James Hartley wrote:
> This adds support for the Imagination Technologies hash accelerator which
> provides hardware acceleration for SHA1 SHA244 SHA256 and MD5 hashes.
>
> Tested on silicon, using testmgr.
All applied. Thanks!
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt