Add binding documentation for the Freescale RNGC found on
some i.MX2/3/5 SoCs.
Signed-off-by: Steffen Trumtrar <[email protected]>
---
Documentation/devicetree/bindings/rng/mxc_rngc.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/mxc_rngc.txt
diff --git a/Documentation/devicetree/bindings/rng/mxc_rngc.txt b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
new file mode 100644
index 000000000000..e147a6dde40a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
@@ -0,0 +1,16 @@
+Freescale RNGC (Random Number Generator Version C)
+
+Required properties:
+- compatible : Should be "fsl,imx25-rng"
+- reg : Offset and length of the register set of this block
+- interrupts : the interrupt number for the RNG block
+- clocks: should contain the RNG clk source
+
+Example:
+
+rng@53fb0000 {
+ compatible = "fsl,imx25-rng";
+ reg = <0x53fb0000 0x4000>;
+ interrupts = <22>;
+ clocks = <&trng_clk>;
+};
--
2.7.0
Add a devicetree entry for the Random Number Generator Version C (RNGC).
Signed-off-by: Steffen Trumtrar <[email protected]>
---
Changes in v2:
- remove interrupt-names from dtsi
arch/arm/boot/dts/imx25.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index cde329e9b9e3..ebf11d9f123e 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -397,6 +397,14 @@
interrupts = <41>;
};
+ rng: rng@53fb0000 {
+ compatible = "fsl,imx25-rng";
+ reg = <0x53fb0000 0x4000>;
+ clocks = <&clks 109>;
+ clock-names = "ipg";
+ interrupts = <22>;
+ };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
--
2.7.0
The driver is ported from Freescales Linux git and can be
found in the
vendor/freescale/imx_2.6.35_maintain
branch.
According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
The i.MX2x actually has an RNGB, which has no driver implementation
in Freescales kernel. However as it turns out, the driver for the RNGC
works fine on the (at least) i.MX25. So, they seem to be somewhat
compatible.
Signed-off-by: Steffen Trumtrar <[email protected]>
---
Changes in v2:
- remove irq variable from private struct
- move devm_request_irq from mxc_rngc_init to probe
- return irq in case of error
- handle irq 0 as error
drivers/char/hw_random/Kconfig | 13 ++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/mxc-rngc.c | 398 ++++++++++++++++++++++++++++++++++++++
3 files changed, 412 insertions(+)
create mode 100644 drivers/char/hw_random/mxc-rngc.c
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index dbf22719462f..9d6b5c42255b 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -255,6 +255,19 @@ config HW_RANDOM_MXC_RNGA
If unsure, say Y.
+config HW_RANDOM_MXC_RNGC
+ tristate "Freescale i.MX RNGC Random Number Generator"
+ depends on ARCH_MXC
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on some Freescale i.MX processors.
+
+ To compile this driver as a module, choose M here: the
+ module will be called mxc-rngc.
+
+ If unsure, say Y.
+
config HW_RANDOM_NOMADIK
tristate "ST-Ericsson Nomadik Random Number Generator support"
depends on ARCH_NOMADIK
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 5ad397635128..008463bcf662 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
+obj-$(CONFIG_HW_RANDOM_MXC_RNGC) += mxc-rngc.o
obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
obj-$(CONFIG_HW_RANDOM_PPC4XX) += ppc4xx-rng.o
diff --git a/drivers/char/hw_random/mxc-rngc.c b/drivers/char/hw_random/mxc-rngc.c
new file mode 100644
index 000000000000..3a2a9b2ad7db
--- /dev/null
+++ b/drivers/char/hw_random/mxc-rngc.c
@@ -0,0 +1,398 @@
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
+ * (c) Copyright 2003 Red Hat Inc <[email protected]>
+ *
+ * derived from
+ *
+ * Hardware driver for the AMD 768 Random Number Generator (RNG)
+ * (c) Copyright 2001 Red Hat Inc <[email protected]>
+ *
+ * derived from
+ *
+ * Hardware driver for Intel i810 Random Number Generator (RNG)
+ * Copyright 2000,2001 Jeff Garzik <[email protected]>
+ * Copyright 2000,2001 Philipp Rumpf <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/hw_random.h>
+#include <linux/completion.h>
+#include <linux/io.h>
+
+#define RNGC_VERSION_MAJOR3 3
+
+#define RNGC_VERSION_ID 0x0000
+#define RNGC_COMMAND 0x0004
+#define RNGC_CONTROL 0x0008
+#define RNGC_STATUS 0x000C
+#define RNGC_ERROR 0x0010
+#define RNGC_FIFO 0x0014
+#define RNGC_VERIF_CTRL 0x0020
+#define RNGC_OSC_CTRL_COUNT 0x0028
+#define RNGC_OSC_COUNT 0x002C
+#define RNGC_OSC_COUNT_STATUS 0x0030
+
+#define RNGC_VERID_ZEROS_MASK 0x0f000000
+#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000
+#define RNGC_VERID_RNG_TYPE_SHIFT 28
+#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000
+#define RNGC_VERID_CHIP_VERSION_SHIFT 16
+#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00
+#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
+#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff
+#define RNGC_VERID_VERSION_MINOR_SHIFT 0
+
+#define RNGC_CMD_ZEROS_MASK 0xffffff8c
+#define RNGC_CMD_SW_RST 0x00000040
+#define RNGC_CMD_CLR_ERR 0x00000020
+#define RNGC_CMD_CLR_INT 0x00000010
+#define RNGC_CMD_SEED 0x00000002
+#define RNGC_CMD_SELF_TEST 0x00000001
+
+#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c
+#define RNGC_CTRL_CTL_ACC 0x00000200
+#define RNGC_CTRL_VERIF_MODE 0x00000100
+#define RNGC_CTRL_MASK_ERROR 0x00000040
+
+#define RNGC_CTRL_MASK_DONE 0x00000020
+#define RNGC_CTRL_AUTO_SEED 0x00000010
+#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003
+#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0
+
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1
+#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2
+#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3
+
+#define RNGC_STATUS_ST_PF_MASK 0x00c00000
+#define RNGC_STATUS_ST_PF_SHIFT 22
+#define RNGC_STATUS_ST_PF_TRNG 0x00800000
+#define RNGC_STATUS_ST_PF_PRNG 0x00400000
+#define RNGC_STATUS_ERROR 0x00010000
+#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000
+#define RNGC_STATUS_FIFO_SIZE_SHIFT 12
+#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
+#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040
+#define RNGC_STATUS_SEED_DONE 0x00000020
+#define RNGC_STATUS_ST_DONE 0x00000010
+#define RNGC_STATUS_RESEED 0x00000008
+#define RNGC_STATUS_SLEEP 0x00000004
+#define RNGC_STATUS_BUSY 0x00000002
+#define RNGC_STATUS_SEC_STATE 0x00000001
+
+#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0
+#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040
+#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020
+#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010
+#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
+#define RNGC_ERROR_STATUS_ST_ERR 0x00000004
+#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002
+#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001
+
+#define RNG_ADDR_RANGE 0x34
+
+struct mxc_rngc {
+ struct device *dev;
+ struct clk *clk;
+ void __iomem *base;
+ struct hwrng rng;
+ struct completion rng_self_testing;
+ struct completion rng_seed_done;
+};
+
+static int mxc_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
+{
+ struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
+ unsigned int status;
+ unsigned int level;
+ int retval = 0;
+
+ while (max > sizeof(u32)) {
+ status = __raw_readl(rngc->base + RNGC_STATUS);
+ /* how many random numbers are in FIFO? [0-16] */
+ level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+ RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+ /* is there some error while reading this random number? */
+ if (status & RNGC_STATUS_ERROR)
+ break;
+
+ if (level) {
+ /* retrieve a random number from FIFO */
+ *(u32 *)data = __raw_readl(rngc->base + RNGC_FIFO);
+
+ retval += sizeof(u32);
+ data += sizeof(u32);
+ max -= sizeof(u32);
+ }
+ }
+
+ return retval ? retval : -EIO;
+}
+
+static irqreturn_t rngc_irq(int irq, void *priv)
+{
+ struct mxc_rngc *rngc = (struct mxc_rngc *)priv;
+ int handled = IRQ_NONE;
+
+ /* is the seed creation done? */
+ if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) {
+ complete(&rngc->rng_seed_done);
+ __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+ rngc->base + RNGC_COMMAND);
+ handled = IRQ_HANDLED;
+ }
+
+ /* is the self test done? */
+ if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) {
+ complete(&rngc->rng_self_testing);
+ __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+ rngc->base + RNGC_COMMAND);
+ handled = IRQ_HANDLED;
+ }
+
+ /* is there any error? */
+ if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ERROR) {
+ /* clear interrupt */
+ __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+ rngc->base + RNGC_COMMAND);
+ handled = IRQ_HANDLED;
+ }
+
+ return handled;
+}
+
+static int mxc_rngc_init(struct hwrng *rng)
+{
+ struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
+ u32 cmd;
+ u32 ctrl;
+ u32 osc;
+ int err;
+
+ err = __raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ERROR;
+ if (err) {
+ /* is this a bad keys error ? */
+ if (__raw_readl(rngc->base + RNGC_ERROR) &
+ RNGC_ERROR_STATUS_BAD_KEY) {
+ dev_err(rngc->dev, "Can't start, Bad Keys.\n");
+ return -EIO;
+ }
+ }
+
+ /* mask all interrupts, will be unmasked soon */
+ ctrl = __raw_readl(rngc->base + RNGC_CONTROL);
+ __raw_writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR,
+ rngc->base + RNGC_CONTROL);
+
+ /* verify if oscillator is working */
+ osc = __raw_readl(rngc->base + RNGC_ERROR);
+ if (osc & RNGC_ERROR_STATUS_OSC_ERR) {
+ dev_err(rngc->dev, "RNGC Oscillator is dead!\n");
+ return -EIO;
+ }
+
+ /* do self test, repeat until get success */
+ do {
+ /* clear error */
+ cmd = __raw_readl(rngc->base + RNGC_COMMAND);
+ __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+ /* unmask all interrupt */
+ ctrl = __raw_readl(rngc->base + RNGC_CONTROL);
+ __raw_writel(ctrl & ~(RNGC_CTRL_MASK_DONE |
+ RNGC_CTRL_MASK_ERROR),
+ rngc->base + RNGC_CONTROL);
+
+ /* run self test */
+ cmd = __raw_readl(rngc->base + RNGC_COMMAND);
+ __raw_writel(cmd | RNGC_CMD_SELF_TEST,
+ rngc->base + RNGC_COMMAND);
+
+ wait_for_completion(&rngc->rng_self_testing);
+
+ } while (__raw_readl(rngc->base + RNGC_ERROR) &
+ RNGC_ERROR_STATUS_ST_ERR);
+
+ /* clear interrupt. Is it really necessary here? */
+ __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
+ rngc->base + RNGC_COMMAND);
+
+ /* create seed, repeat while there is some statistical error */
+ do {
+ /* clear error */
+ cmd = __raw_readl(rngc->base + RNGC_COMMAND);
+ __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+ /* seed creation */
+ cmd = __raw_readl(rngc->base + RNGC_COMMAND);
+ __raw_writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+ wait_for_completion(&rngc->rng_seed_done);
+
+ } while (__raw_readl(rngc->base + RNGC_ERROR) &
+ RNGC_ERROR_STATUS_STAT_ERR);
+
+ err = __raw_readl(rngc->base + RNGC_ERROR) &
+ (RNGC_ERROR_STATUS_STAT_ERR |
+ RNGC_ERROR_STATUS_RAND_ERR |
+ RNGC_ERROR_STATUS_FIFO_ERR |
+ RNGC_ERROR_STATUS_ST_ERR |
+ RNGC_ERROR_STATUS_OSC_ERR |
+ RNGC_ERROR_STATUS_LFSR_ERR);
+
+ if (err) {
+ dev_err(rngc->dev, "FSL RNGC appears inoperable.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int mxc_rngc_probe(struct platform_device *pdev)
+{
+ struct mxc_rngc *rngc;
+ struct resource *res;
+ int ret;
+ int irq;
+
+ rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
+ if (!rngc)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ rngc->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(rngc->base))
+ return PTR_ERR(rngc->base);
+
+ rngc->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(rngc->clk)) {
+ dev_err(&pdev->dev, "Can not get rng_clk\n");
+ return PTR_ERR(rngc->clk);
+ }
+
+ ret = clk_prepare_enable(rngc->clk);
+ if (ret)
+ return ret;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
+ clk_disable_unprepare(rngc->clk);
+
+ return irq;
+ }
+ ret = devm_request_irq(rngc->dev, irq, rngc_irq, 0, pdev->name,
+ (void *)rngc);
+ if (ret) {
+ dev_err(rngc->dev, "Can't get interrupt working.\n");
+ return -EIO;
+ }
+
+ init_completion(&rngc->rng_self_testing);
+ init_completion(&rngc->rng_seed_done);
+
+ rngc->rng.name = pdev->name;
+ rngc->rng.init = mxc_rngc_init;
+ rngc->rng.read = mxc_rngc_read;
+
+ rngc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, rngc);
+
+ ret = hwrng_register(&rngc->rng);
+ if (ret) {
+ dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
+ clk_disable_unprepare(rngc->clk);
+
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "Freescale RNGC Registered.\n");
+
+ return 0;
+}
+
+static int mxc_rngc_remove(struct platform_device *pdev)
+{
+ struct mxc_rngc *rngc = platform_get_drvdata(pdev);
+
+ hwrng_unregister(&rngc->rng);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_rngc_suspend(struct device *dev)
+{
+ struct mxc_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+static int mxc_rngc_resume(struct device *dev)
+{
+ struct mxc_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_prepare_enable(rngc->clk);
+
+ return 0;
+}
+
+static const struct dev_pm_ops mxc_rngc_pm_ops = {
+ .suspend = mxc_rngc_suspend,
+ .resume = mxc_rngc_resume,
+};
+#endif
+
+static const struct of_device_id mxc_rngc_dt_ids[] = {
+ { .compatible = "fsl,imx25-rng", .data = NULL, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxc_rngc_dt_ids);
+
+static struct platform_driver mxc_rngc_driver = {
+ .probe = mxc_rngc_probe,
+ .remove = mxc_rngc_remove,
+ .driver = {
+ .name = "mxc_rngc",
+#ifdef CONFIG_PM
+ .pm = &mxc_rngc_pm_ops,
+#endif
+ .of_match_table = mxc_rngc_dt_ids,
+ },
+};
+
+module_platform_driver(mxc_rngc_driver);
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
+MODULE_LICENSE("GPL");
--
2.7.0
On 11.03.2016 16:06, Steffen Trumtrar wrote:
> The driver is ported from Freescales Linux git and can be
> found in the
>
> vendor/freescale/imx_2.6.35_maintain
>
> branch.
>
> According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
> The i.MX2x actually has an RNGB, which has no driver implementation
> in Freescales kernel. However as it turns out, the driver for the RNGC
> works fine on the (at least) i.MX25. So, they seem to be somewhat
> compatible.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> ---
> Changes in v2:
> - remove irq variable from private struct
> - move devm_request_irq from mxc_rngc_init to probe
> - return irq in case of error
> - handle irq 0 as error
>
> drivers/char/hw_random/Kconfig | 13 ++
> drivers/char/hw_random/Makefile | 1 +
> drivers/char/hw_random/mxc-rngc.c | 398 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 412 insertions(+)
> create mode 100644 drivers/char/hw_random/mxc-rngc.c
>
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index dbf22719462f..9d6b5c42255b 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -255,6 +255,19 @@ config HW_RANDOM_MXC_RNGA
>
> If unsure, say Y.
>
> +config HW_RANDOM_MXC_RNGC
> + tristate "Freescale i.MX RNGC Random Number Generator"
> + depends on ARCH_MXC
> + default HW_RANDOM
> + ---help---
> + This driver provides kernel-side support for the Random Number
> + Generator hardware found on some Freescale i.MX processors.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called mxc-rngc.
> +
> + If unsure, say Y.
> +
> config HW_RANDOM_NOMADIK
> tristate "ST-Ericsson Nomadik Random Number Generator support"
> depends on ARCH_NOMADIK
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index 5ad397635128..008463bcf662 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
> obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
> obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
> obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
> +obj-$(CONFIG_HW_RANDOM_MXC_RNGC) += mxc-rngc.o
> obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
> obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
> obj-$(CONFIG_HW_RANDOM_PPC4XX) += ppc4xx-rng.o
> diff --git a/drivers/char/hw_random/mxc-rngc.c b/drivers/char/hw_random/mxc-rngc.c
> new file mode 100644
> index 000000000000..3a2a9b2ad7db
> --- /dev/null
> +++ b/drivers/char/hw_random/mxc-rngc.c
> @@ -0,0 +1,398 @@
> +/*
> + * RNG driver for Freescale RNGC
> + *
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/*
> + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
> + * (c) Copyright 2003 Red Hat Inc <[email protected]>
> + *
> + * derived from
> + *
> + * Hardware driver for the AMD 768 Random Number Generator (RNG)
> + * (c) Copyright 2001 Red Hat Inc <[email protected]>
> + *
> + * derived from
> + *
> + * Hardware driver for Intel i810 Random Number Generator (RNG)
> + * Copyright 2000,2001 Jeff Garzik <[email protected]>
> + * Copyright 2000,2001 Philipp Rumpf <[email protected]>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/hw_random.h>
> +#include <linux/completion.h>
> +#include <linux/io.h>
> +
> +#define RNGC_VERSION_MAJOR3 3
> +
> +#define RNGC_VERSION_ID 0x0000
> +#define RNGC_COMMAND 0x0004
> +#define RNGC_CONTROL 0x0008
> +#define RNGC_STATUS 0x000C
> +#define RNGC_ERROR 0x0010
> +#define RNGC_FIFO 0x0014
> +#define RNGC_VERIF_CTRL 0x0020
> +#define RNGC_OSC_CTRL_COUNT 0x0028
> +#define RNGC_OSC_COUNT 0x002C
> +#define RNGC_OSC_COUNT_STATUS 0x0030
> +
> +#define RNGC_VERID_ZEROS_MASK 0x0f000000
> +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000
> +#define RNGC_VERID_RNG_TYPE_SHIFT 28
> +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000
> +#define RNGC_VERID_CHIP_VERSION_SHIFT 16
> +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00
> +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
> +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff
> +#define RNGC_VERID_VERSION_MINOR_SHIFT 0
All RNGC_VERID_* are not used. And actually quite many other
defined values are not used, e.g. all *_ZEROS_MASK etc.
> +
> +#define RNGC_CMD_ZEROS_MASK 0xffffff8c
> +#define RNGC_CMD_SW_RST 0x00000040
> +#define RNGC_CMD_CLR_ERR 0x00000020
> +#define RNGC_CMD_CLR_INT 0x00000010
> +#define RNGC_CMD_SEED 0x00000002
> +#define RNGC_CMD_SELF_TEST 0x00000001
> +
> +#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c
> +#define RNGC_CTRL_CTL_ACC 0x00000200
> +#define RNGC_CTRL_VERIF_MODE 0x00000100
> +#define RNGC_CTRL_MASK_ERROR 0x00000040
> +
> +#define RNGC_CTRL_MASK_DONE 0x00000020
> +#define RNGC_CTRL_AUTO_SEED 0x00000010
> +#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003
> +#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0
> +
> +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0
> +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1
> +#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2
> +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3
> +
> +#define RNGC_STATUS_ST_PF_MASK 0x00c00000
> +#define RNGC_STATUS_ST_PF_SHIFT 22
> +#define RNGC_STATUS_ST_PF_TRNG 0x00800000
> +#define RNGC_STATUS_ST_PF_PRNG 0x00400000
> +#define RNGC_STATUS_ERROR 0x00010000
> +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000
> +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12
> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
> +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040
> +#define RNGC_STATUS_SEED_DONE 0x00000020
> +#define RNGC_STATUS_ST_DONE 0x00000010
> +#define RNGC_STATUS_RESEED 0x00000008
> +#define RNGC_STATUS_SLEEP 0x00000004
> +#define RNGC_STATUS_BUSY 0x00000002
> +#define RNGC_STATUS_SEC_STATE 0x00000001
> +
> +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0
> +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040
> +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020
> +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010
> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
> +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004
> +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002
> +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001
> +
> +#define RNG_ADDR_RANGE 0x34
> +
> +struct mxc_rngc {
> + struct device *dev;
> + struct clk *clk;
> + void __iomem *base;
> + struct hwrng rng;
> + struct completion rng_self_testing;
> + struct completion rng_seed_done;
> +};
> +
> +static int mxc_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
> +{
> + struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
> + unsigned int status;
> + unsigned int level;
> + int retval = 0;
> +
> + while (max > sizeof(u32)) {
> + status = __raw_readl(rngc->base + RNGC_STATUS);
> + /* how many random numbers are in FIFO? [0-16] */
> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
> +
> + /* is there some error while reading this random number? */
> + if (status & RNGC_STATUS_ERROR)
> + break;
> +
> + if (level) {
> + /* retrieve a random number from FIFO */
> + *(u32 *)data = __raw_readl(rngc->base + RNGC_FIFO);
> +
> + retval += sizeof(u32);
> + data += sizeof(u32);
> + max -= sizeof(u32);
> + }
> + }
> +
> + return retval ? retval : -EIO;
> +}
> +
> +static irqreturn_t rngc_irq(int irq, void *priv)
> +{
> + struct mxc_rngc *rngc = (struct mxc_rngc *)priv;
> + int handled = IRQ_NONE;
> +
> + /* is the seed creation done? */
> + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) {
> + complete(&rngc->rng_seed_done);
> + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> + rngc->base + RNGC_COMMAND);
> + handled = IRQ_HANDLED;
> + }
> +
> + /* is the self test done? */
> + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) {
> + complete(&rngc->rng_self_testing);
> + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> + rngc->base + RNGC_COMMAND);
> + handled = IRQ_HANDLED;
> + }
> +
> + /* is there any error? */
> + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ERROR) {
> + /* clear interrupt */
> + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> + rngc->base + RNGC_COMMAND);
> + handled = IRQ_HANDLED;
For the code errors seem to be harmless, is it so? Does it make
sense to inform a user about errors?
> + }
> +
> + return handled;
> +}
> +
> +static int mxc_rngc_init(struct hwrng *rng)
> +{
> + struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
> + u32 cmd;
> + u32 ctrl;
> + u32 osc;
> + int err;
> +
> + err = __raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ERROR;
> + if (err) {
> + /* is this a bad keys error ? */
> + if (__raw_readl(rngc->base + RNGC_ERROR) &
> + RNGC_ERROR_STATUS_BAD_KEY) {
> + dev_err(rngc->dev, "Can't start, Bad Keys.\n");
> + return -EIO;
> + }
> + }
> +
> + /* mask all interrupts, will be unmasked soon */
> + ctrl = __raw_readl(rngc->base + RNGC_CONTROL);
> + __raw_writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR,
> + rngc->base + RNGC_CONTROL);
> +
> + /* verify if oscillator is working */
> + osc = __raw_readl(rngc->base + RNGC_ERROR);
> + if (osc & RNGC_ERROR_STATUS_OSC_ERR) {
> + dev_err(rngc->dev, "RNGC Oscillator is dead!\n");
> + return -EIO;
> + }
> +
> + /* do self test, repeat until get success */
> + do {
> + /* clear error */
> + cmd = __raw_readl(rngc->base + RNGC_COMMAND);
> + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
> +
> + /* unmask all interrupt */
> + ctrl = __raw_readl(rngc->base + RNGC_CONTROL);
> + __raw_writel(ctrl & ~(RNGC_CTRL_MASK_DONE |
> + RNGC_CTRL_MASK_ERROR),
> + rngc->base + RNGC_CONTROL);
> +
> + /* run self test */
> + cmd = __raw_readl(rngc->base + RNGC_COMMAND);
> + __raw_writel(cmd | RNGC_CMD_SELF_TEST,
> + rngc->base + RNGC_COMMAND);
> +
> + wait_for_completion(&rngc->rng_self_testing);
I would suggest to use wait_for_completion_timeout().
> +
> + } while (__raw_readl(rngc->base + RNGC_ERROR) &
> + RNGC_ERROR_STATUS_ST_ERR);
Logic of running a self test until error condition is gone looks strange.
> +
> + /* clear interrupt. Is it really necessary here? */
> + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> + rngc->base + RNGC_COMMAND);
Answering the question above I believe it is not needed here.
> + /* create seed, repeat while there is some statistical error */
> + do {
> + /* clear error */
> + cmd = __raw_readl(rngc->base + RNGC_COMMAND);
> + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
> +
> + /* seed creation */
> + cmd = __raw_readl(rngc->base + RNGC_COMMAND);
> + __raw_writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
> +
> + wait_for_completion(&rngc->rng_seed_done);
I would suggest to use wait_for_completion_timeout().
> +
> + } while (__raw_readl(rngc->base + RNGC_ERROR) &
> + RNGC_ERROR_STATUS_STAT_ERR);
Any chance to loop forever?
> +
> + err = __raw_readl(rngc->base + RNGC_ERROR) &
> + (RNGC_ERROR_STATUS_STAT_ERR |
> + RNGC_ERROR_STATUS_RAND_ERR |
> + RNGC_ERROR_STATUS_FIFO_ERR |
> + RNGC_ERROR_STATUS_ST_ERR |
> + RNGC_ERROR_STATUS_OSC_ERR |
> + RNGC_ERROR_STATUS_LFSR_ERR);
> +
> + if (err) {
> + dev_err(rngc->dev, "FSL RNGC appears inoperable.\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int mxc_rngc_probe(struct platform_device *pdev)
> +{
> + struct mxc_rngc *rngc;
> + struct resource *res;
> + int ret;
> + int irq;
> +
> + rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
> + if (!rngc)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + rngc->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(rngc->base))
> + return PTR_ERR(rngc->base);
> +
> + rngc->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(rngc->clk)) {
> + dev_err(&pdev->dev, "Can not get rng_clk\n");
> + return PTR_ERR(rngc->clk);
> + }
> +
> + ret = clk_prepare_enable(rngc->clk);
> + if (ret)
> + return ret;
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq <= 0) {
> + dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
> + clk_disable_unprepare(rngc->clk);
> +
> + return irq;
> + }
> + ret = devm_request_irq(rngc->dev, irq, rngc_irq, 0, pdev->name,
> + (void *)rngc);
> + if (ret) {
> + dev_err(rngc->dev, "Can't get interrupt working.\n");
> + return -EIO;
Leaked enabled rngc->clk clock on error path.
> + }
> +
> + init_completion(&rngc->rng_self_testing);
> + init_completion(&rngc->rng_seed_done);
> +
> + rngc->rng.name = pdev->name;
> + rngc->rng.init = mxc_rngc_init;
> + rngc->rng.read = mxc_rngc_read;
> +
> + rngc->dev = &pdev->dev;
> + platform_set_drvdata(pdev, rngc);
> +
> + ret = hwrng_register(&rngc->rng);
> + if (ret) {
> + dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
> + clk_disable_unprepare(rngc->clk);
> +
> + return ret;
> + }
> +
> + dev_info(&pdev->dev, "Freescale RNGC Registered.\n");
> +
> + return 0;
> +}
> +
> +static int mxc_rngc_remove(struct platform_device *pdev)
> +{
> + struct mxc_rngc *rngc = platform_get_drvdata(pdev);
> +
> + hwrng_unregister(&rngc->rng);
> +
> + clk_disable_unprepare(rngc->clk);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int mxc_rngc_suspend(struct device *dev)
> +{
> + struct mxc_rngc *rngc = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(rngc->clk);
> +
> + return 0;
> +}
> +
> +static int mxc_rngc_resume(struct device *dev)
> +{
> + struct mxc_rngc *rngc = dev_get_drvdata(dev);
> +
> + clk_prepare_enable(rngc->clk);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops mxc_rngc_pm_ops = {
> + .suspend = mxc_rngc_suspend,
> + .resume = mxc_rngc_resume,
> +};
> +#endif
> +
> +static const struct of_device_id mxc_rngc_dt_ids[] = {
> + { .compatible = "fsl,imx25-rng", .data = NULL, },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mxc_rngc_dt_ids);
> +
> +static struct platform_driver mxc_rngc_driver = {
> + .probe = mxc_rngc_probe,
> + .remove = mxc_rngc_remove,
> + .driver = {
> + .name = "mxc_rngc",
> +#ifdef CONFIG_PM
> + .pm = &mxc_rngc_pm_ops,
> +#endif
> + .of_match_table = mxc_rngc_dt_ids,
> + },
> +};
> +
> +module_platform_driver(mxc_rngc_driver);
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
> +MODULE_LICENSE("GPL");
>
--
With best wishes,
Vladimir
On Fri, Mar 11, 2016 at 03:06:38PM +0100, Steffen Trumtrar wrote:
> Add binding documentation for the Freescale RNGC found on
> some i.MX2/3/5 SoCs.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> ---
> Documentation/devicetree/bindings/rng/mxc_rngc.txt | 16 ++++++++++++++++
The MXC name is still not dead?
> 1 file changed, 16 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/mxc_rngc.txt
>
> diff --git a/Documentation/devicetree/bindings/rng/mxc_rngc.txt b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
> new file mode 100644
> index 000000000000..e147a6dde40a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
> @@ -0,0 +1,16 @@
> +Freescale RNGC (Random Number Generator Version C)
> +
> +Required properties:
> +- compatible : Should be "fsl,imx25-rng"
What about i.MX3/5 compatible strings?
> +- reg : Offset and length of the register set of this block
> +- interrupts : the interrupt number for the RNG block
> +- clocks: should contain the RNG clk source
> +
> +Example:
> +
> +rng@53fb0000 {
> + compatible = "fsl,imx25-rng";
> + reg = <0x53fb0000 0x4000>;
> + interrupts = <22>;
> + clocks = <&trng_clk>;
> +};
> --
> 2.7.0
>
On Fri, Mar 11, 2016 at 03:06:39PM +0100, Steffen Trumtrar wrote:
> Add a devicetree entry for the Random Number Generator Version C (RNGC).
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> ---
> Changes in v2:
> - remove interrupt-names from dtsi
>
> arch/arm/boot/dts/imx25.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
> index cde329e9b9e3..ebf11d9f123e 100644
> --- a/arch/arm/boot/dts/imx25.dtsi
> +++ b/arch/arm/boot/dts/imx25.dtsi
> @@ -397,6 +397,14 @@
> interrupts = <41>;
> };
>
> + rng: rng@53fb0000 {
> + compatible = "fsl,imx25-rng";
> + reg = <0x53fb0000 0x4000>;
> + clocks = <&clks 109>;
> + clock-names = "ipg";
I think clock-names can be dropped too.
Shawn
> + interrupts = <22>;
> + };
> +
> esdhc1: esdhc@53fb4000 {
> compatible = "fsl,imx25-esdhc";
> reg = <0x53fb4000 0x4000>;
> --
> 2.7.0
>
>
Dear all,
looking for a Freescale RNGB/C driver, I came across this old mail
thread. It seems the review got stuck and the driver was never merged.
This mail is the latest conversation I could find.
I would like to pick up this work and prepare the RNGC driver for
merging into the mailine kernel.
Thus wrote Vladimir Zapolskiy ([email protected]):
> > +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00
> > +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
> > +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff
> > +#define RNGC_VERID_VERSION_MINOR_SHIFT 0
> All RNGC_VERID_* are not used. And actually quite many other
> defined values are not used, e.g. all *_ZEROS_MASK etc.
I removed unused defines.
> > + struct mxc_rngc *rngc = (struct mxc_rngc *)priv;
> > + int handled = IRQ_NONE;
> > +
> > + /* is the seed creation done? */
> > + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) {
> > + complete(&rngc->rng_seed_done);
> > + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> > + rngc->base + RNGC_COMMAND);
> > + handled = IRQ_HANDLED;
> > + }
> > +
> > + /* is the self test done? */
> > + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) {
> > + complete(&rngc->rng_self_testing);
> > + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> > + rngc->base + RNGC_COMMAND);
> > + handled = IRQ_HANDLED;
> > + }
> > +
> > + /* is there any error? */
> > + if (__raw_readl(rngc->base + RNGC_STATUS) & RNGC_STATUS_ERROR) {
> > + /* clear interrupt */
> > + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> > + rngc->base + RNGC_COMMAND);
> > + handled = IRQ_HANDLED;
> For the code errors seem to be harmless, is it so? Does it make
> sense to inform a user about errors?
Either one of the completions is triggered or we time out when we wait
on a wait queue, see below. In any case, we read the error register and
abort the operation if there's an error.
> > + wait_for_completion(&rngc->rng_self_testing);
> I would suggest to use wait_for_completion_timeout().
I fixed this.
> > +
> > + } while (__raw_readl(rngc->base + RNGC_ERROR) &
> > + RNGC_ERROR_STATUS_ST_ERR);
> Logic of running a self test until error condition is gone looks strange.
Agreed. I don't see why the self test should fail in the first run and
complete successfully when we retry without a reset. I changed the code
to run the self test only once.
> > +
> > + /* clear interrupt. Is it really necessary here? */
> > + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
> > + rngc->base + RNGC_COMMAND);
> Answering the question above I believe it is not needed here.
True. The irq handler clears the error status and interrupt bits.
> > + wait_for_completion(&rngc->rng_seed_done);
> I would suggest to use wait_for_completion_timeout().
Done.
> > +
> > + } while (__raw_readl(rngc->base + RNGC_ERROR) &
> > + RNGC_ERROR_STATUS_STAT_ERR);
> Any chance to loop forever?
I exit the loop now for all errors except the "statistical error". This
+ the timeout on the wait queue should prevent us from looping forever.
> > + if (ret) {
> > + dev_err(rngc->dev, "Can't get interrupt working.\n");
> > + return -EIO;
> Leaked enabled rngc->clk clock on error path.
I restructured the probe function such that the clock is disabled when
there's an error after it was enabled.
Best regards,
Martin
Dear all,
I'd like to pick this up and get the rgnc driver merged.
Thus wrote Shawn Guo ([email protected]):
> > + rng: rng@53fb0000 {
> > + compatible = "fsl,imx25-rng";
> > + reg = <0x53fb0000 0x4000>;
> > + clocks = <&clks 109>;
> > + clock-names = "ipg";
> I think clock-names can be dropped too.
done. I'll upload a new version shortly.
Best regards,
Martin
Hi,
I'd like to pick this up and get the rngc driver merged finally.
Thus wrote Rob Herring ([email protected]):
> The MXC name is still not dead?
looks like no. There's still CONFIG_ARCH_MXC etc. The other similar rng
driver is called mxc-rnga.c so it makes sense to use mxc-rngc.
> > 1 file changed, 16 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/rng/mxc_rngc.txt
> > diff --git a/Documentation/devicetree/bindings/rng/mxc_rngc.txt b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
> > new file mode 100644
> > index 000000000000..e147a6dde40a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
> > @@ -0,0 +1,16 @@
> > +Freescale RNGC (Random Number Generator Version C)
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,imx25-rng"
> What about i.MX3/5 compatible strings?
I couldn't find an imx5 chip that has this rng. I added a compatible
string for imx35.
Best regards,
Martin
From: Steffen Trumtrar <[email protected]>
Add binding documentation for the Freescale RNGC found on
some i.MX2/3 SoCs.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
---
Changes in v4:
none
Changes in v3:
- add compatible string for imx35
- remove imx5 from the commit message,
I couldn't find an i.MX SOC that has RNGC
Changes in v2:
none
Documentation/devicetree/bindings/rng/mxc_rngc.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/mxc_rngc.txt
diff --git a/Documentation/devicetree/bindings/rng/mxc_rngc.txt b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
new file mode 100644
index 0000000..5a12ada
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/mxc_rngc.txt
@@ -0,0 +1,16 @@
+Freescale RNGC (Random Number Generator Version C)
+
+Required properties:
+- compatible : Should be "fsl,imx25-rng" or "fsl,imx35-rng"
+- reg : Offset and length of the register set of this block
+- interrupts : the interrupt number for the RNG block
+- clocks: should contain the RNG clk source
+
+Example:
+
+rng@53fb0000 {
+ compatible = "fsl,imx25-rng";
+ reg = <0x53fb0000 0x4000>;
+ interrupts = <22>;
+ clocks = <&trng_clk>;
+};
--
2.1.4
From: Steffen Trumtrar <[email protected]>
Add a devicetree entry for the Random Number Generator Version C (RNGC).
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
---
Changes in v4:
none
Changes in v3:
- remove clock-names from dtsi
Changes in v2:
- remove interrupt-names from dtsi
arch/arm/boot/dts/imx25.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index dfcc8e0..0d2f3a1 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -451,6 +451,13 @@
interrupt-names = "scm", "smn";
};
+ rng: rng@53fb0000 {
+ compatible = "fsl,imx25-rng";
+ reg = <0x53fb0000 0x4000>;
+ clocks = <&clks 109>;
+ interrupts = <22>;
+ };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
--
2.1.4
From: Steffen Trumtrar <[email protected]>
The driver is ported from Freescales Linux git and can be
found in the
vendor/freescale/imx_2.6.35_maintain
branch.
According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
The i.MX2x actually has an RNGB, which has no driver implementation
in Freescales kernel. However as it turns out, the driver for the RNGC
works fine on the (at least) i.MX25. So, they seem to be somewhat
compatible.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
---
Changes in v4:
- use readl, writel instead of the __raw versions
- move the self test to a separate function
- remove the error checks before the self test,
it'll fail when there are errors
- run the self test in the probe function, add a parameter to skip it
- read the error status register before we clear irq and error
- rewrite the irq handler to read and store error status
- helper functions for irq mask, unmask
- remove some more unused defines
- fix a bounds check in the read function
- read function: check status before the fifo level
- clean up the file header, add myself to the copyright notice
Changes in v3:
- use pdev->dev to request the irq, rngc->dev is not yet initialized
- remove unused defines for registers and fields
- use module_platform_driver_probe()
- clean up the error handling in the probe function,
disable the clock if necessary
- self-test must succeed in the first run
- check for errors after seeding, exit for errors unrelated to statistics
- set a timeout when waiting for a completion
Changes in v2:
- remove irq variable from private struct
- move devm_request_irq from mxc_rngc_init to probe
- return irq in case of error
- handle irq 0 as error
drivers/char/hw_random/Kconfig | 13 ++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/mxc-rngc.c | 338 ++++++++++++++++++++++++++++++++++++++
3 files changed, 352 insertions(+)
create mode 100644 drivers/char/hw_random/mxc-rngc.c
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 1b223c3..ef057b7 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -255,6 +255,19 @@ config HW_RANDOM_MXC_RNGA
If unsure, say Y.
+config HW_RANDOM_MXC_RNGC
+ tristate "Freescale i.MX RNGC Random Number Generator"
+ depends on ARCH_MXC
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on some Freescale i.MX processors.
+
+ To compile this driver as a module, choose M here: the
+ module will be called mxc-rngc.
+
+ If unsure, say Y.
+
config HW_RANDOM_NOMADIK
tristate "ST-Ericsson Nomadik Random Number Generator support"
depends on ARCH_NOMADIK
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index b085975..043b71d 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
+obj-$(CONFIG_HW_RANDOM_MXC_RNGC) += mxc-rngc.o
obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
diff --git a/drivers/char/hw_random/mxc-rngc.c b/drivers/char/hw_random/mxc-rngc.c
new file mode 100644
index 0000000..5733a8e
--- /dev/null
+++ b/drivers/char/hw_random/mxc-rngc.c
@@ -0,0 +1,338 @@
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 Martin Kaiser <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/hw_random.h>
+#include <linux/completion.h>
+#include <linux/io.h>
+
+#define RNGC_COMMAND 0x0004
+#define RNGC_CONTROL 0x0008
+#define RNGC_STATUS 0x000C
+#define RNGC_ERROR 0x0010
+#define RNGC_FIFO 0x0014
+
+#define RNGC_CMD_CLR_ERR 0x00000020
+#define RNGC_CMD_CLR_INT 0x00000010
+#define RNGC_CMD_SEED 0x00000002
+#define RNGC_CMD_SELF_TEST 0x00000001
+
+#define RNGC_CTRL_MASK_ERROR 0x00000040
+#define RNGC_CTRL_MASK_DONE 0x00000020
+
+#define RNGC_STATUS_ERROR 0x00010000
+#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
+#define RNGC_STATUS_SEED_DONE 0x00000020
+#define RNGC_STATUS_ST_DONE 0x00000010
+
+#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
+
+#define RNGC_TIMEOUT 3000 /* 3 sec */
+
+
+static bool self_test = true;
+module_param(self_test, bool, 0);
+
+struct mxc_rngc {
+ struct device *dev;
+ struct clk *clk;
+ void __iomem *base;
+ struct hwrng rng;
+ struct completion rng_self_testing;
+ struct completion rng_seed_done;
+ /*
+ * err_reg is written only by the irq handler and read only
+ * when interrupts are masked, we need no spinlock
+ */
+ u32 err_reg;
+};
+
+
+static inline void mxc_rngc_irq_mask_clear(struct mxc_rngc *rngc)
+{
+ u32 ctrl, cmd;
+
+ /* mask interrupts */
+ ctrl = readl(rngc->base + RNGC_CONTROL);
+ ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
+ writel(ctrl, rngc->base + RNGC_CONTROL);
+
+ /*
+ * CLR_INT clears the interrupt only if there's no error
+ * CLR_ERR clear the interrupt and the error register if there
+ * is an error
+ */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
+ writel(cmd, rngc->base + RNGC_COMMAND);
+}
+
+static inline void mxc_rngc_irq_unmask(struct mxc_rngc *rngc)
+{
+ u32 ctrl;
+
+ ctrl = readl(rngc->base + RNGC_CONTROL);
+ ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
+ writel(ctrl, rngc->base + RNGC_CONTROL);
+}
+
+static int mxc_rngc_self_test(struct mxc_rngc *rngc)
+{
+ u32 cmd;
+ int ret;
+
+ mxc_rngc_irq_unmask(rngc);
+
+ /* run self test */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
+
+ ret = wait_for_completion_timeout(&rngc->rng_self_testing,
+ RNGC_TIMEOUT);
+
+ if (!ret) {
+ mxc_rngc_irq_mask_clear(rngc);
+ return -ETIMEDOUT;
+ }
+
+ if (rngc->err_reg != 0)
+ return -EIO;
+
+ return 0;
+}
+
+static int mxc_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
+{
+ struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
+ unsigned int status;
+ unsigned int level;
+ int retval = 0;
+
+ while (max >= sizeof(u32)) {
+ status = readl(rngc->base + RNGC_STATUS);
+
+ /* is there some error while reading this random number? */
+ if (status & RNGC_STATUS_ERROR)
+ break;
+
+ /* how many random numbers are in FIFO? [0-16] */
+ level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+ RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+ if (level) {
+ /* retrieve a random number from FIFO */
+ *(u32 *)data = readl(rngc->base + RNGC_FIFO);
+
+ retval += sizeof(u32);
+ data += sizeof(u32);
+ max -= sizeof(u32);
+ }
+ }
+
+ return retval ? retval : -EIO;
+}
+
+static irqreturn_t mxc_rngc_irq(int irq, void *priv)
+{
+ struct mxc_rngc *rngc = (struct mxc_rngc *)priv;
+ u32 status;
+
+ /*
+ * clearing the interrupt will also clear the error register
+ * read error and status before clearing
+ */
+ status = readl(rngc->base + RNGC_STATUS);
+ rngc->err_reg = readl(rngc->base + RNGC_ERROR);
+
+ mxc_rngc_irq_mask_clear(rngc);
+
+ if (status & RNGC_STATUS_SEED_DONE)
+ complete(&rngc->rng_seed_done);
+
+ if (status & RNGC_STATUS_ST_DONE)
+ complete(&rngc->rng_self_testing);
+
+ return IRQ_HANDLED;
+}
+
+static int mxc_rngc_init(struct hwrng *rng)
+{
+ struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
+ u32 cmd;
+ int ret;
+
+ /* clear error */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+ /* create seed, repeat while there is some statistical error */
+ do {
+ mxc_rngc_irq_unmask(rngc);
+
+ /* seed creation */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+ ret = wait_for_completion_timeout(&rngc->rng_seed_done,
+ RNGC_TIMEOUT);
+
+ if (!ret) {
+ mxc_rngc_irq_mask_clear(rngc);
+ return -ETIMEDOUT;
+ }
+
+ } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
+
+ return rngc->err_reg ? -EIO : 0;
+}
+
+static int mxc_rngc_probe(struct platform_device *pdev)
+{
+ struct mxc_rngc *rngc;
+ struct resource *res;
+ int ret;
+ int irq;
+
+ rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
+ if (!rngc)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ rngc->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(rngc->base))
+ return PTR_ERR(rngc->base);
+
+ rngc->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(rngc->clk)) {
+ dev_err(&pdev->dev, "Can not get rng_clk\n");
+ return PTR_ERR(rngc->clk);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
+ return irq;
+ }
+
+ ret = clk_prepare_enable(rngc->clk);
+ if (ret)
+ return ret;
+
+ ret = devm_request_irq(&pdev->dev,
+ irq, mxc_rngc_irq, 0, pdev->name, (void *)rngc);
+ if (ret) {
+ dev_err(rngc->dev, "Can't get interrupt working.\n");
+ goto err;
+ }
+
+ init_completion(&rngc->rng_self_testing);
+ init_completion(&rngc->rng_seed_done);
+
+ rngc->rng.name = pdev->name;
+ rngc->rng.init = mxc_rngc_init;
+ rngc->rng.read = mxc_rngc_read;
+
+ rngc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, rngc);
+
+ mxc_rngc_irq_mask_clear(rngc);
+
+ if (self_test) {
+ ret = mxc_rngc_self_test(rngc);
+ if (ret) {
+ dev_err(rngc->dev, "FSL RNGC self test failed.\n");
+ goto err;
+ }
+ }
+
+ ret = hwrng_register(&rngc->rng);
+ if (ret) {
+ dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
+ goto err;
+ }
+
+ dev_info(&pdev->dev, "Freescale RNGC registered.\n");
+ return 0;
+
+err:
+ clk_disable_unprepare(rngc->clk);
+
+ return ret;
+}
+
+static int __exit mxc_rngc_remove(struct platform_device *pdev)
+{
+ struct mxc_rngc *rngc = platform_get_drvdata(pdev);
+
+ hwrng_unregister(&rngc->rng);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int mxc_rngc_suspend(struct device *dev)
+{
+ struct mxc_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+static int mxc_rngc_resume(struct device *dev)
+{
+ struct mxc_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_prepare_enable(rngc->clk);
+
+ return 0;
+}
+
+static const struct dev_pm_ops mxc_rngc_pm_ops = {
+ .suspend = mxc_rngc_suspend,
+ .resume = mxc_rngc_resume,
+};
+#endif
+
+static const struct of_device_id mxc_rngc_dt_ids[] = {
+ { .compatible = "fsl,imx25-rng", .data = NULL, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxc_rngc_dt_ids);
+
+static struct platform_driver mxc_rngc_driver = {
+ .driver = {
+ .name = "mxc_rngc",
+#ifdef CONFIG_PM
+ .pm = &mxc_rngc_pm_ops,
+#endif
+ .of_match_table = mxc_rngc_dt_ids,
+ },
+ .remove = __exit_p(mxc_rngc_remove),
+};
+
+module_platform_driver_probe(mxc_rngc_driver, mxc_rngc_probe);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
+MODULE_LICENSE("GPL");
--
2.1.4
Hi Martin,
Nice to see a quick turnaround. Have a minor suggestion below.
On 20 July 2017 at 15:57, Martin Kaiser <martin-XxZfDwE/[email protected]> wrote:
> From: Steffen Trumtrar <[email protected]>
>
> The driver is ported from Freescales Linux git and can be
> found in the
>
> vendor/freescale/imx_2.6.35_maintain
>
> branch.
>
> According to that code, the RNGC is found on Freescales i.MX3/5 SoCs.
> The i.MX2x actually has an RNGB, which has no driver implementation
> in Freescales kernel. However as it turns out, the driver for the RNGC
> works fine on the (at least) i.MX25. So, they seem to be somewhat
> compatible.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> Signed-off-by: Martin Kaiser <martin-XxZfDwE/[email protected]>
> ---
> Changes in v4:
> - use readl, writel instead of the __raw versions
> - move the self test to a separate function
> - remove the error checks before the self test,
> it'll fail when there are errors
> - run the self test in the probe function, add a parameter to skip it
> - read the error status register before we clear irq and error
> - rewrite the irq handler to read and store error status
> - helper functions for irq mask, unmask
> - remove some more unused defines
> - fix a bounds check in the read function
> - read function: check status before the fifo level
> - clean up the file header, add myself to the copyright notice
>
> Changes in v3:
> - use pdev->dev to request the irq, rngc->dev is not yet initialized
> - remove unused defines for registers and fields
> - use module_platform_driver_probe()
> - clean up the error handling in the probe function,
> disable the clock if necessary
> - self-test must succeed in the first run
> - check for errors after seeding, exit for errors unrelated to statistics
> - set a timeout when waiting for a completion
>
> Changes in v2:
> - remove irq variable from private struct
> - move devm_request_irq from mxc_rngc_init to probe
> - return irq in case of error
> - handle irq 0 as error
>
> drivers/char/hw_random/Kconfig | 13 ++
> drivers/char/hw_random/Makefile | 1 +
> drivers/char/hw_random/mxc-rngc.c | 338 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 352 insertions(+)
> create mode 100644 drivers/char/hw_random/mxc-rngc.c
>
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 1b223c3..ef057b7 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -255,6 +255,19 @@ config HW_RANDOM_MXC_RNGA
>
> If unsure, say Y.
>
> +config HW_RANDOM_MXC_RNGC
> + tristate "Freescale i.MX RNGC Random Number Generator"
> + depends on ARCH_MXC
> + default HW_RANDOM
> + ---help---
> + This driver provides kernel-side support for the Random Number
> + Generator hardware found on some Freescale i.MX processors.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called mxc-rngc.
> +
> + If unsure, say Y.
> +
> config HW_RANDOM_NOMADIK
> tristate "ST-Ericsson Nomadik Random Number Generator support"
> depends on ARCH_NOMADIK
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index b085975..043b71d 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
> obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
> obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
> obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
> +obj-$(CONFIG_HW_RANDOM_MXC_RNGC) += mxc-rngc.o
> obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
> obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
> obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
> diff --git a/drivers/char/hw_random/mxc-rngc.c b/drivers/char/hw_random/mxc-rngc.c
> new file mode 100644
> index 0000000..5733a8e
> --- /dev/null
> +++ b/drivers/char/hw_random/mxc-rngc.c
> @@ -0,0 +1,338 @@
> +/*
> + * RNG driver for Freescale RNGC
> + *
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2017 Martin Kaiser <martin-XxZfDwE/[email protected]>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/hw_random.h>
> +#include <linux/completion.h>
> +#include <linux/io.h>
> +
> +#define RNGC_COMMAND 0x0004
> +#define RNGC_CONTROL 0x0008
> +#define RNGC_STATUS 0x000C
> +#define RNGC_ERROR 0x0010
> +#define RNGC_FIFO 0x0014
> +
> +#define RNGC_CMD_CLR_ERR 0x00000020
> +#define RNGC_CMD_CLR_INT 0x00000010
> +#define RNGC_CMD_SEED 0x00000002
> +#define RNGC_CMD_SELF_TEST 0x00000001
> +
> +#define RNGC_CTRL_MASK_ERROR 0x00000040
> +#define RNGC_CTRL_MASK_DONE 0x00000020
> +
> +#define RNGC_STATUS_ERROR 0x00010000
> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
> +#define RNGC_STATUS_SEED_DONE 0x00000020
> +#define RNGC_STATUS_ST_DONE 0x00000010
> +
> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
> +
> +#define RNGC_TIMEOUT 3000 /* 3 sec */
> +
> +
> +static bool self_test = true;
> +module_param(self_test, bool, 0);
> +
> +struct mxc_rngc {
> + struct device *dev;
> + struct clk *clk;
> + void __iomem *base;
> + struct hwrng rng;
> + struct completion rng_self_testing;
> + struct completion rng_seed_done;
Self test and seeding does not happen at the same time so a single
completion structure should suffice.
> + /*
> + * err_reg is written only by the irq handler and read only
> + * when interrupts are masked, we need no spinlock
> + */
> + u32 err_reg;
> +};
> +
> +
> +static inline void mxc_rngc_irq_mask_clear(struct mxc_rngc *rngc)
> +{
> + u32 ctrl, cmd;
> +
> + /* mask interrupts */
> + ctrl = readl(rngc->base + RNGC_CONTROL);
> + ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
> + writel(ctrl, rngc->base + RNGC_CONTROL);
> +
> + /*
> + * CLR_INT clears the interrupt only if there's no error
> + * CLR_ERR clear the interrupt and the error register if there
> + * is an error
> + */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
> + writel(cmd, rngc->base + RNGC_COMMAND);
> +}
> +
> +static inline void mxc_rngc_irq_unmask(struct mxc_rngc *rngc)
> +{
> + u32 ctrl;
> +
> + ctrl = readl(rngc->base + RNGC_CONTROL);
> + ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
> + writel(ctrl, rngc->base + RNGC_CONTROL);
> +}
> +
> +static int mxc_rngc_self_test(struct mxc_rngc *rngc)
> +{
> + u32 cmd;
> + int ret;
> +
> + mxc_rngc_irq_unmask(rngc);
> +
> + /* run self test */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
> +
> + ret = wait_for_completion_timeout(&rngc->rng_self_testing,
> + RNGC_TIMEOUT);
> +
> + if (!ret) {
> + mxc_rngc_irq_mask_clear(rngc);
> + return -ETIMEDOUT;
> + }
> +
> + if (rngc->err_reg != 0)
> + return -EIO;
> +
> + return 0;
> +}
> +
> +static int mxc_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
> +{
> + struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
> + unsigned int status;
> + unsigned int level;
> + int retval = 0;
> +
> + while (max >= sizeof(u32)) {
> + status = readl(rngc->base + RNGC_STATUS);
> +
> + /* is there some error while reading this random number? */
> + if (status & RNGC_STATUS_ERROR)
> + break;
> +
> + /* how many random numbers are in FIFO? [0-16] */
> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
> +
> + if (level) {
> + /* retrieve a random number from FIFO */
> + *(u32 *)data = readl(rngc->base + RNGC_FIFO);
> +
> + retval += sizeof(u32);
> + data += sizeof(u32);
> + max -= sizeof(u32);
> + }
> + }
> +
> + return retval ? retval : -EIO;
> +}
> +
> +static irqreturn_t mxc_rngc_irq(int irq, void *priv)
> +{
> + struct mxc_rngc *rngc = (struct mxc_rngc *)priv;
> + u32 status;
> +
> + /*
> + * clearing the interrupt will also clear the error register
> + * read error and status before clearing
> + */
> + status = readl(rngc->base + RNGC_STATUS);
> + rngc->err_reg = readl(rngc->base + RNGC_ERROR);
> +
> + mxc_rngc_irq_mask_clear(rngc);
> +
> + if (status & RNGC_STATUS_SEED_DONE)
> + complete(&rngc->rng_seed_done);
> +
> + if (status & RNGC_STATUS_ST_DONE)
> + complete(&rngc->rng_self_testing);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int mxc_rngc_init(struct hwrng *rng)
> +{
> + struct mxc_rngc *rngc = container_of(rng, struct mxc_rngc, rng);
> + u32 cmd;
> + int ret;
> +
> + /* clear error */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
> +
> + /* create seed, repeat while there is some statistical error */
> + do {
> + mxc_rngc_irq_unmask(rngc);
> +
> + /* seed creation */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
> +
> + ret = wait_for_completion_timeout(&rngc->rng_seed_done,
> + RNGC_TIMEOUT);
> +
> + if (!ret) {
> + mxc_rngc_irq_mask_clear(rngc);
> + return -ETIMEDOUT;
> + }
> +
> + } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
> +
> + return rngc->err_reg ? -EIO : 0;
> +}
> +
> +static int mxc_rngc_probe(struct platform_device *pdev)
> +{
> + struct mxc_rngc *rngc;
> + struct resource *res;
> + int ret;
> + int irq;
> +
> + rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
> + if (!rngc)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + rngc->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(rngc->base))
> + return PTR_ERR(rngc->base);
> +
> + rngc->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(rngc->clk)) {
> + dev_err(&pdev->dev, "Can not get rng_clk\n");
> + return PTR_ERR(rngc->clk);
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq <= 0) {
> + dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
> + return irq;
> + }
> +
> + ret = clk_prepare_enable(rngc->clk);
> + if (ret)
> + return ret;
> +
> + ret = devm_request_irq(&pdev->dev,
> + irq, mxc_rngc_irq, 0, pdev->name, (void *)rngc);
> + if (ret) {
> + dev_err(rngc->dev, "Can't get interrupt working.\n");
> + goto err;
> + }
> +
> + init_completion(&rngc->rng_self_testing);
> + init_completion(&rngc->rng_seed_done);
> +
> + rngc->rng.name = pdev->name;
> + rngc->rng.init = mxc_rngc_init;
> + rngc->rng.read = mxc_rngc_read;
> +
> + rngc->dev = &pdev->dev;
> + platform_set_drvdata(pdev, rngc);
> +
> + mxc_rngc_irq_mask_clear(rngc);
> +
> + if (self_test) {
> + ret = mxc_rngc_self_test(rngc);
> + if (ret) {
> + dev_err(rngc->dev, "FSL RNGC self test failed.\n");
> + goto err;
> + }
> + }
> +
> + ret = hwrng_register(&rngc->rng);
> + if (ret) {
> + dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
> + goto err;
> + }
> +
> + dev_info(&pdev->dev, "Freescale RNGC registered.\n");
> + return 0;
> +
> +err:
> + clk_disable_unprepare(rngc->clk);
> +
> + return ret;
> +}
> +
> +static int __exit mxc_rngc_remove(struct platform_device *pdev)
> +{
> + struct mxc_rngc *rngc = platform_get_drvdata(pdev);
> +
> + hwrng_unregister(&rngc->rng);
> +
> + clk_disable_unprepare(rngc->clk);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int mxc_rngc_suspend(struct device *dev)
> +{
> + struct mxc_rngc *rngc = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(rngc->clk);
> +
> + return 0;
> +}
> +
> +static int mxc_rngc_resume(struct device *dev)
> +{
> + struct mxc_rngc *rngc = dev_get_drvdata(dev);
> +
> + clk_prepare_enable(rngc->clk);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops mxc_rngc_pm_ops = {
> + .suspend = mxc_rngc_suspend,
> + .resume = mxc_rngc_resume,
> +};
> +#endif
> +
> +static const struct of_device_id mxc_rngc_dt_ids[] = {
> + { .compatible = "fsl,imx25-rng", .data = NULL, },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mxc_rngc_dt_ids);
> +
> +static struct platform_driver mxc_rngc_driver = {
> + .driver = {
> + .name = "mxc_rngc",
> +#ifdef CONFIG_PM
> + .pm = &mxc_rngc_pm_ops,
> +#endif
> + .of_match_table = mxc_rngc_dt_ids,
> + },
> + .remove = __exit_p(mxc_rngc_remove),
> +};
> +
> +module_platform_driver_probe(mxc_rngc_driver, mxc_rngc_probe);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
> +MODULE_LICENSE("GPL");
> --
> 2.1.4
>
Regardless of the minor suggestion, code looks good to me as is.
Reviewed-by: PrasannaKumar Muralidharan <[email protected]>.
Note: Add my reviewed by tag if you are going for next version.
Regards,
PrasannaKumar
From: Steffen Trumtrar <[email protected]>
Add binding documentation for the Freescale RNGC found on
some i.MX2/3 SoCs.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
---
Changes in v6:
- be more precise about rngc and rngb
- get rid of mxc, rename the file to imx-rngc.txt
- reformat the compatible strings
- use RNGC instead of RNG
- clarify that clock is not optional (remove "should contain")
Changes in v5:
none
Changes in v4:
none
Changes in v3:
- add compatible string for imx35
- remove imx5 from the commit message,
I couldn't find an i.MX SOC that has RNGC
Changes in v2:
none
Documentation/devicetree/bindings/rng/imx-rngc.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/imx-rngc.txt
diff --git a/Documentation/devicetree/bindings/rng/imx-rngc.txt b/Documentation/devicetree/bindings/rng/imx-rngc.txt
new file mode 100644
index 0000000..93c7174
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/imx-rngc.txt
@@ -0,0 +1,21 @@
+Freescale RNGC (Random Number Generator Version C)
+
+The driver also supports version B, which is mostly compatible
+to version C.
+
+Required properties:
+- compatible : should be one of
+ "fsl,imx25-rngb"
+ "fsl,imx35-rngc"
+- reg : offset and length of the register set of this block
+- interrupts : the interrupt number for the RNGC block
+- clocks : the RNGC clk source
+
+Example:
+
+rng@53fb0000 {
+ compatible = "fsl,imx25-rngb";
+ reg = <0x53fb0000 0x4000>;
+ interrupts = <22>;
+ clocks = <&trng_clk>;
+};
--
2.1.4
From: Steffen Trumtrar <[email protected]>
Add a devicetree entry for the Random Number Generator Version B (RNGB).
The driver for RNGC supports version B as well.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
---
Changes in v6:
- use rngb instead of just rng
Changes in v5:
none
Changes in v4:
none
Changes in v3:
- remove clock-names from dtsi
Changes in v2:
- remove interrupt-names from dtsi
arch/arm/boot/dts/imx25.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index dfcc8e0..d8d3163 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -451,6 +451,13 @@
interrupt-names = "scm", "smn";
};
+ rngb: rngb@53fb0000 {
+ compatible = "fsl,imx25-rngb";
+ reg = <0x53fb0000 0x4000>;
+ clocks = <&clks 109>;
+ interrupts = <22>;
+ };
+
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
--
2.1.4
The driver is ported from Freescale's Linux git and can be
found in the
vendor/freescale/imx_2.6.35_maintain
branch.
The driver supports both RNG version C that's part of some Freescale
i.MX3 SoCs and version B that is available on i.MX2x chipsets.
Signed-off-by: Steffen Trumtrar <[email protected]>
Signed-off-by: Martin Kaiser <[email protected]>
Reviewed-by: PrasannaKumar Muralidharan <[email protected]>
---
Changes in v6:
- get rid of mxc: rename the .c file and the kconfig option
- update the kconfig help text
- rename structs, function names etc. from mxc_rngc to imx_rngc
- rewrite the commit message to not use mxc
- set myself as commit author so people know who to blame
Changes in v5:
- use only one completion for self test and seeding
Changes in v4:
- use readl, writel instead of the __raw versions
- move the self test to a separate function
- remove the error checks before the self test,
it'll fail when there are errors
- run the self test in the probe function, add a parameter to skip it
- read the error status register before we clear irq and error
- rewrite the irq handler to read and store error status
- helper functions for irq mask, unmask
- remove some more unused defines
- fix a bounds check in the read function
- read function: check status before the fifo level
- clean up the file header, add myself to the copyright notice
Changes in v3:
- use pdev->dev to request the irq, rngc->dev is not yet initialized
- remove unused defines for registers and fields
- use module_platform_driver_probe()
- clean up the error handling in the probe function,
disable the clock if necessary
- self-test must succeed in the first run
- check for errors after seeding, exit for errors unrelated to statistics
- set a timeout when waiting for a completion
Changes in v2:
- remove irq variable from private struct
- move devm_request_irq from mxc_rngc_init to probe
- return irq in case of error
- handle irq 0 as error
drivers/char/hw_random/Kconfig | 14 ++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/imx-rngc.c | 331 ++++++++++++++++++++++++++++++++++++++
3 files changed, 346 insertions(+)
create mode 100644 drivers/char/hw_random/imx-rngc.c
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 1b223c3..6530948 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -255,6 +255,20 @@ config HW_RANDOM_MXC_RNGA
If unsure, say Y.
+config HW_RANDOM_IMX_RNGC
+ tristate "Freescale i.MX RNGC Random Number Generator"
+ depends on ARCH_MXC
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator Version C hardware found on some Freescale i.MX
+ processors. Version B is also supported by this driver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called imx-rngc.
+
+ If unsure, say Y.
+
config HW_RANDOM_NOMADIK
tristate "ST-Ericsson Nomadik Random Number Generator support"
depends on ARCH_NOMADIK
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index b085975..39a67de 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
+obj-$(CONFIG_HW_RANDOM_IMX_RNGC) += imx-rngc.o
obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c
new file mode 100644
index 0000000..88db42d
--- /dev/null
+++ b/drivers/char/hw_random/imx-rngc.c
@@ -0,0 +1,331 @@
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 Martin Kaiser <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/hw_random.h>
+#include <linux/completion.h>
+#include <linux/io.h>
+
+#define RNGC_COMMAND 0x0004
+#define RNGC_CONTROL 0x0008
+#define RNGC_STATUS 0x000C
+#define RNGC_ERROR 0x0010
+#define RNGC_FIFO 0x0014
+
+#define RNGC_CMD_CLR_ERR 0x00000020
+#define RNGC_CMD_CLR_INT 0x00000010
+#define RNGC_CMD_SEED 0x00000002
+#define RNGC_CMD_SELF_TEST 0x00000001
+
+#define RNGC_CTRL_MASK_ERROR 0x00000040
+#define RNGC_CTRL_MASK_DONE 0x00000020
+
+#define RNGC_STATUS_ERROR 0x00010000
+#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
+#define RNGC_STATUS_SEED_DONE 0x00000020
+#define RNGC_STATUS_ST_DONE 0x00000010
+
+#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
+
+#define RNGC_TIMEOUT 3000 /* 3 sec */
+
+
+static bool self_test = true;
+module_param(self_test, bool, 0);
+
+struct imx_rngc {
+ struct device *dev;
+ struct clk *clk;
+ void __iomem *base;
+ struct hwrng rng;
+ struct completion rng_op_done;
+ /*
+ * err_reg is written only by the irq handler and read only
+ * when interrupts are masked, we need no spinlock
+ */
+ u32 err_reg;
+};
+
+
+static inline void imx_rngc_irq_mask_clear(struct imx_rngc *rngc)
+{
+ u32 ctrl, cmd;
+
+ /* mask interrupts */
+ ctrl = readl(rngc->base + RNGC_CONTROL);
+ ctrl |= RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR;
+ writel(ctrl, rngc->base + RNGC_CONTROL);
+
+ /*
+ * CLR_INT clears the interrupt only if there's no error
+ * CLR_ERR clear the interrupt and the error register if there
+ * is an error
+ */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ cmd |= RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR;
+ writel(cmd, rngc->base + RNGC_COMMAND);
+}
+
+static inline void imx_rngc_irq_unmask(struct imx_rngc *rngc)
+{
+ u32 ctrl;
+
+ ctrl = readl(rngc->base + RNGC_CONTROL);
+ ctrl &= ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR);
+ writel(ctrl, rngc->base + RNGC_CONTROL);
+}
+
+static int imx_rngc_self_test(struct imx_rngc *rngc)
+{
+ u32 cmd;
+ int ret;
+
+ imx_rngc_irq_unmask(rngc);
+
+ /* run self test */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
+
+ ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT);
+ if (!ret) {
+ imx_rngc_irq_mask_clear(rngc);
+ return -ETIMEDOUT;
+ }
+
+ if (rngc->err_reg != 0)
+ return -EIO;
+
+ return 0;
+}
+
+static int imx_rngc_read(struct hwrng *rng, void *data, size_t max, bool wait)
+{
+ struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
+ unsigned int status;
+ unsigned int level;
+ int retval = 0;
+
+ while (max >= sizeof(u32)) {
+ status = readl(rngc->base + RNGC_STATUS);
+
+ /* is there some error while reading this random number? */
+ if (status & RNGC_STATUS_ERROR)
+ break;
+
+ /* how many random numbers are in FIFO? [0-16] */
+ level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+ RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+ if (level) {
+ /* retrieve a random number from FIFO */
+ *(u32 *)data = readl(rngc->base + RNGC_FIFO);
+
+ retval += sizeof(u32);
+ data += sizeof(u32);
+ max -= sizeof(u32);
+ }
+ }
+
+ return retval ? retval : -EIO;
+}
+
+static irqreturn_t imx_rngc_irq(int irq, void *priv)
+{
+ struct imx_rngc *rngc = (struct imx_rngc *)priv;
+ u32 status;
+
+ /*
+ * clearing the interrupt will also clear the error register
+ * read error and status before clearing
+ */
+ status = readl(rngc->base + RNGC_STATUS);
+ rngc->err_reg = readl(rngc->base + RNGC_ERROR);
+
+ imx_rngc_irq_mask_clear(rngc);
+
+ if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
+ complete(&rngc->rng_op_done);
+
+ return IRQ_HANDLED;
+}
+
+static int imx_rngc_init(struct hwrng *rng)
+{
+ struct imx_rngc *rngc = container_of(rng, struct imx_rngc, rng);
+ u32 cmd;
+ int ret;
+
+ /* clear error */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+ /* create seed, repeat while there is some statistical error */
+ do {
+ imx_rngc_irq_unmask(rngc);
+
+ /* seed creation */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+ ret = wait_for_completion_timeout(&rngc->rng_op_done,
+ RNGC_TIMEOUT);
+
+ if (!ret) {
+ imx_rngc_irq_mask_clear(rngc);
+ return -ETIMEDOUT;
+ }
+
+ } while (rngc->err_reg == RNGC_ERROR_STATUS_STAT_ERR);
+
+ return rngc->err_reg ? -EIO : 0;
+}
+
+static int imx_rngc_probe(struct platform_device *pdev)
+{
+ struct imx_rngc *rngc;
+ struct resource *res;
+ int ret;
+ int irq;
+
+ rngc = devm_kzalloc(&pdev->dev, sizeof(*rngc), GFP_KERNEL);
+ if (!rngc)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ rngc->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(rngc->base))
+ return PTR_ERR(rngc->base);
+
+ rngc->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(rngc->clk)) {
+ dev_err(&pdev->dev, "Can not get rng_clk\n");
+ return PTR_ERR(rngc->clk);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
+ return irq;
+ }
+
+ ret = clk_prepare_enable(rngc->clk);
+ if (ret)
+ return ret;
+
+ ret = devm_request_irq(&pdev->dev,
+ irq, imx_rngc_irq, 0, pdev->name, (void *)rngc);
+ if (ret) {
+ dev_err(rngc->dev, "Can't get interrupt working.\n");
+ goto err;
+ }
+
+ init_completion(&rngc->rng_op_done);
+
+ rngc->rng.name = pdev->name;
+ rngc->rng.init = imx_rngc_init;
+ rngc->rng.read = imx_rngc_read;
+
+ rngc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, rngc);
+
+ imx_rngc_irq_mask_clear(rngc);
+
+ if (self_test) {
+ ret = imx_rngc_self_test(rngc);
+ if (ret) {
+ dev_err(rngc->dev, "FSL RNGC self test failed.\n");
+ goto err;
+ }
+ }
+
+ ret = hwrng_register(&rngc->rng);
+ if (ret) {
+ dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", ret);
+ goto err;
+ }
+
+ dev_info(&pdev->dev, "Freescale RNGC registered.\n");
+ return 0;
+
+err:
+ clk_disable_unprepare(rngc->clk);
+
+ return ret;
+}
+
+static int __exit imx_rngc_remove(struct platform_device *pdev)
+{
+ struct imx_rngc *rngc = platform_get_drvdata(pdev);
+
+ hwrng_unregister(&rngc->rng);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int imx_rngc_suspend(struct device *dev)
+{
+ struct imx_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rngc->clk);
+
+ return 0;
+}
+
+static int imx_rngc_resume(struct device *dev)
+{
+ struct imx_rngc *rngc = dev_get_drvdata(dev);
+
+ clk_prepare_enable(rngc->clk);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx_rngc_pm_ops = {
+ .suspend = imx_rngc_suspend,
+ .resume = imx_rngc_resume,
+};
+#endif
+
+static const struct of_device_id imx_rngc_dt_ids[] = {
+ { .compatible = "fsl,imx25-rngb", .data = NULL, },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
+
+static struct platform_driver imx_rngc_driver = {
+ .driver = {
+ .name = "imx_rngc",
+#ifdef CONFIG_PM
+ .pm = &imx_rngc_pm_ops,
+#endif
+ .of_match_table = imx_rngc_dt_ids,
+ },
+ .remove = __exit_p(imx_rngc_remove),
+};
+
+module_platform_driver_probe(imx_rngc_driver, imx_rngc_probe);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("H/W RNGC driver for i.MX");
+MODULE_LICENSE("GPL");
--
2.1.4
On Sun, Jul 23, 2017 at 12:49 PM, Martin Kaiser <martin-XxZfDwE/[email protected]> wrote:
> From: Steffen Trumtrar <[email protected]>
>
> Add binding documentation for the Freescale RNGC found on
> some i.MX2/3 SoCs.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> Signed-off-by: Martin Kaiser <martin-XxZfDwE/[email protected]>
> ---
> Changes in v6:
> - be more precise about rngc and rngb
> - get rid of mxc, rename the file to imx-rngc.txt
> - reformat the compatible strings
> - use RNGC instead of RNG
> - clarify that clock is not optional (remove "should contain")
>
> Changes in v5:
> none
>
> Changes in v4:
> none
>
> Changes in v3:
> - add compatible string for imx35
> - remove imx5 from the commit message,
> I couldn't find an i.MX SOC that has RNGC
>
> Changes in v2:
> none
>
> Documentation/devicetree/bindings/rng/imx-rngc.txt | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/imx-rngc.txt
Reviewed-by: Rob Herring <[email protected]>
On Sun, Jul 23, 2017 at 07:49:04PM +0200, Martin Kaiser wrote:
> From: Steffen Trumtrar <[email protected]>
>
> Add binding documentation for the Freescale RNGC found on
> some i.MX2/3 SoCs.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> Signed-off-by: Martin Kaiser <martin-XxZfDwE/[email protected]>
Patch applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Sun, Jul 23, 2017 at 07:49:06PM +0200, Martin Kaiser wrote:
> The driver is ported from Freescale's Linux git and can be
> found in the
>
> vendor/freescale/imx_2.6.35_maintain
>
> branch.
>
> The driver supports both RNG version C that's part of some Freescale
> i.MX3 SoCs and version B that is available on i.MX2x chipsets.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> Signed-off-by: Martin Kaiser <[email protected]>
> Reviewed-by: PrasannaKumar Muralidharan <[email protected]>
Patch applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Sun, Jul 23, 2017 at 07:49:05PM +0200, Martin Kaiser wrote:
> From: Steffen Trumtrar <[email protected]>
>
> Add a devicetree entry for the Random Number Generator Version B (RNGB).
> The driver for RNGC supports version B as well.
>
> Signed-off-by: Steffen Trumtrar <[email protected]>
> Signed-off-by: Martin Kaiser <[email protected]>
Applied, thanks.