2020-07-09 08:54:01

by Sven Auhagen

Subject: [PATCH 1/1] marvell cesa irq balance

Balance the irqs of the marvell cesa driver over all
available cpus.
Currently all interrupts are handled by the first CPU.

From my testing with IPSec AES 256 SHA256
on my clearfog base with 2 Cores I get a 2x speed increase:

Before the patch: 26.74 Kpps
With the patch: 56.11 Kpps

Signed-off-by: Sven Auhagen <[email protected]>
---
drivers/crypto/marvell/cesa/cesa.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/marvell/cesa/cesa.c b/drivers/crypto/marvell/cesa/cesa.c
index 8a5f0b0bdf77..bf1bda2e904a 100644
--- a/drivers/crypto/marvell/cesa/cesa.c
+++ b/drivers/crypto/marvell/cesa/cesa.c
@@ -438,7 +438,7 @@ static int mv_cesa_probe(struct platform_device *pdev)
struct mv_cesa_dev *cesa;
struct mv_cesa_engine *engines;
struct resource *res;
- int irq, ret, i;
+ int irq, ret, i, cpu;
u32 sram_size;

if (cesa_dev) {
@@ -548,6 +548,10 @@ static int mv_cesa_probe(struct platform_device *pdev)
if (ret)
goto err_cleanup;

+ // Set affinity
+ cpu = engine->id % num_online_cpus();
+ irq_set_affinity_hint(irq, get_cpu_mask(cpu));
+
crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);
atomic_set(&engine->load, 0);
INIT_LIST_HEAD(&engine->complete_queue);
--
2.20.1

2020-07-16 07:25:56

by Herbert Xu

Subject: Re: [PATCH 1/1] marvell cesa irq balance

Sven Auhagen <[email protected]> wrote:
> Balance the irqs of the marvell cesa driver over all
> available cpus.
> Currently all interrupts are handled by the first CPU.
>
> From my testing with IPSec AES 256 SHA256
> on my clearfog base with 2 Cores I get a 2x speed increase:
>
> Before the patch: 26.74 Kpps
> With the patch: 56.11 Kpps
>
> Signed-off-by: Sven Auhagen <[email protected]>
> ---
> drivers/crypto/marvell/cesa/cesa.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/marvell/cesa/cesa.c b/drivers/crypto/marvell/cesa/cesa.c
> index 8a5f0b0bdf77..bf1bda2e904a 100644
> --- a/drivers/crypto/marvell/cesa/cesa.c
> +++ b/drivers/crypto/marvell/cesa/cesa.c
> @@ -438,7 +438,7 @@ static int mv_cesa_probe(struct platform_device *pdev)
> struct mv_cesa_dev *cesa;
> struct mv_cesa_engine *engines;
> struct resource *res;
> - int irq, ret, i;
> + int irq, ret, i, cpu;
> u32 sram_size;
>
> if (cesa_dev) {
> @@ -548,6 +548,10 @@ static int mv_cesa_probe(struct platform_device *pdev)
> if (ret)
> goto err_cleanup;
>
> + // Set affinity
> + cpu = engine->id % num_online_cpus();
> + irq_set_affinity_hint(irq, get_cpu_mask(cpu));
> +

Same issue as the inside-secure patch.

Cheers,
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt