This patch series is a result of running kernel crypto fuzz tests (by
enabling CONFIG_CRYPTO_MANAGER_EXTRA_TESTS) on the transformations
currently supported via the Qualcomm crypto engine on sdm845. The first
four patches are fixes for various regressions found during testing. The
last two patches are minor clean ups of unused variable and parameters.
v2->v3:
- Made the comparison between keys to check if any two keys are
same for triple des algorithms constant-time as per
Nym Seddon's suggestion.
- Rebased to 5.11-rc4.
v1->v2:
- Introduced custom struct qce_sha_saved_state to store and restore
partial sha transformation.
- Rebased to 5.11-rc3.
Thara Gopinath (6):
drivers: crypto: qce: sha: Restore/save ahash state with custom struct
in export/import
drivers: crypto: qce: sha: Hold back a block of data to be transferred
as part of final
drivers: crypto: qce: skcipher: Fix regressions found during fuzz
testing
drivers: crypto: qce: common: Set data unit size to message length for
AES XTS transformation
drivers: crypto: qce: Remover src_tbl from qce_cipher_reqctx
drivers: crypto: qce: Remove totallen and offset in qce_start
drivers/crypto/qce/cipher.h | 1 -
drivers/crypto/qce/common.c | 25 +++---
drivers/crypto/qce/common.h | 3 +-
drivers/crypto/qce/sha.c | 143 +++++++++++++---------------------
drivers/crypto/qce/skcipher.c | 70 ++++++++++++++---
5 files changed, 127 insertions(+), 115 deletions(-)
--
2.25.1
This patch contains the following fixes for the supported encryption
algorithms in the Qualcomm crypto engine(CE)
1. Return unsupported if key1 = key2 for AES XTS algorithm since CE
does not support this and the operation causes the engine to hang.
2. Return unsupported if any three keys are same for DES3 algorithms
since CE does not support this and the operation causes the engine to
hang.
3. Return unsupported for 0 length plain texts since crypto engine BAM
dma does not support 0 length data.
4. ECB messages do not have an IV and hence set the ivsize to 0.
5. Ensure that the data passed for ECB/CBC encryption/decryption is
blocksize aligned. Otherwise the CE hangs on the operation.
6. Allow messages of length less that 512 bytes for all other encryption
algorithms other than AES XTS. The recommendation is only for AES XTS
to have data size greater than 512 bytes.
Signed-off-by: Thara Gopinath <[email protected]>
---
v2->v3:
- Made the comparison between keys to check if any two keys are
same for triple des algorithms constant-time as per
Nym Seddon's suggestion.
drivers/crypto/qce/skcipher.c | 68 ++++++++++++++++++++++++++++++-----
1 file changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index a2d3da0ad95f..d78b932441ab 100644
--- a/drivers/crypto/qce/skcipher.c
+++ b/drivers/crypto/qce/skcipher.c
@@ -167,16 +167,32 @@ static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key,
struct crypto_tfm *tfm = crypto_skcipher_tfm(ablk);
struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
unsigned long flags = to_cipher_tmpl(ablk)->alg_flags;
+ unsigned int __keylen;
int ret;
if (!key || !keylen)
return -EINVAL;
- switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
+ /*
+ * AES XTS key1 = key2 not supported by crypto engine.
+ * Revisit to request a fallback cipher in this case.
+ */
+ if (IS_XTS(flags)) {
+ __keylen = keylen >> 1;
+ if (!memcmp(key, key + __keylen, __keylen))
+ return -EINVAL;
+ } else {
+ __keylen = keylen;
+ }
+ switch (__keylen) {
case AES_KEYSIZE_128:
case AES_KEYSIZE_256:
memcpy(ctx->enc_key, key, keylen);
break;
+ case AES_KEYSIZE_192:
+ break;
+ default:
+ return -EINVAL;
}
ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
@@ -204,12 +220,27 @@ static int qce_des3_setkey(struct crypto_skcipher *ablk, const u8 *key,
unsigned int keylen)
{
struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk);
+ u32 _key[6];
int err;
err = verify_skcipher_des3_key(ablk, key);
if (err)
return err;
+ /*
+ * The crypto engine does not support any two keys
+ * being the same for triple des algorithms. The
+ * verify_skcipher_des3_key does not check for all the
+ * below conditions. Return -ENOKEY in case any two keys
+ * are the same. Revisit to see if a fallback cipher
+ * is needed to handle this condition.
+ */
+ memcpy(_key, key, DES3_EDE_KEY_SIZE);
+ if (!((_key[0] ^ _key[2]) | (_key[1] ^ _key[3])) |
+ !((_key[2] ^ _key[4]) | (_key[3] ^ _key[5])) |
+ !((_key[0] ^ _key[4]) | (_key[1] ^ _key[5])))
+ return -ENOKEY;
+
ctx->enc_keylen = keylen;
memcpy(ctx->enc_key, key, keylen);
return 0;
@@ -221,6 +252,7 @@ static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
+ unsigned int blocksize = crypto_skcipher_blocksize(tfm);
int keylen;
int ret;
@@ -228,14 +260,34 @@ static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
- /* qce is hanging when AES-XTS request len > QCE_SECTOR_SIZE and
- * is not a multiple of it; pass such requests to the fallback
+ /* CE does not handle 0 length messages */
+ if (!req->cryptlen)
+ return -EINVAL;
+
+ /*
+ * ECB and CBC algorithms require message lengths to be
+ * multiples of block size.
+ * TODO: The spec says AES CBC mode for certain versions
+ * of crypto engine can handle partial blocks as well.
+ * Test and enable such messages.
+ */
+ if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
+ if (!IS_ALIGNED(req->cryptlen, blocksize))
+ return -EINVAL;
+
+ /*
+ * Conditions for requesting a fallback cipher
+ * AES-192 (not supported by crypto engine (CE))
+ * AES-XTS request with len <= 512 byte (not recommended to use CE)
+ * AES-XTS request with len > QCE_SECTOR_SIZE and
+ * is not a multiple of it.(Revisit this condition to check if it is
+ * needed in all versions of CE)
*/
if (IS_AES(rctx->flags) &&
- (((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
- req->cryptlen <= aes_sw_max_len) ||
- (IS_XTS(rctx->flags) && req->cryptlen > QCE_SECTOR_SIZE &&
- req->cryptlen % QCE_SECTOR_SIZE))) {
+ ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
+ (IS_XTS(rctx->flags) && ((req->cryptlen <= aes_sw_max_len) ||
+ (req->cryptlen > QCE_SECTOR_SIZE &&
+ req->cryptlen % QCE_SECTOR_SIZE))))) {
skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
skcipher_request_set_callback(&rctx->fallback_req,
req->base.flags,
@@ -307,7 +359,7 @@ static const struct qce_skcipher_def skcipher_def[] = {
.name = "ecb(aes)",
.drv_name = "ecb-aes-qce",
.blocksize = AES_BLOCK_SIZE,
- .ivsize = AES_BLOCK_SIZE,
+ .ivsize = 0,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
},
--
2.25.1
totallen is used to get the size of the data to be transformed.
This is also available via nbytes or cryptlen in the qce_sha_reqctx
and qce_cipher_ctx. Similarly offset convey nothing for the supported
encryption and authentication transformations and is always 0.
Remove these two redundant parameters in qce_start.
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/common.c | 17 +++++++----------
drivers/crypto/qce/common.h | 3 +--
drivers/crypto/qce/sha.c | 2 +-
drivers/crypto/qce/skcipher.c | 2 +-
4 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
index f7bc701a4aa2..dceb9579d87a 100644
--- a/drivers/crypto/qce/common.c
+++ b/drivers/crypto/qce/common.c
@@ -140,8 +140,7 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
return cfg;
}
-static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
- u32 totallen, u32 offset)
+static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
{
struct ahash_request *req = ahash_request_cast(async_req);
struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
@@ -306,8 +305,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
}
-static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
- u32 totallen, u32 offset)
+static int qce_setup_regs_skcipher(struct crypto_async_request *async_req)
{
struct skcipher_request *req = skcipher_request_cast(async_req);
struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
@@ -367,7 +365,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
- qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);
+ qce_write(qce, REG_ENCR_SEG_START, 0);
if (IS_CTR(flags)) {
qce_write(qce, REG_CNTR_MASK, ~0);
@@ -376,7 +374,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
qce_write(qce, REG_CNTR_MASK2, ~0);
}
- qce_write(qce, REG_SEG_SIZE, totallen);
+ qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);
/* get little endianness */
config = qce_config_reg(qce, 1);
@@ -388,17 +386,16 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
}
#endif
-int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
- u32 offset)
+int qce_start(struct crypto_async_request *async_req, u32 type)
{
switch (type) {
#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
case CRYPTO_ALG_TYPE_SKCIPHER:
- return qce_setup_regs_skcipher(async_req, totallen, offset);
+ return qce_setup_regs_skcipher(async_req);
#endif
#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
case CRYPTO_ALG_TYPE_AHASH:
- return qce_setup_regs_ahash(async_req, totallen, offset);
+ return qce_setup_regs_ahash(async_req);
#endif
default:
return -EINVAL;
diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
index 85ba16418a04..3bc244bcca2d 100644
--- a/drivers/crypto/qce/common.h
+++ b/drivers/crypto/qce/common.h
@@ -94,7 +94,6 @@ struct qce_alg_template {
void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);
int qce_check_status(struct qce_device *qce, u32 *status);
void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
-int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
- u32 offset);
+int qce_start(struct crypto_async_request *async_req, u32 type);
#endif /* _COMMON_H_ */
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index dd263c5e4dd8..a079e92b4e75 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -113,7 +113,7 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
qce_dma_issue_pending(&qce->dma);
- ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
+ ret = qce_start(async_req, tmpl->crypto_alg_type);
if (ret)
goto error_terminate;
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index d78b932441ab..a93fd3fd5f1a 100644
--- a/drivers/crypto/qce/skcipher.c
+++ b/drivers/crypto/qce/skcipher.c
@@ -143,7 +143,7 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req)
qce_dma_issue_pending(&qce->dma);
- ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);
+ ret = qce_start(async_req, tmpl->crypto_alg_type);
if (ret)
goto error_terminate;
--
2.25.1
Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
transformation. Anything else causes the engine to return back
wrong results.
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
index a73db2a5637f..f7bc701a4aa2 100644
--- a/drivers/crypto/qce/common.c
+++ b/drivers/crypto/qce/common.c
@@ -295,15 +295,15 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
{
u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
- unsigned int xtsdusize;
qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
enckeylen / 2);
qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
- /* xts du size 512B */
- xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
- qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
+ /* Set data unit size to cryptlen. Anything else causes
+ * crypto engine to return back incorrect results.
+ */
+ qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
}
static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
--
2.25.1
src_table is unused and hence remove it from struct qce_cipher_reqctx
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/cipher.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
index cffa9fc628ff..850f257d00f3 100644
--- a/drivers/crypto/qce/cipher.h
+++ b/drivers/crypto/qce/cipher.h
@@ -40,7 +40,6 @@ struct qce_cipher_reqctx {
struct scatterlist result_sg;
struct sg_table dst_tbl;
struct scatterlist *dst_sg;
- struct sg_table src_tbl;
struct scatterlist *src_sg;
unsigned int cryptlen;
struct skcipher_request fallback_req; // keep at the end
--
2.25.1
If the available data to transfer is exactly a multiple of block size, save
the last block to be transferred in qce_ahash_final (with the last block
bit set) if this is indeed the end of data stream. If not this saved block
will be transferred as part of next update. If this block is not held back
and if this is indeed the end of data stream, the digest obtained will be
wrong since qce_ahash_final will see that rctx->buflen is 0 and return
doing nothing which in turn means that a digest will not be copied to the
destination result buffer. qce_ahash_final cannot be made to alter this
behavior and allowed to proceed if rctx->buflen is 0 because the crypto
engine BAM does not allow for zero length transfers.
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/sha.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index 08aed03e2b59..dd263c5e4dd8 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -216,6 +216,25 @@ static int qce_ahash_update(struct ahash_request *req)
/* calculate how many bytes will be hashed later */
hash_later = total % blocksize;
+
+ /*
+ * At this point, there is more than one block size of data. If
+ * the available data to transfer is exactly a multiple of block
+ * size, save the last block to be transferred in qce_ahash_final
+ * (with the last block bit set) if this is indeed the end of data
+ * stream. If not this saved block will be transferred as part of
+ * next update. If this block is not held back and if this is
+ * indeed the end of data stream, the digest obtained will be wrong
+ * since qce_ahash_final will see that rctx->buflen is 0 and return
+ * doing nothing which in turn means that a digest will not be
+ * copied to the destination result buffer. qce_ahash_final cannot
+ * be made to alter this behavior and allowed to proceed if
+ * rctx->buflen is 0 because the crypto engine BAM does not allow
+ * for zero length transfers.
+ */
+ if (!hash_later)
+ hash_later = blocksize;
+
if (hash_later) {
unsigned int src_offset = req->nbytes - hash_later;
scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
--
2.25.1
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> This patch contains the following fixes for the supported encryption
> algorithms in the Qualcomm crypto engine(CE)
> 1. Return unsupported if key1 = key2 for AES XTS algorithm since CE
> does not support this and the operation causes the engine to hang.
> 2. Return unsupported if any three keys are same for DES3 algorithms
> since CE does not support this and the operation causes the engine to
> hang.
> 3. Return unsupported for 0 length plain texts since crypto engine BAM
> dma does not support 0 length data.
> 4. ECB messages do not have an IV and hence set the ivsize to 0.
> 5. Ensure that the data passed for ECB/CBC encryption/decryption is
> blocksize aligned. Otherwise the CE hangs on the operation.
> 6. Allow messages of length less that 512 bytes for all other encryption
> algorithms other than AES XTS. The recommendation is only for AES XTS
> to have data size greater than 512 bytes.
>
This seems like 6 trivial changes, that if send individually will be
easy to reason about and if there's ever any regressions it will be easy
to bisect.
So please split this patch.
Regards,
Bjorn
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
>
> v2->v3:
> - Made the comparison between keys to check if any two keys are
> same for triple des algorithms constant-time as per
> Nym Seddon's suggestion.
>
> drivers/crypto/qce/skcipher.c | 68 ++++++++++++++++++++++++++++++-----
> 1 file changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
> index a2d3da0ad95f..d78b932441ab 100644
> --- a/drivers/crypto/qce/skcipher.c
> +++ b/drivers/crypto/qce/skcipher.c
> @@ -167,16 +167,32 @@ static int qce_skcipher_setkey(struct crypto_skcipher *ablk, const u8 *key,
> struct crypto_tfm *tfm = crypto_skcipher_tfm(ablk);
> struct qce_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
> unsigned long flags = to_cipher_tmpl(ablk)->alg_flags;
> + unsigned int __keylen;
> int ret;
>
> if (!key || !keylen)
> return -EINVAL;
>
> - switch (IS_XTS(flags) ? keylen >> 1 : keylen) {
> + /*
> + * AES XTS key1 = key2 not supported by crypto engine.
> + * Revisit to request a fallback cipher in this case.
> + */
> + if (IS_XTS(flags)) {
> + __keylen = keylen >> 1;
> + if (!memcmp(key, key + __keylen, __keylen))
> + return -EINVAL;
> + } else {
> + __keylen = keylen;
> + }
> + switch (__keylen) {
> case AES_KEYSIZE_128:
> case AES_KEYSIZE_256:
> memcpy(ctx->enc_key, key, keylen);
> break;
> + case AES_KEYSIZE_192:
> + break;
> + default:
> + return -EINVAL;
> }
>
> ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
> @@ -204,12 +220,27 @@ static int qce_des3_setkey(struct crypto_skcipher *ablk, const u8 *key,
> unsigned int keylen)
> {
> struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(ablk);
> + u32 _key[6];
> int err;
>
> err = verify_skcipher_des3_key(ablk, key);
> if (err)
> return err;
>
> + /*
> + * The crypto engine does not support any two keys
> + * being the same for triple des algorithms. The
> + * verify_skcipher_des3_key does not check for all the
> + * below conditions. Return -ENOKEY in case any two keys
> + * are the same. Revisit to see if a fallback cipher
> + * is needed to handle this condition.
> + */
> + memcpy(_key, key, DES3_EDE_KEY_SIZE);
> + if (!((_key[0] ^ _key[2]) | (_key[1] ^ _key[3])) |
> + !((_key[2] ^ _key[4]) | (_key[3] ^ _key[5])) |
> + !((_key[0] ^ _key[4]) | (_key[1] ^ _key[5])))
> + return -ENOKEY;
> +
> ctx->enc_keylen = keylen;
> memcpy(ctx->enc_key, key, keylen);
> return 0;
> @@ -221,6 +252,7 @@ static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
> struct qce_cipher_ctx *ctx = crypto_skcipher_ctx(tfm);
> struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
> struct qce_alg_template *tmpl = to_cipher_tmpl(tfm);
> + unsigned int blocksize = crypto_skcipher_blocksize(tfm);
> int keylen;
> int ret;
>
> @@ -228,14 +260,34 @@ static int qce_skcipher_crypt(struct skcipher_request *req, int encrypt)
> rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
> keylen = IS_XTS(rctx->flags) ? ctx->enc_keylen >> 1 : ctx->enc_keylen;
>
> - /* qce is hanging when AES-XTS request len > QCE_SECTOR_SIZE and
> - * is not a multiple of it; pass such requests to the fallback
> + /* CE does not handle 0 length messages */
> + if (!req->cryptlen)
> + return -EINVAL;
> +
> + /*
> + * ECB and CBC algorithms require message lengths to be
> + * multiples of block size.
> + * TODO: The spec says AES CBC mode for certain versions
> + * of crypto engine can handle partial blocks as well.
> + * Test and enable such messages.
> + */
> + if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
> + if (!IS_ALIGNED(req->cryptlen, blocksize))
> + return -EINVAL;
> +
> + /*
> + * Conditions for requesting a fallback cipher
> + * AES-192 (not supported by crypto engine (CE))
> + * AES-XTS request with len <= 512 byte (not recommended to use CE)
> + * AES-XTS request with len > QCE_SECTOR_SIZE and
> + * is not a multiple of it.(Revisit this condition to check if it is
> + * needed in all versions of CE)
> */
> if (IS_AES(rctx->flags) &&
> - (((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
> - req->cryptlen <= aes_sw_max_len) ||
> - (IS_XTS(rctx->flags) && req->cryptlen > QCE_SECTOR_SIZE &&
> - req->cryptlen % QCE_SECTOR_SIZE))) {
> + ((keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_256) ||
> + (IS_XTS(rctx->flags) && ((req->cryptlen <= aes_sw_max_len) ||
> + (req->cryptlen > QCE_SECTOR_SIZE &&
> + req->cryptlen % QCE_SECTOR_SIZE))))) {
> skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
> skcipher_request_set_callback(&rctx->fallback_req,
> req->base.flags,
> @@ -307,7 +359,7 @@ static const struct qce_skcipher_def skcipher_def[] = {
> .name = "ecb(aes)",
> .drv_name = "ecb-aes-qce",
> .blocksize = AES_BLOCK_SIZE,
> - .ivsize = AES_BLOCK_SIZE,
> + .ivsize = 0,
> .min_keysize = AES_MIN_KEY_SIZE,
> .max_keysize = AES_MAX_KEY_SIZE,
> },
> --
> 2.25.1
>
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
> transformation. Anything else causes the engine to return back
> wrong results.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
> drivers/crypto/qce/common.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
> index a73db2a5637f..f7bc701a4aa2 100644
> --- a/drivers/crypto/qce/common.c
> +++ b/drivers/crypto/qce/common.c
> @@ -295,15 +295,15 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
> {
> u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
> unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
> - unsigned int xtsdusize;
>
> qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
> enckeylen / 2);
> qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
>
> - /* xts du size 512B */
> - xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
I wonder if this is a hardware limitation that has gone away in the
newer chips. I am however not able to find anything about it, so I'm in
favor of merging this patch and if anyone actually uses the driver on
the older hardware we'd have to go back and quirk it somehow.
Acked-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> - qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
> + /* Set data unit size to cryptlen. Anything else causes
> + * crypto engine to return back incorrect results.
> + */
> + qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
> }
>
> static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> --
> 2.25.1
>
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> src_table is unused and hence remove it from struct qce_cipher_reqctx
>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
> drivers/crypto/qce/cipher.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
> index cffa9fc628ff..850f257d00f3 100644
> --- a/drivers/crypto/qce/cipher.h
> +++ b/drivers/crypto/qce/cipher.h
> @@ -40,7 +40,6 @@ struct qce_cipher_reqctx {
> struct scatterlist result_sg;
> struct sg_table dst_tbl;
> struct scatterlist *dst_sg;
> - struct sg_table src_tbl;
Please also remove the associated kerneldoc entry.
Regards,
Bjorn
> struct scatterlist *src_sg;
> unsigned int cryptlen;
> struct skcipher_request fallback_req; // keep at the end
> --
> 2.25.1
>
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> totallen is used to get the size of the data to be transformed.
> This is also available via nbytes or cryptlen in the qce_sha_reqctx
> and qce_cipher_ctx. Similarly offset convey nothing for the supported
> encryption and authentication transformations and is always 0.
> Remove these two redundant parameters in qce_start.
>
Please drop "drivers: " from $subject.
Reviewed-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
> drivers/crypto/qce/common.c | 17 +++++++----------
> drivers/crypto/qce/common.h | 3 +--
> drivers/crypto/qce/sha.c | 2 +-
> drivers/crypto/qce/skcipher.c | 2 +-
> 4 files changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
> index f7bc701a4aa2..dceb9579d87a 100644
> --- a/drivers/crypto/qce/common.c
> +++ b/drivers/crypto/qce/common.c
> @@ -140,8 +140,7 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
> return cfg;
> }
>
> -static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
> - u32 totallen, u32 offset)
> +static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
> {
> struct ahash_request *req = ahash_request_cast(async_req);
> struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
> @@ -306,8 +305,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
> qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
> }
>
> -static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> - u32 totallen, u32 offset)
> +static int qce_setup_regs_skcipher(struct crypto_async_request *async_req)
> {
> struct skcipher_request *req = skcipher_request_cast(async_req);
> struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
> @@ -367,7 +365,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
>
> qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
> qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
> - qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);
> + qce_write(qce, REG_ENCR_SEG_START, 0);
>
> if (IS_CTR(flags)) {
> qce_write(qce, REG_CNTR_MASK, ~0);
> @@ -376,7 +374,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> qce_write(qce, REG_CNTR_MASK2, ~0);
> }
>
> - qce_write(qce, REG_SEG_SIZE, totallen);
> + qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);
>
> /* get little endianness */
> config = qce_config_reg(qce, 1);
> @@ -388,17 +386,16 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> }
> #endif
>
> -int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
> - u32 offset)
> +int qce_start(struct crypto_async_request *async_req, u32 type)
> {
> switch (type) {
> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> case CRYPTO_ALG_TYPE_SKCIPHER:
> - return qce_setup_regs_skcipher(async_req, totallen, offset);
> + return qce_setup_regs_skcipher(async_req);
> #endif
> #ifdef CONFIG_CRYPTO_DEV_QCE_SHA
> case CRYPTO_ALG_TYPE_AHASH:
> - return qce_setup_regs_ahash(async_req, totallen, offset);
> + return qce_setup_regs_ahash(async_req);
> #endif
> default:
> return -EINVAL;
> diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
> index 85ba16418a04..3bc244bcca2d 100644
> --- a/drivers/crypto/qce/common.h
> +++ b/drivers/crypto/qce/common.h
> @@ -94,7 +94,6 @@ struct qce_alg_template {
> void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);
> int qce_check_status(struct qce_device *qce, u32 *status);
> void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
> -int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
> - u32 offset);
> +int qce_start(struct crypto_async_request *async_req, u32 type);
>
> #endif /* _COMMON_H_ */
> diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
> index dd263c5e4dd8..a079e92b4e75 100644
> --- a/drivers/crypto/qce/sha.c
> +++ b/drivers/crypto/qce/sha.c
> @@ -113,7 +113,7 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
>
> qce_dma_issue_pending(&qce->dma);
>
> - ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
> + ret = qce_start(async_req, tmpl->crypto_alg_type);
> if (ret)
> goto error_terminate;
>
> diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
> index d78b932441ab..a93fd3fd5f1a 100644
> --- a/drivers/crypto/qce/skcipher.c
> +++ b/drivers/crypto/qce/skcipher.c
> @@ -143,7 +143,7 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req)
>
> qce_dma_issue_pending(&qce->dma);
>
> - ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);
> + ret = qce_start(async_req, tmpl->crypto_alg_type);
> if (ret)
> goto error_terminate;
>
> --
> 2.25.1
>