Convert Qualcomm QCE crypto devicetree binding to YAML.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
.../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++
2 files changed, 69 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
deleted file mode 100644
index fdd53b184ba8..000000000000
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm crypto engine driver
-
-Required properties:
-
-- compatible : should be "qcom,crypto-v5.1"
-- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
-- dmas : DMA specifiers for tx and rx dma channels. For more see
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names : DMA request names should be "rx" and "tx"
-
-Example:
- crypto@fd45a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0xfd45a000 0x6000>;
- clocks = <&gcc GCC_CE2_AHB_CLK>,
- <&gcc GCC_CE2_AXI_CLK>,
- <&gcc GCC_CE2_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- };
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
new file mode 100644
index 000000000000..a691cd08f372
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+ - Bhupesh Sharma <[email protected]>
+
+description: |
+ This document defines the binding for the QCE crypto
+ controller found on Qualcomm parts.
+
+properties:
+ compatible:
+ const: qcom,crypto-v5.1
+
+ reg:
+ maxItems: 1
+ description: |
+ Specifies base physical address and size of the registers map.
+
+ clocks:
+ items:
+ - description: iface clocks register interface.
+ - description: bus clocks data transfer interface.
+ - description: core clocks rest of the crypto block.
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ dmas:
+ items:
+ - description: DMA specifiers for tx dma channel.
+ - description: DMA specifiers for rx dma channel.
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+ crypto-engine@fd45a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0xfd45a000 0x6000>;
+ clocks = <&gcc GCC_CE2_AHB_CLK>,
+ <&gcc GCC_CE2_AXI_CLK>,
+ <&gcc GCC_CE2_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ };
--
2.31.1
On Wed, May 19, 2021 at 08:06:47PM +0530, Bhupesh Sharma wrote:
> Convert Qualcomm QCE crypto devicetree binding to YAML.
>
> Cc: Thara Gopinath <[email protected]>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Andy Gross <[email protected]>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: Michael Turquette <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> .../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
> .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++
> 2 files changed, 69 insertions(+), 25 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
> create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> deleted file mode 100644
> index fdd53b184ba8..000000000000
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Qualcomm crypto engine driver
> -
> -Required properties:
> -
> -- compatible : should be "qcom,crypto-v5.1"
> -- reg : specifies base physical address and size of the registers map
> -- clocks : phandle to clock-controller plus clock-specifier pair
> -- clock-names : "iface" clocks register interface
> - "bus" clocks data transfer interface
> - "core" clocks rest of the crypto block
> -- dmas : DMA specifiers for tx and rx dma channels. For more see
> - Documentation/devicetree/bindings/dma/dma.txt
> -- dma-names : DMA request names should be "rx" and "tx"
> -
> -Example:
> - crypto@fd45a000 {
> - compatible = "qcom,crypto-v5.1";
> - reg = <0xfd45a000 0x6000>;
> - clocks = <&gcc GCC_CE2_AHB_CLK>,
> - <&gcc GCC_CE2_AXI_CLK>,
> - <&gcc GCC_CE2_CLK>;
> - clock-names = "iface", "bus", "core";
> - dmas = <&cryptobam 2>, <&cryptobam 3>;
> - dma-names = "rx", "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> new file mode 100644
> index 000000000000..a691cd08f372
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm crypto engine driver
> +
> +maintainers:
> + - Bhupesh Sharma <[email protected]>
> +
> +description: |
> + This document defines the binding for the QCE crypto
> + controller found on Qualcomm parts.
> +
> +properties:
> + compatible:
> + const: qcom,crypto-v5.1
> +
> + reg:
> + maxItems: 1
> + description: |
> + Specifies base physical address and size of the registers map.
Yep, that's every 'reg'. Drop.
With that dropped,
Reviewed-by: Rob Herring <[email protected]>
> +
> + clocks:
> + items:
> + - description: iface clocks register interface.
> + - description: bus clocks data transfer interface.
> + - description: core clocks rest of the crypto block.
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> +
> + dmas:
> + items:
> + - description: DMA specifiers for tx dma channel.
> + - description: DMA specifiers for rx dma channel.
> +
> + dma-names:
> + items:
> + - const: rx
> + - const: tx
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - dmas
> + - dma-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-apq8084.h>
> + crypto-engine@fd45a000 {
> + compatible = "qcom,crypto-v5.1";
> + reg = <0xfd45a000 0x6000>;
> + clocks = <&gcc GCC_CE2_AHB_CLK>,
> + <&gcc GCC_CE2_AXI_CLK>,
> + <&gcc GCC_CE2_CLK>;
> + clock-names = "iface", "bus", "core";
> + dmas = <&cryptobam 2>, <&cryptobam 3>;
> + dma-names = "rx", "tx";
> + };
> --
> 2.31.1
>