As both SDCC and UFS drivers use the ICE with duplicated implementation,
while none of the currently supported platforms make use concomitantly
of the same ICE IP block instance, the new SM8550 allows both UFS and
SDCC to do so. In order to support such scenario, there is a need for
a unified implementation and a devicetree node to be shared between
both types of storage devices. So lets drop the duplicate implementation
of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
For now, only SM8550 has been added to support the new approach. This
also involves adding support for HW version 4.x.
The v5 is here:
https://lore.kernel.org/all/[email protected]/
Changes since v5:
* See each individual patch for changelogs.
Changes since v4:
* dropped the SDHCI dt-bindings patch as it will be added along
with the first use of qcom,ice property from an SDHCI DT node
Abel Vesa (6):
dt-bindings: crypto: Add Qualcomm Inline Crypto Engine
dt-bindings: ufs: qcom: Add ICE phandle
soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
scsi: ufs: ufs-qcom: Switch to the new ICE API
mmc: sdhci-msm: Switch to the new ICE API
arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
.../crypto/qcom,inline-crypto-engine.yaml | 42 ++
.../devicetree/bindings/ufs/qcom,ufs.yaml | 26 ++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +
drivers/mmc/host/Kconfig | 2 +-
drivers/mmc/host/sdhci-msm.c | 223 +++--------
drivers/soc/qcom/Kconfig | 4 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/ice.c | 366 ++++++++++++++++++
drivers/ufs/host/Kconfig | 2 +-
drivers/ufs/host/Makefile | 4 +-
drivers/ufs/host/ufs-qcom-ice.c | 244 ------------
drivers/ufs/host/ufs-qcom.c | 99 ++++-
drivers/ufs/host/ufs-qcom.h | 32 +-
include/soc/qcom/ice.h | 37 ++
14 files changed, 637 insertions(+), 454 deletions(-)
create mode 100644 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
create mode 100644 drivers/soc/qcom/ice.c
delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c
create mode 100644 include/soc/qcom/ice.h
--
2.34.1
Add support for UFS ICE by adding the qcom,ice property and the
ICE dedicated devicetree node. While at it, add the reg-name property
to the UFS HC node to be in line with older platforms.
Signed-off-by: Abel Vesa <[email protected]>
---
The v5 is here:
https://lore.kernel.org/all/[email protected]/
Changes since v5:
* Dropped the reg-names property from UFS node as it was not needed and
makes the bindings check fail
Changes since v4:
* none
Changes since v3:
* none
arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d252658c73dd..2b3a721292b6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1932,9 +1932,18 @@ ufs_mem_hc: ufs@1d84000 {
<0 0>,
<0 0>,
<0 0>;
+ qcom,ice = <&ice>;
+
status = "disabled";
};
+ ice: crypto@1d88000 {
+ compatible = "qcom,sm8550-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d88000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
--
2.34.1
On Fri, Apr 07, 2023 at 01:50:29PM +0300, Abel Vesa wrote:
> Add support for UFS ICE by adding the qcom,ice property and the
> ICE dedicated devicetree node. While at it, add the reg-name property
> to the UFS HC node to be in line with older platforms.
>
> Signed-off-by: Abel Vesa <[email protected]>
> ---
>
> The v5 is here:
> https://lore.kernel.org/all/[email protected]/
>
> Changes since v5:
> * Dropped the reg-names property from UFS node as it was not needed and
> makes the bindings check fail
You forgot to drop the related sentence from the commit message.
Regards,
Bjorn
>
> Changes since v4:
> * none
>
> Changes since v3:
> * none
>
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index d252658c73dd..2b3a721292b6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1932,9 +1932,18 @@ ufs_mem_hc: ufs@1d84000 {
> <0 0>,
> <0 0>,
> <0 0>;
> + qcom,ice = <&ice>;
> +
> status = "disabled";
> };
>
> + ice: crypto@1d88000 {
> + compatible = "qcom,sm8550-inline-crypto-engine",
> + "qcom,inline-crypto-engine";
> + reg = <0 0x01d88000 0 0x8000>;
> + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0 0x01f40000 0 0x20000>;
> --
> 2.34.1
>
On Fri, Apr 07, 2023 at 01:50:23PM +0300, Abel Vesa wrote:
> As both SDCC and UFS drivers use the ICE with duplicated implementation,
> while none of the currently supported platforms make use concomitantly
> of the same ICE IP block instance, the new SM8550 allows both UFS and
> SDCC to do so. In order to support such scenario, there is a need for
> a unified implementation and a devicetree node to be shared between
> both types of storage devices. So lets drop the duplicate implementation
> of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
>
> For now, only SM8550 has been added to support the new approach. This
> also involves adding support for HW version 4.x.
>
I picked the ICE driver and pushed it out to make it possible to pick up
the mmc and ufs patches independently.
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/[email protected]
Regards,
Bjorn
> The v5 is here:
> https://lore.kernel.org/all/[email protected]/
>
> Changes since v5:
> * See each individual patch for changelogs.
>
> Changes since v4:
> * dropped the SDHCI dt-bindings patch as it will be added along
> with the first use of qcom,ice property from an SDHCI DT node
>
> Abel Vesa (6):
> dt-bindings: crypto: Add Qualcomm Inline Crypto Engine
> dt-bindings: ufs: qcom: Add ICE phandle
> soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
> scsi: ufs: ufs-qcom: Switch to the new ICE API
> mmc: sdhci-msm: Switch to the new ICE API
> arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
>
> .../crypto/qcom,inline-crypto-engine.yaml | 42 ++
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 ++
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +
> drivers/mmc/host/Kconfig | 2 +-
> drivers/mmc/host/sdhci-msm.c | 223 +++--------
> drivers/soc/qcom/Kconfig | 4 +
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/ice.c | 366 ++++++++++++++++++
> drivers/ufs/host/Kconfig | 2 +-
> drivers/ufs/host/Makefile | 4 +-
> drivers/ufs/host/ufs-qcom-ice.c | 244 ------------
> drivers/ufs/host/ufs-qcom.c | 99 ++++-
> drivers/ufs/host/ufs-qcom.h | 32 +-
> include/soc/qcom/ice.h | 37 ++
> 14 files changed, 637 insertions(+), 454 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> create mode 100644 drivers/soc/qcom/ice.c
> delete mode 100644 drivers/ufs/host/ufs-qcom-ice.c
> create mode 100644 include/soc/qcom/ice.h
>
> --
> 2.34.1
>
On Fri, 7 Apr 2023 13:50:23 +0300, Abel Vesa wrote:
> As both SDCC and UFS drivers use the ICE with duplicated implementation,
> while none of the currently supported platforms make use concomitantly
> of the same ICE IP block instance, the new SM8550 allows both UFS and
> SDCC to do so. In order to support such scenario, there is a need for
> a unified implementation and a devicetree node to be shared between
> both types of storage devices. So lets drop the duplicate implementation
> of the ICE from both SDCC and UFS and make it a dedicated (soc) driver.
>
> [...]
Applied, thanks!
[1/6] dt-bindings: crypto: Add Qualcomm Inline Crypto Engine
commit: f6ff91a47ac57cb1118d94020302617b6b22c0d1
[3/6] soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
commit: 2afbf43a4aec6e31dac7835e65d52c867f2be400
[6/6] arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node
commit: b8630c48b43fcf77039c04a1d30153e283cf41b4
Best regards,
--
Bjorn Andersson <[email protected]>