Changes since v6:
-----------------
- v6 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Collected Acks, R-Bs and Tested-by for various patches.
- Addressed Konrad's comment about iommu sids for sm8150 and sm8250
crypto node entries.
- Addressed Konrad's and Stephan's comments about adding RPM clock for
crypto blocks on qcm2290 and sm6115.
Changes since v5:
-----------------
- v5 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Collected Ack from Rob for [PATCH 01/11].
- Addressed Georgi's comment about interconnect cells in [PATCH 10/11].
Changes since v4:
-----------------
- v4 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Collected R-Bs from Konrad for a couple of patches sent in v4.
- Fixed incorrect email IDs for a couple of patches sent in v3, which I used for
some patches created on a different work machine.
- No functional changes since v3.
Changes since v3:
-----------------
- v3 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Collected Acks from Krzysztof for a couple of patches sent in v3.
- Fixed review comments from Krzysztof regarding DMA binding document
and also added a couple of new patches which are required to fix the
'dtbs_check' errors highlighted after this fix.
Changes since v2:
-----------------
- v2 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- No functional change since v2. As the sdm845 patch from v1 was accepted in linux-next,
dropped it from this version.
Changes since v1:
-----------------
- v1 can be viewed here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Folded the BAM DMA dt-binding change.
(sent earlier as: https://lore.kernel.org/linux-arm-msm/[email protected]/)
- Folded the QCE dt-binding change.
(sent earlier as: https://lore.kernel.org/linux-arm-msm/[email protected]/)
- Folded Neil's SM8450 dts patch in this series.
- Addressed review comments from Rob, Stephan and Konrad.
- Collected Konrad's R-B for [PATCH 5/9].
This patchset enables Crypto Engine support for Qualcomm SoCs like
SM6115, SM8150, SM8250, SM8350 and SM8450.
Note that:
- SM8250 crypto engine patch utilizes the work already done by myself and
Vladimir.
- SM8350 crypto engine patch utilizes the work already done by Robert.
- SM8450 crypto engine patch utilizes the work already done by Neil.
Also this patchset is rebased on linux-next/master.
Bhupesh Sharma (10):
dt-bindings: dma: Add support for SM6115 and QCM2290 SoCs
dt-bindings: dma: Increase iommu maxItems for BAM DMA
arm64: dts: qcom: sdm8550: Fix the BAM DMA engine compatible string
arm64: dts: qcom: sdm845: Fix the slimbam DMA engine compatible string
dt-bindings: qcom-qce: Fix compatible combinations for SM8150 and
IPQ4019 SoCs
dt-bindings: qcom-qce: Add compatibles for SM6115 and QCM2290
arm64: dts: qcom: sm6115: Add Crypto Engine support
arm64: dts: qcom: sm8150: Add Crypto Engine support
arm64: dts: qcom: sm8250: Add Crypto Engine support
arm64: dts: qcom: sm8350: Add Crypto Engine support
Neil Armstrong (1):
arm64: dts: qcom: sm8450: add crypto nodes
.../devicetree/bindings/crypto/qcom-qce.yaml | 50 +++++++++++++++----
.../devicetree/bindings/dma/qcom,bam-dma.yaml | 22 +++++---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6115.dtsi | 25 ++++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 30 +++++++++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 22 ++++++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 +++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
9 files changed, 194 insertions(+), 19 deletions(-)
--
2.38.1
Since SM8450 BAM DMA engine supports five iommu entries,
increase the maxItems in the iommu property section, without
which 'dtbs_check' reports the following error:
arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dtb:
dma-controller@1dc4000: iommus: is too long
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
index c663b6102f50..5636d38f712a 100644
--- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
@@ -44,7 +44,7 @@ properties:
iommus:
minItems: 1
- maxItems: 4
+ maxItems: 5
num-channels:
$ref: /schemas/types.yaml#/definitions/uint32
--
2.38.1
As per documentation, Qualcomm SM8550 SoC supports BAM DMA
engine v1.7.4, so use the correct compatible strings.
Reviewed-by: Konrad Dybcio <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 6e9bad8f6f33..e477ea391e93 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1839,7 +1839,7 @@ pcie1_phy: phy@1c0e000 {
};
cryptobam: dma-controller@1dc4000 {
- compatible = "qcom,bam-v1.7.0";
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
--
2.38.1
Currently the compatible list available in 'qce' dt-bindings does not
support SM8150 and IPQ4019 SoCs directly which may lead to potential
'dtbs_check' error(s).
Fix the same.
Fixes: 00f3bc2db351 ("dt-bindings: qcom-qce: Add new SoC compatible strings for Qualcomm QCE IP")
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Acked-by: Rob Herring <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index e375bd981300..90ddf98a6df9 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -24,6 +24,12 @@ properties:
deprecated: true
description: Kept only for ABI backward compatibility
+ - items:
+ - enum:
+ - qcom,ipq4019-qce
+ - qcom,sm8150-qce
+ - const: qcom,qce
+
- items:
- enum:
- qcom,ipq6018-qce
--
2.38.1
As per documentation, Qualcomm SDM845 SoC supports SLIMBAM DMA
engine v1.7.4, so use the correct compatible strings.
Reviewed-by: Konrad Dybcio <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 90424442bb4a..4d768e09d62d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5212,7 +5212,7 @@ msi-controller@17a40000 {
};
slimbam: dma-controller@17184000 {
- compatible = "qcom,bam-v1.7.0";
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0 0x17184000 0 0x2a000>;
num-channels = <31>;
--
2.38.1
The core clock for the Crypto Engine block on Qualcomm SoCs SM6115 and
QCM2290 are provided via the RPM block.
So mark the compatibles for these SoCs to indicate that only 'core'
clock is required for such SoCs.
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 44 +++++++++++++++----
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 90ddf98a6df9..bb828068c3b8 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -35,7 +35,9 @@ properties:
- qcom,ipq6018-qce
- qcom,ipq8074-qce
- qcom,msm8996-qce
+ - qcom,qcm2290-qce
- qcom,sdm845-qce
+ - qcom,sm6115-qce
- const: qcom,ipq4019-qce
- const: qcom,qce
@@ -52,16 +54,12 @@ properties:
maxItems: 1
clocks:
- items:
- - description: iface clocks register interface.
- - description: bus clocks data transfer interface.
- - description: core clocks rest of the crypto block.
+ minItems: 1
+ maxItems: 3
clock-names:
- items:
- - const: iface
- - const: bus
- - const: core
+ minItems: 1
+ maxItems: 3
iommus:
minItems: 1
@@ -95,9 +93,37 @@ allOf:
enum:
- qcom,crypto-v5.1
- qcom,crypto-v5.4
- - qcom,ipq4019-qce
+ - qcom,ipq6018-qce
+ - qcom,ipq8074-qce
+ - qcom,msm8996-qce
+ - qcom,sdm845-qce
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ required:
+ - clocks
+ - clock-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcm2290-qce
+ - qcom,sm6115-qce
then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: core
required:
- clocks
- clock-names
--
2.38.1
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm6115.dtsi'.
Reviewed-by: Konrad Dybcio <[email protected]>
Tested-by: Konrad Dybcio <[email protected]>
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 631ca327e064..27ff42cf6066 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 {
status = "disabled";
};
+ cryptobam: dma-controller@1b04000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01b04000 0x0 0x24000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <8>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x94 0x11>,
+ <&apps_smmu 0x96 0x11>;
+ };
+
+ crypto: crypto@1b3a000 {
+ compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
+ reg = <0x0 0x01b3a000 0x0 0x6000>;
+ clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+ clock-names = "core";
+
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x94 0x11>,
+ <&apps_smmu 0x96 0x11>;
+ };
+
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
--
2.38.1
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8250.dtsi'.
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Co-developed-by and Signed-off-by: Vladimir Zapolskiy <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7bea916900e2..79fad917d142 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2232,6 +2232,38 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <8>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x592 0x0000>,
+ <&apps_smmu 0x598 0x0000>,
+ <&apps_smmu 0x599 0x0000>,
+ <&apps_smmu 0x59f 0x0000>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x592 0x0000>,
+ <&apps_smmu 0x598 0x0000>,
+ <&apps_smmu 0x599 0x0000>,
+ <&apps_smmu 0x59f 0x0000>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
--
2.38.1
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8150.dtsi'.
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 30 ++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 2c377d7bb3a2..2a5b2b99968a 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2085,6 +2085,36 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ num-channels = <8>;
+ qcom,num-ees = <2>;
+ iommus = <&apps_smmu 0x502 0x0641>,
+ <&apps_smmu 0x504 0x0011>,
+ <&apps_smmu 0x506 0x0011>,
+ <&apps_smmu 0x508 0x0011>,
+ <&apps_smmu 0x512 0x0000>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x502 0x0641>,
+ <&apps_smmu 0x504 0x0011>,
+ <&apps_smmu 0x506 0x0011>,
+ <&apps_smmu 0x508 0x0011>,
+ <&apps_smmu 0x512 0x0000>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
--
2.38.1
Add crypto engine (CE) and CE BAM related nodes and definitions to
'sm8350.dtsi'.
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Co-developed-by and Signed-off-by: Robert Foss <[email protected]>
[Bhupesh: Switch to '#interconnect-cells = <2>', available since commit 4f287e31ff5f]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index ebcb481571c2..d00542f29dc8 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1726,6 +1726,28 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ iommus = <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "memory";
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sm8350-ipa";
--
2.38.1
From: Neil Armstrong <[email protected]>
Add crypto engine (CE) and CE BAM related nodes and definitions
for the SM8450 SoC.
Tested-by: Anders Roxell <[email protected]>
Tested-by: Linux Kernel Functional Testing <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
[Bhupesh: Corrected the compatible list]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 595533aeafc4..1c65f7dc67f2 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -4138,6 +4138,34 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x28000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ iommus = <&apps_smmu 0x584 0x11>,
+ <&apps_smmu 0x588 0x0>,
+ <&apps_smmu 0x598 0x5>,
+ <&apps_smmu 0x59a 0x0>,
+ <&apps_smmu 0x59f 0x0>;
+ };
+
+ crypto: crypto@1de0000 {
+ compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x11>,
+ <&apps_smmu 0x588 0x0>,
+ <&apps_smmu 0x598 0x5>,
+ <&apps_smmu 0x59a 0x0>,
+ <&apps_smmu 0x59f 0x0>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "memory";
+ };
+
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
--
2.38.1
On Sat, May 20, 2023 at 03:18:09AM +0530, Bhupesh Sharma wrote:
> Add crypto engine (CE) and CE BAM related nodes and definitions to
> 'sm6115.dtsi'.
>
> Reviewed-by: Konrad Dybcio <[email protected]>
> Tested-by: Konrad Dybcio <[email protected]>
> Tested-by: Anders Roxell <[email protected]>
> Tested-by: Linux Kernel Functional Testing <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 631ca327e064..27ff42cf6066 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -661,6 +661,31 @@ usb_hsphy: phy@1613000 {
> status = "disabled";
> };
>
> + cryptobam: dma-controller@1b04000 {
> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> + reg = <0x0 0x01b04000 0x0 0x24000>;
> + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + num-channels = <8>;
> + qcom,num-ees = <2>;
I would also add the RPM_SMD_CE1_CLK clock here and then omit
"num-channels" and "qcom,num-ees" (with [1]). It's not strictly
necessary but will guarantee that the clock is running whenever the BAM
is accessed (potentially avoiding crashes). And it seems to be the
typical approach so far, see e.g. sdm845. RPMH_CE_CLK is used on both
&cryptobam and &crypto there.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/commit/?id=8975dd41a9dbca3b47f7b8dac5bc4dfb23011000
Thanks,
Stephan