Add support for Tegra Security Engine which can accelerates various
crypto algorithms. The Engine has two separate instances within for
AES and HASH algorithms respectively.
The driver registers two crypto engines - one for AES and another for
HASH algorithms and these operate independently and both uses the host1x
bus. Additionally, it provides hardware-assisted key protection for up to
15 symmetric keys which it can use for the cipher operations.
v2->v3:
* Update compatible in driver and device trees.
* Remove extra new lines and symbols in binding doc.
v1->v2:
* Update probe errors with 'dev_err_probe'.
* Clean up function prototypes and redundant prints.
* Remove readl/writel wrappers.
* Fix test bot warnings.
Akhil R (5):
dt-bindings: crypto: Add Tegra Security Engine
gpu: host1x: Add Tegra SE to SID table
crypto: tegra: Add Tegra Security Engine driver
arm64: defconfig: Enable Tegra Security Engine
arm64: tegra: Add Tegra Security Engine DT nodes
.../crypto/nvidia,tegra234-se-aes.yaml | 53 +
.../crypto/nvidia,tegra234-se-hash.yaml | 53 +
MAINTAINERS | 5 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 +
arch/arm64/configs/defconfig | 1 +
drivers/crypto/Kconfig | 8 +
drivers/crypto/Makefile | 1 +
drivers/crypto/tegra/Makefile | 9 +
drivers/crypto/tegra/tegra-se-aes.c | 1932 +++++++++++++++++
drivers/crypto/tegra/tegra-se-hash.c | 1022 +++++++++
drivers/crypto/tegra/tegra-se-key.c | 155 ++
drivers/crypto/tegra/tegra-se-main.c | 439 ++++
drivers/crypto/tegra/tegra-se.h | 569 +++++
drivers/gpu/host1x/dev.c | 24 +
14 files changed, 4287 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-aes.yaml
create mode 100644 Documentation/devicetree/bindings/crypto/nvidia,tegra234-se-hash.yaml
create mode 100644 drivers/crypto/tegra/Makefile
create mode 100644 drivers/crypto/tegra/tegra-se-aes.c
create mode 100644 drivers/crypto/tegra/tegra-se-hash.c
create mode 100644 drivers/crypto/tegra/tegra-se-key.c
create mode 100644 drivers/crypto/tegra/tegra-se-main.c
create mode 100644 drivers/crypto/tegra/tegra-se.h
--
2.17.1
Add Tegra Security Engine details to the SID table in host1x driver.
These will be referred when registering the SE as host1x device.
Signed-off-by: Akhil R <[email protected]>
---
drivers/gpu/host1x/dev.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 42fd504abbcd..b564c7042235 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -214,6 +214,30 @@ static const struct host1x_info host1x07_info = {
* and firmware stream ID in the MMIO path table.
*/
static const struct host1x_sid_entry tegra234_sid_table[] = {
+ {
+ /* SE2 MMIO */
+ .base = 0x1658,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 MMIO */
+ .base = 0x1660,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE2 channel */
+ .base = 0x1738,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 channel */
+ .base = 0x1740,
+ .offset = 0x90,
+ .limit = 0x90
+ },
{
/* VIC channel */
.base = 0x17b8,
--
2.17.1
Enable Tegra Security Engine which can accelerate various
AES and HASH algorithms on supported hardware.
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0e67a4849b91..4f5b01cc3b1a 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1602,6 +1602,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
CONFIG_CRYPTO_DEV_QCE=m
CONFIG_CRYPTO_DEV_QCOM_RNG=m
+CONFIG_CRYPTO_DEV_TEGRA=m
CONFIG_CRYPTO_DEV_CCREE=m
CONFIG_CRYPTO_DEV_HISI_SEC2=m
CONFIG_CRYPTO_DEV_HISI_ZIP=m
--
2.17.1