This patch set does the following:
- Updates the Makefile for xilinx subdirectory
- Adds communication layer support for sha_hash in zynqmp.c
- Adds device tree node for ZynqMP SHA3 driver
- Adds dt-binding docs for Xilinx ZynqMP SHA3 driver
- Adds Xilinx ZynqMP driver for SHA3 Algorithm
- Updates the list of MAINTAINERS
Harsha (6):
drivers: crypto: Updated Makefile for xilinx subdirectory
firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver
arm64: dts: zynqmp: Add Xilinx SHA3 node
crypto: xilinx: Add Xilinx SHA3 driver
MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver
.../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 +++
MAINTAINERS | 6 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 +
drivers/crypto/Kconfig | 10 +
drivers/crypto/Makefile | 2 +-
drivers/crypto/xilinx/Makefile | 1 +
drivers/crypto/xilinx/zynqmp-sha.c | 265 +++++++++++++++++++++
drivers/firmware/xilinx/zynqmp.c | 26 ++
include/linux/firmware/xlnx-zynqmp.h | 8 +
9 files changed, 351 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
--
1.8.2.1
This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
SHA3 hash of given data.
Signed-off-by: Harsha <[email protected]>
---
drivers/firmware/xilinx/zynqmp.c | 26 ++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 3dd45a7..a84c5ea 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1117,6 +1117,32 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
/**
+ * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
+ * @address: Address of the data/ Address of output buffer where
+ * hash should be stored.
+ * @size: Size of the data.
+ * @flags:
+ * BIT(0) - for initializing csudma driver and SHA3(Here address
+ * and size inputs can be NULL).
+ * BIT(1) - to call Sha3_Update API which can be called multiple
+ * times when data is not contiguous.
+ * BIT(2) - to get final hash of the whole updated data.
+ * Hash will be overwritten at provided address with
+ * 48 bytes.
+ *
+ * Return: Returns status, either success or error code.
+ */
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
+{
+ u32 lower_addr = lower_32_bits(address);
+ u32 upper_addr = upper_32_bits(address);
+
+ return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,
+ size, flags, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
+
+/**
* zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart
* @type: Shutdown or restart? 0 for shutdown, 1 for restart
* @subtype: Specifies which system should be restarted or shut down
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 47fd4e5..38ef708 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -78,6 +78,7 @@ enum pm_api_id {
PM_FPGA_LOAD = 22,
PM_FPGA_GET_STATUS = 23,
PM_GET_CHIPID = 24,
+ PM_SECURE_SHA = 26,
PM_PINCTRL_REQUEST = 28,
PM_PINCTRL_RELEASE = 29,
PM_PINCTRL_GET_FUNCTION = 30,
@@ -410,6 +411,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
int zynqmp_pm_write_ggs(u32 index, u32 value);
@@ -581,6 +583,12 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return -ENODEV;
}
+static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
const u32 flags)
{
--
1.8.2.1
This patch updates the Makefile for xilinx subdirectory.
Currently the xilinx subdirectory includes only zynqmp-aes-gcm.c.
Since this patch series adds zynqmp-sha.c in the xilinx subdirectory,
so the Makefile needs to be updated.
Signed-off-by: Harsha <[email protected]>
---
drivers/crypto/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 1fe5120..0a4fff2 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
-obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
+obj-y += xilinx/
obj-y += hisilicon/
obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
obj-y += keembay/
--
1.8.2.1
This patch adds documentation to describe Xilinx ZynqMP SHA3 driver
bindings.
Signed-off-by: Harsha <[email protected]>
---
.../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
new file mode 100644
index 0000000..45a8022
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-sha3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP SHA3 Hardware Accelerator Device Tree Bindings
+
+maintainers:
+ - Harsha Harsha<[email protected]>
+
+description: |
+ The ZynqMP SHA3 hardened cryptographic accelerator is used to
+ calculate the SHA3 hash for the given user data.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-sha3-384
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ xlnx_sha3_384: sha3-384 {
+ compatible = "xlnx,zynqmp-sha3-384";
+ };
+...
--
1.8.2.1
This patch adds a SHA3 DT node for Xilinx ZynqMP SoC.
Signed-off-by: Harsha <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 74e6644..33b7ef6 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -174,6 +174,10 @@
compatible = "xlnx,zynqmp-aes";
};
+ xlnx_sha3_384: sha384 {
+ compatible = "xlnx,zynqmp-sha3-384";
+ };
+
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
--
1.8.2.1
This patch adds an entry for ZynqMP SHA3 driver in the list of
Maintainers.
Signed-off-by: Harsha <[email protected]>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0047564..73cc994 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20929,6 +20929,12 @@ T: git https://github.com/Xilinx/linux-xlnx.git
F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
F: drivers/phy/xilinx/phy-zynqmp.c
+XILINX ZYNQMP SHA3 DRIVER
+M: Harsha <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
+F: drivers/crypto/xilinx/zynqmp-sha.c
+
XILLYBUS DRIVER
M: Eli Billauer <[email protected]>
L: [email protected]
--
1.8.2.1
This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation.
The flow is
SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware ->
SHA3 HW Engine
SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing
of 2 hash requests.
Therefore, software fallback is being used for init, update, final,
export and import in the ZynqMP SHA driver
For digest, the calculation of SHA3 hash is done by the hardened
SHA3 accelerator in Xilinx ZynqMP SoC.
Signed-off-by: Harsha <[email protected]>
---
drivers/crypto/Kconfig | 10 ++
drivers/crypto/xilinx/Makefile | 1 +
drivers/crypto/xilinx/zynqmp-sha.c | 265 +++++++++++++++++++++++++++++++++++++
3 files changed, 276 insertions(+)
create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 51690e7..5df252e 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -796,6 +796,16 @@ config CRYPTO_DEV_ZYNQMP_AES
accelerator. Select this if you want to use the ZynqMP module
for AES algorithms.
+config CRYPTO_DEV_ZYNQMP_SHA3
+ bool "Support for Xilinx ZynqMP SHA3 hw accelerator"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ select CRYPTO_SHA3
+ help
+ Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
+ This driver interfaces with SHA3 hw engine.
+ Select this if you want to use the ZynqMP module
+ for SHA3 hash computation.
+
source "drivers/crypto/chelsio/Kconfig"
source "drivers/crypto/virtio/Kconfig"
diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
index 534e32d..730feff 100644
--- a/drivers/crypto/xilinx/Makefile
+++ b/drivers/crypto/xilinx/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
+obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o
diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/zynqmp-sha.c
new file mode 100644
index 0000000..c7166ef
--- /dev/null
+++ b/drivers/crypto/xilinx/zynqmp-sha.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP SHA Driver.
+ * Copyright (c) 2021 Xilinx Inc.
+ */
+#include <asm/cacheflush.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/sha3.h>
+#include <linux/crypto.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define ZYNQMP_DMA_BIT_MASK 32U
+#define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U
+
+enum zynqmp_sha_op {
+ ZYNQMP_SHA3_INIT = 1,
+ ZYNQMP_SHA3_UPDATE = 2,
+ ZYNQMP_SHA3_FINAL = 4,
+};
+
+struct zynqmp_sha_drv_ctx {
+ struct shash_alg sha3_384;
+ struct device *dev;
+};
+
+struct zynqmp_sha_tfm_ctx {
+ struct device *dev;
+ struct crypto_shash *fbk_tfm;
+};
+
+struct zynqmp_sha_desc_ctx {
+ struct shash_desc fbk_req;
+};
+
+static dma_addr_t update_dma_addr, final_dma_addr;
+static char *ubuf, *fbuf;
+
+static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
+{
+ const char *fallback_driver_name = crypto_shash_alg_name(hash);
+ struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+ struct shash_alg *alg = crypto_shash_alg(hash);
+ struct crypto_shash *fallback_tfm;
+ struct zynqmp_sha_drv_ctx *drv_ctx;
+
+ drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
+ tfm_ctx->dev = drv_ctx->dev;
+
+ /* Allocate a fallback and abort if it failed. */
+ fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
+ CRYPTO_ALG_NEED_FALLBACK);
+ if (IS_ERR(fallback_tfm))
+ return PTR_ERR(fallback_tfm);
+
+ tfm_ctx->fbk_tfm = fallback_tfm;
+ hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
+
+ return 0;
+}
+
+static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
+{
+ struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+
+ if (tfm_ctx->fbk_tfm) {
+ crypto_free_shash(tfm_ctx->fbk_tfm);
+ tfm_ctx->fbk_tfm = NULL;
+ }
+
+ memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
+}
+
+static int zynqmp_sha_init(struct shash_desc *desc)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+ struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+ dctx->fbk_req.tfm = tctx->fbk_tfm;
+ return crypto_shash_init(&dctx->fbk_req);
+}
+
+static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_update(&dctx->fbk_req, data, length);
+}
+
+static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_final(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_finup(&dctx->fbk_req, data, length, out);
+}
+
+static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+ struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+ dctx->fbk_req.tfm = tctx->fbk_tfm;
+ return crypto_shash_import(&dctx->fbk_req, in);
+}
+
+static int zynqmp_sha_export(struct shash_desc *desc, void *out)
+{
+ struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ return crypto_shash_export(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
+{
+ int remaining_len = len;
+ int update_size;
+ int ret;
+
+ ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
+ if (ret)
+ return ret;
+
+ while (remaining_len != 0) {
+ memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
+ if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
+ update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+ remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+ } else {
+ update_size = remaining_len;
+ remaining_len = 0;
+ }
+ memcpy(ubuf, data, update_size);
+ flush_icache_user_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
+ ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
+ if (ret)
+ return ret;
+
+ data += update_size;
+ }
+
+ ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
+ memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
+ memset(fbuf, 0, SHA3_384_DIGEST_SIZE);
+
+ return ret;
+}
+
+static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
+ .sha3_384 = {
+ .init = zynqmp_sha_init,
+ .update = zynqmp_sha_update,
+ .final = zynqmp_sha_final,
+ .finup = zynqmp_sha_finup,
+ .digest = zynqmp_sha_digest,
+ .export = zynqmp_sha_export,
+ .import = zynqmp_sha_import,
+ .init_tfm = zynqmp_sha_init_tfm,
+ .exit_tfm = zynqmp_sha_exit_tfm,
+ .descsize = sizeof(struct zynqmp_sha_desc_ctx),
+ .statesize = sizeof(struct sha3_state),
+ .digestsize = SHA3_384_DIGEST_SIZE,
+ .base = {
+ .cra_name = "sha3-384",
+ .cra_driver_name = "zynqmp-sha3-384",
+ .cra_priority = 300,
+ .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_NEED_FALLBACK,
+ .cra_blocksize = SHA3_384_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
+ .cra_alignmask = 3,
+ .cra_module = THIS_MODULE,
+ }
+ }
+};
+
+static int zynqmp_sha_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int err;
+
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
+ if (err < 0) {
+ dev_err(dev, "No usable DMA configuration\n");
+ return err;
+ }
+
+ err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
+ if (err < 0) {
+ dev_err(dev, "Failed to register shash alg.\n");
+ return err;
+ }
+
+ sha3_drv_ctx.dev = dev;
+ platform_set_drvdata(pdev, &sha3_drv_ctx);
+
+ ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
+ if (!ubuf) {
+ err = -ENOMEM;
+ goto err_shash;
+ }
+
+ fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
+ if (!fbuf) {
+ err = -ENOMEM;
+ goto err_mem;
+ }
+
+ return 0;
+
+err_mem:
+ dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+
+err_shash:
+ crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+ return err;
+}
+
+static int zynqmp_sha_remove(struct platform_device *pdev)
+{
+ sha3_drv_ctx.dev = platform_get_drvdata(pdev);
+
+ dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+ dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
+ crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+ return 0;
+}
+
+static const struct of_device_id zynqmp_sha_dt_ids[] = {
+ { .compatible = "xlnx,zynqmp-sha3-384" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, zynqmp_sha_dt_ids);
+
+static struct platform_driver zynqmp_sha_driver = {
+ .probe = zynqmp_sha_probe,
+ .remove = zynqmp_sha_remove,
+ .driver = {
+ .name = "zynqmp-sha3-384",
+ .of_match_table = of_match_ptr(zynqmp_sha_dt_ids),
+ },
+};
+
+module_platform_driver(zynqmp_sha_driver);
+
+MODULE_DESCRIPTION("ZynqMP SHA3 hw acceleration support.");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Harsha <[email protected]>");
--
1.8.2.1
Hi--
On 11/30/21 00:54, Harsha wrote:
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 51690e7..5df252e 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -796,6 +796,16 @@ config CRYPTO_DEV_ZYNQMP_AES
> accelerator. Select this if you want to use the ZynqMP module
> for AES algorithms.
>
> +config CRYPTO_DEV_ZYNQMP_SHA3
> + bool "Support for Xilinx ZynqMP SHA3 hw accelerator"
s/hw/hardware/
> + depends on ARCH_ZYNQMP || COMPILE_TEST
> + select CRYPTO_SHA3
> + help
> + Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
> + This driver interfaces with SHA3 hw engine.
s/hw/hardware/
> + Select this if you want to use the ZynqMP module
> + for SHA3 hash computation.
thanks.
--
~Randy
Hi Randy,
Thanks for reviewing the patch. I will make the following changes:
- ZynqMP SHA3 hw accelerator -> ZynqMP SHA3 hardware accelerator
- SHA3 hw engine -> SHA3 hardware engine
Regards,
Harsha
> -----Original Message-----
> From: Randy Dunlap <[email protected]>
> Sent: Tuesday, November 30, 2021 7:44 PM
> To: Harsha Harsha <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; Michal Simek <[email protected]>; [email protected]; [email protected];
> [email protected]
> Cc: Sarat Chand Savitala <[email protected]>; Harsh Jain <[email protected]>
> Subject: Re: [RFC PATCH 5/6] crypto: xilinx: Add Xilinx SHA3 driver
>
> Hi--
>
> On 11/30/21 00:54, Harsha wrote:
> > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> > index 51690e7..5df252e 100644
> > --- a/drivers/crypto/Kconfig
> > +++ b/drivers/crypto/Kconfig
> > @@ -796,6 +796,16 @@ config CRYPTO_DEV_ZYNQMP_AES
> > accelerator. Select this if you want to use the ZynqMP module
> > for AES algorithms.
> >
> > +config CRYPTO_DEV_ZYNQMP_SHA3
> > + bool "Support for Xilinx ZynqMP SHA3 hw accelerator"
>
> s/hw/hardware/
>
> > + depends on ARCH_ZYNQMP || COMPILE_TEST
> > + select CRYPTO_SHA3
> > + help
> > + Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
> > + This driver interfaces with SHA3 hw engine.
>
> s/hw/hardware/
>
> > + Select this if you want to use the ZynqMP module
> > + for SHA3 hash computation.
>
> thanks.
> --
> ~Randy
On 11/29/21 20:20, Harsha wrote:
> This patch updates the Makefile for xilinx subdirectory.
> Currently the xilinx subdirectory includes only zynqmp-aes-gcm.c.
> Since this patch series adds zynqmp-sha.c in the xilinx subdirectory,
> so the Makefile needs to be updated.
You should change this description.
CONFIG_CRYPTO_DEV_ZYNQMP_AES protects zynqmp-aes-gcm.o and it is used
twice and it is enough to use it once.
>
> Signed-off-by: Harsha <[email protected]>
> ---
> drivers/crypto/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index 1fe5120..0a4fff2 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -47,7 +47,7 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
> obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
> obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
> obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
> -obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
> +obj-y += xilinx/
> obj-y += hisilicon/
> obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
> obj-y += keembay/
>
This should be regular patch not just RFC. When this is fixed feel free
to add my
Reviewed-by: Michal Simek <[email protected]>
Thanks,
Michal
On 11/29/21 20:20, Harsha wrote:
> This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
> SHA3 hash of given data.
>
> Signed-off-by: Harsha <[email protected]>
> ---
> drivers/firmware/xilinx/zynqmp.c | 26 ++++++++++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 3dd45a7..a84c5ea 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -1117,6 +1117,32 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
> EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
>
> /**
> + * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
> + * @address: Address of the data/ Address of output buffer where
> + * hash should be stored.
> + * @size: Size of the data.
> + * @flags:
> + * BIT(0) - for initializing csudma driver and SHA3(Here address
> + * and size inputs can be NULL).
> + * BIT(1) - to call Sha3_Update API which can be called multiple
> + * times when data is not contiguous.
> + * BIT(2) - to get final hash of the whole updated data.
> + * Hash will be overwritten at provided address with
> + * 48 bytes.
> + *
> + * Return: Returns status, either success or error code.
> + */
> +int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
> +{
> + u32 lower_addr = lower_32_bits(address);
> + u32 upper_addr = upper_32_bits(address);
> +
> + return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,
> + size, flags, NULL);
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
> +
> +/**
> * zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart
> * @type: Shutdown or restart? 0 for shutdown, 1 for restart
> * @subtype: Specifies which system should be restarted or shut down
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 47fd4e5..38ef708 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -78,6 +78,7 @@ enum pm_api_id {
> PM_FPGA_LOAD = 22,
> PM_FPGA_GET_STATUS = 23,
> PM_GET_CHIPID = 24,
> + PM_SECURE_SHA = 26,
> PM_PINCTRL_REQUEST = 28,
> PM_PINCTRL_RELEASE = 29,
> PM_PINCTRL_GET_FUNCTION = 30,
> @@ -410,6 +411,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
> const u32 qos,
> const enum zynqmp_pm_request_ack ack);
> int zynqmp_pm_aes_engine(const u64 address, u32 *out);
> +int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
> int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
> int zynqmp_pm_fpga_get_status(u32 *value);
> int zynqmp_pm_write_ggs(u32 index, u32 value);
> @@ -581,6 +583,12 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
> return -ENODEV;
> }
>
> +static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
> + const u32 flags)
> +{
> + return -ENODEV;
> +}
> +
> static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
> const u32 flags)
> {
>
Acked-by: Michal Simek <[email protected]>
Thanks,
Michal
On 11/29/21 20:20, Harsha wrote:
> This patch adds a SHA3 DT node for Xilinx ZynqMP SoC.
>
> Signed-off-by: Harsha <[email protected]>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 74e6644..33b7ef6 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -174,6 +174,10 @@
> compatible = "xlnx,zynqmp-aes";
> };
>
> + xlnx_sha3_384: sha384 {
> + compatible = "xlnx,zynqmp-sha3-384";
> + };
> +
> zynqmp_reset: reset-controller {
> compatible = "xlnx,zynqmp-reset";
> #reset-cells = <1>;
>
I will let Rob to comment this but I think this can be discovered and
there is no need to link it with any device now. That's why maybe the
whole dt binding is not needed at all.
Thanks,
Michal
On Tue, Nov 30, 2021 at 02:24:22PM +0530, Harsha wrote:
> This patch adds documentation to describe Xilinx ZynqMP SHA3 driver
> bindings.
>
> Signed-off-by: Harsha <[email protected]>
> ---
> .../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
>
> diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> new file mode 100644
> index 0000000..45a8022
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-sha3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP SHA3 Hardware Accelerator Device Tree Bindings
> +
> +maintainers:
> + - Harsha Harsha<[email protected]>
space ^
> +
> +description: |
Don't need '|' if no formatting to preserve.
> + The ZynqMP SHA3 hardened cryptographic accelerator is used to
> + calculate the SHA3 hash for the given user data.
> +
> +properties:
> + compatible:
> + const: xlnx,zynqmp-sha3-384
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + xlnx_sha3_384: sha3-384 {
crypto {
> + compatible = "xlnx,zynqmp-sha3-384";
You need some way to access this h/w.
> + };
> +...
> --
> 1.8.2.1
>
>
Hi Rob,
Thanks for your review.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Wednesday, December 8, 2021 3:00 AM
> To: Harsha Harsha <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Michal
> Simek <[email protected]>; [email protected]; [email protected]; Sarat Chand Savitala
> <[email protected]>; Harsh Jain <[email protected]>
> Subject: Re: [RFC PATCH 3/6] dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver
>
> On Tue, Nov 30, 2021 at 02:24:22PM +0530, Harsha wrote:
> > This patch adds documentation to describe Xilinx ZynqMP SHA3 driver
> > bindings.
> >
> > Signed-off-by: Harsha <[email protected]>
> > ---
> > .../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 ++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > new file mode 100644
> > index 0000000..45a8022
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > @@ -0,0 +1,30 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-sha3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx ZynqMP SHA3 Hardware Accelerator Device Tree Bindings
> > +
> > +maintainers:
> > + - Harsha Harsha<[email protected]>
>
> space ^
Accepted. Will remove space in next version of patch series.
>
> > +
> > +description: |
>
> Don't need '|' if no formatting to preserve.
Accepted. Will remove | in next version of patch series.
>
> > + The ZynqMP SHA3 hardened cryptographic accelerator is used to
> > + calculate the SHA3 hash for the given user data.
> > +
> > +properties:
> > + compatible:
> > + const: xlnx,zynqmp-sha3-384
> > +
> > +required:
> > + - compatible
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + xlnx_sha3_384: sha3-384 {
>
> crypto {
>
> > + compatible = "xlnx,zynqmp-sha3-384";
>
> You need some way to access this h/w.
Accepted. Will add required details similar to https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/tree/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
>
> > + };
> > +...
> > --
> > 1.8.2.1
> >
> >
Regards,
Harsha
On Tue, Dec 7, 2021 at 10:17 PM Harsha Harsha <[email protected]> wrote:
>
> Hi Rob,
>
> Thanks for your review.
>
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: Wednesday, December 8, 2021 3:00 AM
> > To: Harsha Harsha <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Michal
> > Simek <[email protected]>; [email protected]; [email protected]; Sarat Chand Savitala
> > <[email protected]>; Harsh Jain <[email protected]>
> > Subject: Re: [RFC PATCH 3/6] dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver
> >
> > On Tue, Nov 30, 2021 at 02:24:22PM +0530, Harsha wrote:
> > > This patch adds documentation to describe Xilinx ZynqMP SHA3 driver
> > > bindings.
> > >
> > > Signed-off-by: Harsha <[email protected]>
> > > ---
> > > .../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 ++++++++++++++++++++++
> > > 1 file changed, 30 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > new file mode 100644
> > > index 0000000..45a8022
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > @@ -0,0 +1,30 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-sha3.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Xilinx ZynqMP SHA3 Hardware Accelerator Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Harsha Harsha<[email protected]>
> >
> > space ^
>
> Accepted. Will remove space in next version of patch series.
>
> >
> > > +
> > > +description: |
> >
> > Don't need '|' if no formatting to preserve.
>
> Accepted. Will remove | in next version of patch series.
>
> >
> > > + The ZynqMP SHA3 hardened cryptographic accelerator is used to
> > > + calculate the SHA3 hash for the given user data.
> > > +
> > > +properties:
> > > + compatible:
> > > + const: xlnx,zynqmp-sha3-384
> > > +
> > > +required:
> > > + - compatible
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + xlnx_sha3_384: sha3-384 {
> >
> > crypto {
> >
> > > + compatible = "xlnx,zynqmp-sha3-384";
> >
> > You need some way to access this h/w.
>
> Accepted. Will add required details similar to https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/tree/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
Why do you need a node for each crypto algorithm? Can't your firmware
tell you what algorithms it supports? Worst case, try each possible
one and see what fails or not. None of this needs to be in DT.
Rob
Hi Rob,
Thanks for your review. Please find my reply inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Wednesday, December 8, 2021 10:42 PM
> To: Harsha Harsha <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Michal
> Simek <[email protected]>; [email protected]; [email protected]; Sarat Chand Savitala
> <[email protected]>; Harsh Jain <[email protected]>
> Subject: Re: [RFC PATCH 3/6] dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver
>
> On Tue, Dec 7, 2021 at 10:17 PM Harsha Harsha <[email protected]> wrote:
> >
> > Hi Rob,
> >
> > Thanks for your review.
> >
> >
> > > -----Original Message-----
> > > From: Rob Herring <[email protected]>
> > > Sent: Wednesday, December 8, 2021 3:00 AM
> > > To: Harsha Harsha <[email protected]>
> > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Michal
> > > Simek <[email protected]>; [email protected]; [email protected]; Sarat Chand Savitala
> > > <[email protected]>; Harsh Jain <[email protected]>
> > > Subject: Re: [RFC PATCH 3/6] dt-bindings: crypto: Add bindings for ZynqMP SHA3 driver
> > >
> > > On Tue, Nov 30, 2021 at 02:24:22PM +0530, Harsha wrote:
> > > > This patch adds documentation to describe Xilinx ZynqMP SHA3 driver
> > > > bindings.
> > > >
> > > > Signed-off-by: Harsha <[email protected]>
> > > > ---
> > > > .../bindings/crypto/xlnx,zynqmp-sha3.yaml | 30 ++++++++++++++++++++++
> > > > 1 file changed, 30 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > > new file mode 100644
> > > > index 0000000..45a8022
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-sha3.yaml
> > > > @@ -0,0 +1,30 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-sha3.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Xilinx ZynqMP SHA3 Hardware Accelerator Device Tree Bindings
> > > > +
> > > > +maintainers:
> > > > + - Harsha Harsha<[email protected]>
> > >
> > > space ^
> >
> > Accepted. Will remove space in next version of patch series.
> >
> > >
> > > > +
> > > > +description: |
> > >
> > > Don't need '|' if no formatting to preserve.
> >
> > Accepted. Will remove | in next version of patch series.
> >
> > >
> > > > + The ZynqMP SHA3 hardened cryptographic accelerator is used to
> > > > + calculate the SHA3 hash for the given user data.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: xlnx,zynqmp-sha3-384
> > > > +
> > > > +required:
> > > > + - compatible
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + xlnx_sha3_384: sha3-384 {
> > >
> > > crypto {
> > >
> > > > + compatible = "xlnx,zynqmp-sha3-384";
> > >
> > > You need some way to access this h/w.
> >
> > Accepted. Will add required details similar to https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-
> 2.6.git/tree/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
>
> Why do you need a node for each crypto algorithm? Can't your firmware
> tell you what algorithms it supports? Worst case, try each possible
> one and see what fails or not. None of this needs to be in DT.
>
Do you mean that the firmware should be self discovered and there is no
need to add any DT binding for this driver?
> Rob
Regards,
Harsha