[PATCH v1 0/3] SHA1 for PPC/SPE
The following patches add support for SIMD accelerated SHA1
calculation on PPC processors with SPE instruction set. The
implementation takes care of the following constraints:
- independant of processor endianess
- save SPE registers for interrupt context compatibility
- disable preemtion only for short intervals
Performance numbers from insmod tcrypt sec=3 mode=303 taken
on e500v2 800 MHz (TP Link WDR4900)
data per sha1-ppc this patch speedup cycles
length update bytes/sec bytes/sec factor per byte
------ ------ ----------- ----------- ------- --------
16 16 9,686,688 13,195,285 x1.36 60.63
64 16 18,769,344 21,886,122 x1.17 36.55
64 64 26,187,712 33,181,184 x1.27 24.11
256 16 27,461,120 29,614,080 x1.08 27.01
256 64 45,257,898 52,748,373 x1.17 15.17
256 256 56,050,773 68,863,061 x1.23 11.62
1024 16 30,863,360 32,438,272 x1.05 24.66
1024 256 72,531,626 85,434,709 x1.18 9.36
1024 1024 78,640,469 94,731,605 x1.20 8.44
2048 16 31,771,989 32,970,752 x1.04 24.26
2048 256 76,478,464 89,234,090 x1.17 8.97
2048 1024 83,010,218 98,902,698 x1.19 8.09
2048 2048 84,336,640 101,038,762 x1.19 7.92