SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
features to the one on S5PV210. However with minor changes the s5p-sss.c
driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
This patch set
1. Adds device tree support to the s5p-sss.c driver and Documentation
2. Adds code to support SSS module on Exynos4 and 5 SoCs
3. Adds variant struct to handle the differences in SSS modules
4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
Note: Compatible "exynos4210-secss" should work for Exynos4412 and
Exynos5260 (Exynos5260, for which ARCH code is under review)
I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
test with addition of DT node and clocks support.
These patches are under review at
https://lkml.org/lkml/2014/2/17/124
Naveen Krishna Chatradhi (7):
crypto:s5p-sss: Use platform_get_irq() instead of _byname()
crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
crypto:s5p-sss: Look for the next request in the queue
crypto:s5p-sss: Add device tree support
crypto:s5p-sss: Add support for SSS module on Exynos
crypto:s5p-sss: validate iv before memcpy
crypto:s5p-sss: Use clk_prepare/clk_unprepare
.../devicetree/bindings/crypto/samsung-sss.txt | 35 +++++
drivers/crypto/Kconfig | 6 +-
drivers/crypto/s5p-sss.c | 145 +++++++++++++++-----
3 files changed, 150 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
--
1.7.9.5
This patch adds new compatible and variant struct to support the SSS
module on Exynos4 (Exynos4210), Exynos5 (Exynos5420 and Exynos5250)
for which
1. AES register are at an offset of 0x200 and
2. hash interrupt is not available
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Change since v6:
None
Change since v5:
1. Rewritten the interrupt definition in the documentation
2. Added Reviewed-by: Tomasz Figa <[email protected]>
.../devicetree/bindings/crypto/samsung-sss.txt | 15 ++-
drivers/crypto/s5p-sss.c | 107 +++++++++++++++-----
2 files changed, 95 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
index 3876f71..1702773 100644
--- a/Documentation/devicetree/bindings/crypto/samsung-sss.txt
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -8,16 +8,25 @@ The SSS module in S5PV210 SoC supports the following:
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
-- PRNG: Pseudo Random Number Generator
+The SSS module in Exynos4 (Exynos4210) and
+Exynos5 (Exynos5420 and Exynos5250) SoCs
+supports the following also:
+-- ARCFOUR (ARC4)
+-- True Random Number Generator (TRNG)
+-- Secure Key Manager
+
Required properties:
- compatible : Should contain entries for this and backward compatible
SSS versions:
- "samsung,s5pv210-secss" for S5PV210 SoC.
+ - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
+ Exynos5260 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
- interrupts : interrupt specifiers of SSS module interrupts, should contain
- two entries:
- - first : feed control interrupt,
- - second : hash interrupt.
+ following entries:
+ - first : feed control interrupt (required for all variants),
+ - second : hash interrupt (required only for samsung,s5pv210-secss).
- clocks : list of clock phandle and specifier pairs for all clocks listed in
clock-names property.
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index c6aafe8..37e0598 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -106,7 +106,7 @@
#define SSS_REG_FCPKDMAO 0x005C
/* AES registers */
-#define SSS_REG_AES_CONTROL 0x4000
+#define SSS_REG_AES_CONTROL 0x00
#define SSS_AES_BYTESWAP_DI _BIT(11)
#define SSS_AES_BYTESWAP_DO _BIT(10)
#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -122,21 +122,25 @@
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
#define SSS_AES_MODE_DECRYPT _BIT(0)
-#define SSS_REG_AES_STATUS 0x4004
+#define SSS_REG_AES_STATUS 0x04
#define SSS_AES_BUSY _BIT(2)
#define SSS_AES_INPUT_READY _BIT(1)
#define SSS_AES_OUTPUT_READY _BIT(0)
-#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2))
-#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2))
-#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2))
-#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2))
-#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2))
+#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
+#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
+#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
+#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
+#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
+#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
+#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
+ SSS_AES_REG(dev, reg))
+
/* HW engine modes */
#define FLAGS_AES_DECRYPT _BIT(0)
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -146,6 +150,20 @@
#define AES_KEY_LEN 16
#define CRYPTO_QUEUE_LEN 1
+/**
+ * struct samsung_aes_variant - platform specific SSS driver data
+ * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
+ * @aes_offset: AES register offset from SSS module's base.
+ *
+ * Specifies platform specific configuration of SSS module.
+ * Note: A structure for driver specific platform data is used for future
+ * expansion of its usage.
+ */
+struct samsung_aes_variant {
+ bool has_hash_irq;
+ unsigned int aes_offset;
+};
+
struct s5p_aes_reqctx {
unsigned long mode;
};
@@ -162,6 +180,7 @@ struct s5p_aes_dev {
struct device *dev;
struct clk *clk;
void __iomem *ioaddr;
+ void __iomem *aes_ioaddr;
int irq_hash;
int irq_fc;
@@ -174,16 +193,48 @@ struct s5p_aes_dev {
struct crypto_queue queue;
bool busy;
spinlock_t lock;
+
+ struct samsung_aes_variant *variant;
};
static struct s5p_aes_dev *s5p_dev;
+static const struct samsung_aes_variant s5p_aes_data = {
+ .has_hash_irq = true,
+ .aes_offset = 0x4000,
+};
+
+static const struct samsung_aes_variant exynos_aes_data = {
+ .has_hash_irq = false,
+ .aes_offset = 0x200,
+};
+
static const struct of_device_id s5p_sss_dt_match[] = {
- { .compatible = "samsung,s5pv210-secss" },
+ {
+ .compatible = "samsung,s5pv210-secss",
+ .data = &s5p_aes_data,
+ },
+ {
+ .compatible = "samsung,exynos4210-secss",
+ .data = &exynos_aes_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+static inline struct samsung_aes_variant *find_s5p_sss_version
+ (struct platform_device *pdev)
+{
+ if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
+ const struct of_device_id *match;
+ match = of_match_node(s5p_sss_dt_match,
+ pdev->dev.of_node);
+ return (struct samsung_aes_variant *)match->data;
+ }
+ return (struct samsung_aes_variant *)
+ platform_get_device_id(pdev)->driver_data;
+}
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -329,14 +380,14 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
{
void __iomem *keystart;
- memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
if (keylen == AES_KEYSIZE_256)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
else if (keylen == AES_KEYSIZE_192)
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
else
- keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4);
+ keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
memcpy(keystart, key, keylen);
}
@@ -386,7 +437,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
if (err)
goto outdata_error;
- SSS_WRITE(dev, AES_CONTROL, aes_control);
+ SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
s5p_set_dma_indata(dev, req->src);
@@ -571,6 +622,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
struct s5p_aes_dev *pdata;
struct device *dev = &pdev->dev;
struct resource *res;
+ struct samsung_aes_variant *variant;
if (s5p_dev)
return -EEXIST;
@@ -584,6 +636,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
if (IS_ERR(pdata->ioaddr))
return PTR_ERR(pdata->ioaddr);
+ variant = find_s5p_sss_version(pdev);
+
pdata->clk = devm_clk_get(dev, "secss");
if (IS_ERR(pdata->clk)) {
dev_err(dev, "failed to find secss clock source\n");
@@ -594,6 +648,8 @@ static int s5p_aes_probe(struct platform_device *pdev)
spin_lock_init(&pdata->lock);
+ pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
+
pdata->irq_fc = platform_get_irq(pdev, 0);
if (pdata->irq_fc < 0) {
err = pdata->irq_fc;
@@ -607,19 +663,22 @@ static int s5p_aes_probe(struct platform_device *pdev)
goto err_irq;
}
- pdata->irq_hash = platform_get_irq(pdev, 1);
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
- }
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
- IRQF_SHARED, pdev->name, pdev);
- if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
- goto err_irq;
+ if (variant->has_hash_irq) {
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ IRQF_SHARED, pdev->name, pdev);
+ if (err < 0) {
+ dev_warn(dev, "hash interrupt is not available.\n");
+ goto err_irq;
+ }
}
+ pdata->variant = variant;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
s5p_dev = pdata;
--
1.7.9.5
This patch modifies Kconfig such that ARCH_EXYNOS SoCs
which includes (Exynos4210, Exynos5250 and Exynos5420)
can also select Samsung SSS(Security SubSystem) driver.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Change since v6:
None
Change since v5:
None
drivers/crypto/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 03ccdb0..f066fa2 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -301,14 +301,14 @@ config CRYPTO_DEV_SAHARA
found in some Freescale i.MX chips.
config CRYPTO_DEV_S5P
- tristate "Support for Samsung S5PV210 crypto accelerator"
- depends on ARCH_S5PV210
+ tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
+ depends on ARCH_S5PV210 || ARCH_EXYNOS
select CRYPTO_AES
select CRYPTO_ALGAPI
select CRYPTO_BLKCIPHER
help
This option allows you to have support for S5P crypto acceleration.
- Select this to offload Samsung S5PV210 or S5PC110 from AES
+ Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.
config CRYPTO_DEV_NX
--
1.7.9.5
This patch set adds use of clk_prepare/clk_unprepare as
required by generic clock framework.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Changes since v6:
None
drivers/crypto/s5p-sss.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 0ffc042..ea7d478 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -645,7 +645,11 @@ static int s5p_aes_probe(struct platform_device *pdev)
return -ENOENT;
}
- clk_enable(pdata->clk);
+ err = clk_prepare_enable(pdata->clk);
+ if (err < 0) {
+ dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
+ return err;
+ }
spin_lock_init(&pdata->lock);
@@ -706,7 +710,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
tasklet_kill(&pdata->tasklet);
err_irq:
- clk_disable(pdata->clk);
+ clk_disable_unprepare(pdata->clk);
s5p_dev = NULL;
@@ -726,7 +730,7 @@ static int s5p_aes_remove(struct platform_device *pdev)
tasklet_kill(&pdata->tasklet);
- clk_disable(pdata->clk);
+ clk_disable_unprepare(pdata->clk);
s5p_dev = NULL;
--
1.7.9.5
Currently, the driver enqueues a request only if the busy bit is
false. And every request initiates a dequeue. If 2 requests arrive
simultaneously, only one of them will be dequeued.
To avoid this senario, we will enqueue the next request irrespective
of the system condition (that is what queue is here for). Also
schedule at a tasklet immediatly after the current request is done.
The tasklet will dequeue the next request in the queue, giving
continuous loop. tasklet will exit if there are no requests in the
queue.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Changes since v6:
None
drivers/crypto/s5p-sss.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index ea7d478..47c568e 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -330,8 +330,12 @@ static void s5p_aes_tx(struct s5p_aes_dev *dev)
}
s5p_set_dma_outdata(dev, dev->sg_dst);
- } else
+ } else {
s5p_aes_complete(dev, err);
+
+ dev->busy = true;
+ tasklet_schedule(&dev->tasklet);
+ }
}
static void s5p_aes_rx(struct s5p_aes_dev *dev)
@@ -469,10 +473,13 @@ static void s5p_tasklet_cb(unsigned long data)
spin_lock_irqsave(&dev->lock, flags);
backlog = crypto_get_backlog(&dev->queue);
async_req = crypto_dequeue_request(&dev->queue);
- spin_unlock_irqrestore(&dev->lock, flags);
- if (!async_req)
+ if (!async_req) {
+ dev->busy = false;
+ spin_unlock_irqrestore(&dev->lock, flags);
return;
+ }
+ spin_unlock_irqrestore(&dev->lock, flags);
if (backlog)
backlog->complete(backlog, -EINPROGRESS);
@@ -491,14 +498,13 @@ static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
int err;
spin_lock_irqsave(&dev->lock, flags);
+ err = ablkcipher_enqueue_request(&dev->queue, req);
if (dev->busy) {
- err = -EAGAIN;
spin_unlock_irqrestore(&dev->lock, flags);
goto exit;
}
dev->busy = true;
- err = ablkcipher_enqueue_request(&dev->queue, req);
spin_unlock_irqrestore(&dev->lock, flags);
tasklet_schedule(&dev->tasklet);
@@ -683,6 +689,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
}
}
+ pdata->busy = false;
pdata->variant = variant;
pdata->dev = dev;
platform_set_drvdata(pdev, pdata);
--
1.7.9.5
This patch adds code to validate "iv" buffer before trying to
memcpy the contents
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Changes since v6:
None
drivers/crypto/s5p-sss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 37e0598..0ffc042 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -380,7 +380,8 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
{
void __iomem *keystart;
- memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
+ if (iv)
+ memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
if (keylen == AES_KEYSIZE_256)
keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
--
1.7.9.5
This patch adds device tree support to the s5p-sss.c crypto driver.
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Changes since v6:
None
Changes since v5:
Rewritten the interrupt definition in the documentation
.../devicetree/bindings/crypto/samsung-sss.txt | 26 ++++++++++++++++++++
drivers/crypto/s5p-sss.c | 8 ++++++
2 files changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 0000000..3876f71
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,26 @@
+Samsung SoC SSS (Security SubSystem) module
+
+The SSS module in S5PV210 SoC supports the following:
+-- Feeder (FeedCtrl)
+-- Advanced Encryption Standard (AES)
+-- Data Encryption Standard (DES)/3DES
+-- Public Key Accelerator (PKA)
+-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
+-- PRNG: Pseudo Random Number Generator
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SSS versions:
+ - "samsung,s5pv210-secss" for S5PV210 SoC.
+- reg : Offset and length of the register set for the module
+- interrupts : interrupt specifiers of SSS module interrupts, should contain
+ two entries:
+ - first : feed control interrupt,
+ - second : hash interrupt.
+
+- clocks : list of clock phandle and specifier pairs for all clocks listed in
+ clock-names property.
+- clock-names : list of device clock input names; should contain one entry
+ "secss".
+
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 2876fa3..c6aafe8 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/crypto.h>
#include <linux/interrupt.h>
@@ -177,6 +178,12 @@ struct s5p_aes_dev {
static struct s5p_aes_dev *s5p_dev;
+static const struct of_device_id s5p_sss_dt_match[] = {
+ { .compatible = "samsung,s5pv210-secss" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
+
static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
{
SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -672,6 +679,7 @@ static struct platform_driver s5p_aes_crypto = {
.driver = {
.owner = THIS_MODULE,
.name = "s5p-secss",
+ .of_match_table = s5p_sss_dt_match,
},
};
--
1.7.9.5
This patch uses the platform_get_irq() instead of the
platform_get_irq_byname(). Making feeder control interrupt
as resource "0" and hash interrupt as "1".
reasons for this change.
1. Cannot find any Arch which is currently using this driver
2. Samsung Exynos4 and 5 SoCs only use the feeder control interrupt
3. Patches adding support for DT and H/W version are in pipeline
Signed-off-by: Naveen Krishna Chatradhi <[email protected]>
Reviewed-by: Tomasz Figa <[email protected]>
Acked-by: Herbert Xu <[email protected]>
CC: David S. Miller <[email protected]>
CC: Vladimir Zapolskiy <[email protected]>
TO: <[email protected]>
CC: <[email protected]>
---
Changes since v7:
Added Acked-by from Herbert Xu
Changes since v6:
None
Changes since v5:
None
drivers/crypto/s5p-sss.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index be45762..2876fa3 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -587,29 +587,29 @@ static int s5p_aes_probe(struct platform_device *pdev)
spin_lock_init(&pdata->lock);
- pdata->irq_hash = platform_get_irq_byname(pdev, "hash");
- if (pdata->irq_hash < 0) {
- err = pdata->irq_hash;
- dev_warn(dev, "hash interrupt is not available.\n");
+ pdata->irq_fc = platform_get_irq(pdev, 0);
+ if (pdata->irq_fc < 0) {
+ err = pdata->irq_fc;
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "hash interrupt is not available.\n");
+ dev_warn(dev, "feed control interrupt is not available.\n");
goto err_irq;
}
- pdata->irq_fc = platform_get_irq_byname(pdev, "feed control");
- if (pdata->irq_fc < 0) {
- err = pdata->irq_fc;
- dev_warn(dev, "feed control interrupt is not available.\n");
+ pdata->irq_hash = platform_get_irq(pdev, 1);
+ if (pdata->irq_hash < 0) {
+ err = pdata->irq_hash;
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
- err = devm_request_irq(dev, pdata->irq_fc, s5p_aes_interrupt,
+ err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
IRQF_SHARED, pdev->name, pdev);
if (err < 0) {
- dev_warn(dev, "feed control interrupt is not available.\n");
+ dev_warn(dev, "hash interrupt is not available.\n");
goto err_irq;
}
--
1.7.9.5
Hello All,
On 28 April 2014 16:14, Naveen Krishna Chatradhi <[email protected]> wrote:
> SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
> features to the one on S5PV210. However with minor changes the s5p-sss.c
> driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
>
> This patch set
> 1. Adds device tree support to the s5p-sss.c driver and Documentation
> 2. Adds code to support SSS module on Exynos4 and 5 SoCs
> 3. Adds variant struct to handle the differences in SSS modules
> 4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
>
> Note: Compatible "exynos4210-secss" should work for Exynos4412 and
> Exynos5260 (Exynos5260, for which ARCH code is under review)
> I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
> test with addition of DT node and clocks support.
>
> These patches are under review at
> https://lkml.org/lkml/2014/2/17/124
>
> Naveen Krishna Chatradhi (7):
> crypto:s5p-sss: Use platform_get_irq() instead of _byname()
> crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
> crypto:s5p-sss: Look for the next request in the queue
> crypto:s5p-sss: Add device tree support
> crypto:s5p-sss: Add support for SSS module on Exynos
> crypto:s5p-sss: validate iv before memcpy
> crypto:s5p-sss: Use clk_prepare/clk_unprepare
>
> .../devicetree/bindings/crypto/samsung-sss.txt | 35 +++++
> drivers/crypto/Kconfig | 6 +-
> drivers/crypto/s5p-sss.c | 145 +++++++++++++++-----
> 3 files changed, 150 insertions(+), 36 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
Can we get this series merged in.
Its has got reviewed and re-based several times and got acked by a
couple of seniors.
Thanks,
>
> --
> 1.7.9.5
>
--
Shine bright,
(: Nav :)
On Wed, Apr 30, 2014 at 04:38:05PM +0530, Naveen Krishna Ch wrote:
> Hello All,
>
> On 28 April 2014 16:14, Naveen Krishna Chatradhi <[email protected]> wrote:
> > SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
> > features to the one on S5PV210. However with minor changes the s5p-sss.c
> > driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
> >
> > This patch set
> > 1. Adds device tree support to the s5p-sss.c driver and Documentation
> > 2. Adds code to support SSS module on Exynos4 and 5 SoCs
> > 3. Adds variant struct to handle the differences in SSS modules
> > 4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
> >
> > Note: Compatible "exynos4210-secss" should work for Exynos4412 and
> > Exynos5260 (Exynos5260, for which ARCH code is under review)
> > I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
> > test with addition of DT node and clocks support.
> >
> > These patches are under review at
> > https://lkml.org/lkml/2014/2/17/124
> >
> > Naveen Krishna Chatradhi (7):
> > crypto:s5p-sss: Use platform_get_irq() instead of _byname()
> > crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
> > crypto:s5p-sss: Look for the next request in the queue
> > crypto:s5p-sss: Add device tree support
> > crypto:s5p-sss: Add support for SSS module on Exynos
> > crypto:s5p-sss: validate iv before memcpy
> > crypto:s5p-sss: Use clk_prepare/clk_unprepare
> >
> > .../devicetree/bindings/crypto/samsung-sss.txt | 35 +++++
> > drivers/crypto/Kconfig | 6 +-
> > drivers/crypto/s5p-sss.c | 145 +++++++++++++++-----
> > 3 files changed, 150 insertions(+), 36 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>
> Can we get this series merged in.
> Its has got reviewed and re-based several times and got acked by a
> couple of seniors.
Do you want me to pick these series up?
Cheers,
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Hello Herbert,
On 30 April 2014 17:44, Herbert Xu <[email protected]> wrote:
> On Wed, Apr 30, 2014 at 04:38:05PM +0530, Naveen Krishna Ch wrote:
>> Hello All,
>>
>> On 28 April 2014 16:14, Naveen Krishna Chatradhi <[email protected]> wrote:
>> > SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
>> > features to the one on S5PV210. However with minor changes the s5p-sss.c
>> > driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
>> >
>> > This patch set
>> > 1. Adds device tree support to the s5p-sss.c driver and Documentation
>> > 2. Adds code to support SSS module on Exynos4 and 5 SoCs
>> > 3. Adds variant struct to handle the differences in SSS modules
>> > 4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
>> >
>> > Note: Compatible "exynos4210-secss" should work for Exynos4412 and
>> > Exynos5260 (Exynos5260, for which ARCH code is under review)
>> > I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
>> > test with addition of DT node and clocks support.
>> >
>> > These patches are under review at
>> > https://lkml.org/lkml/2014/2/17/124
>> >
>> > Naveen Krishna Chatradhi (7):
>> > crypto:s5p-sss: Use platform_get_irq() instead of _byname()
>> > crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
>> > crypto:s5p-sss: Look for the next request in the queue
>> > crypto:s5p-sss: Add device tree support
>> > crypto:s5p-sss: Add support for SSS module on Exynos
>> > crypto:s5p-sss: validate iv before memcpy
>> > crypto:s5p-sss: Use clk_prepare/clk_unprepare
>> >
>> > .../devicetree/bindings/crypto/samsung-sss.txt | 35 +++++
>> > drivers/crypto/Kconfig | 6 +-
>> > drivers/crypto/s5p-sss.c | 145 +++++++++++++++-----
>> > 3 files changed, 150 insertions(+), 36 deletions(-)
>> > create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>
>> Can we get this series merged in.
>> Its has got reviewed and re-based several times and got acked by a
>> couple of seniors.
>
> Do you wa1nt me to pick these series up?
Yes please.
>
> Cheers,
Thanks,
Naveen
> --
> Email: Herbert Xu <[email protected]>
> Home Page: http://gondor.apana.org.au/~herbert/
> PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
--
Shine bright,
(: Nav :)
Hi Naveen, Herbert,
On 04/30/14 15:14, Herbert Xu wrote:
> On Wed, Apr 30, 2014 at 04:38:05PM +0530, Naveen Krishna Ch wrote:
>> Hello All,
>>
>> On 28 April 2014 16:14, Naveen Krishna Chatradhi<[email protected]> wrote:
>>> SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
>>> features to the one on S5PV210. However with minor changes the s5p-sss.c
>>> driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
>>>
>>> This patch set
>>> 1. Adds device tree support to the s5p-sss.c driver and Documentation
>>> 2. Adds code to support SSS module on Exynos4 and 5 SoCs
>>> 3. Adds variant struct to handle the differences in SSS modules
>>> 4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
>>>
>>> Note: Compatible "exynos4210-secss" should work for Exynos4412 and
>>> Exynos5260 (Exynos5260, for which ARCH code is under review)
>>> I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
>>> test with addition of DT node and clocks support.
>>>
>>> These patches are under review at
>>> https://lkml.org/lkml/2014/2/17/124
>>>
>>> Naveen Krishna Chatradhi (7):
>>> crypto:s5p-sss: Use platform_get_irq() instead of _byname()
>>> crypto:s5p-sss: Kconfig: Let Exynos SoCs select SSS driver
>>> crypto:s5p-sss: Look for the next request in the queue
>>> crypto:s5p-sss: Add device tree support
>>> crypto:s5p-sss: Add support for SSS module on Exynos
>>> crypto:s5p-sss: validate iv before memcpy
>>> crypto:s5p-sss: Use clk_prepare/clk_unprepare
>>>
>>> .../devicetree/bindings/crypto/samsung-sss.txt | 35 +++++
>>> drivers/crypto/Kconfig | 6 +-
>>> drivers/crypto/s5p-sss.c | 145 +++++++++++++++-----
>>> 3 files changed, 150 insertions(+), 36 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/crypto/samsung-sss.txt
>>
>> Can we get this series merged in.
>> Its has got reviewed and re-based several times and got acked by a
>> couple of seniors.
>
> Do you want me to pick these series up?
>
> Cheers,
thank you for this changeset, in my opinion it is quite good. To all changes
Acked-by: Vladimir Zapolskiy <[email protected]>
--
With best wishes,
Vladimir
On Mon, Apr 28, 2014 at 10:44:52AM +0000, Naveen Krishna Chatradhi wrote:
> SSS module on Exynos4210, Exynos5250 and Exynos5420 SoCs has added
> features to the one on S5PV210. However with minor changes the s5p-sss.c
> driver can be reused to support SSS modules on Exynos4 and 5 SoCs.
>
> This patch set
> 1. Adds device tree support to the s5p-sss.c driver and Documentation
> 2. Adds code to support SSS module on Exynos4 and 5 SoCs
> 3. Adds variant struct to handle the differences in SSS modules
> 4. Adds clk_prepare/clk_unprepare clocks to the s5p-sss.c driver
>
> Note: Compatible "exynos4210-secss" should work for Exynos4412 and
> Exynos5260 (Exynos5260, for which ARCH code is under review)
> I couldn't test on Exynos4412 and Exynos4210 boards, Should be able to
> test with addition of DT node and clocks support.
>
> These patches are under review at
> https://lkml.org/lkml/2014/2/17/124
>
> Naveen Krishna Chatradhi (7):
All applied. Thanks!
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt