This seires patch mainly add some RAS registers to enhance the
DFX positioning function and fix some cleanup issues.
Qi Tao (3):
crypto: hisilicon/sec2 - updates the sec DFX function register
crypto: hisilicon/sec2 - modify nested macro call
crypto: hisilicon/sec2 - fix some cleanup issues
Wenkai Lin (1):
crypto: hisilicon/sec - remove unused parameter
drivers/crypto/hisilicon/sec2/sec_crypto.c | 33 ++++++++--------------
drivers/crypto/hisilicon/sec2/sec_main.c | 5 ++++
2 files changed, 17 insertions(+), 21 deletions(-)
--
2.33.0
As the sec DFX function is enhanced, some RAS registers are added
to the original DFX registers to enhance the DFX positioning function.
Signed-off-by: Qi Tao <[email protected]>
---
drivers/crypto/hisilicon/sec2/sec_main.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 7bb99381bbdf..5fc4d56ee873 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -282,6 +282,11 @@ static const struct debugfs_reg32 sec_dfx_regs[] = {
{"SEC_BD_SAA6 ", 0x301C38},
{"SEC_BD_SAA7 ", 0x301C3C},
{"SEC_BD_SAA8 ", 0x301C40},
+ {"SEC_RAS_CE_ENABLE ", 0x301050},
+ {"SEC_RAS_FE_ENABLE ", 0x301054},
+ {"SEC_RAS_NFE_ENABLE ", 0x301058},
+ {"SEC_REQ_TRNG_TIME_TH ", 0x30112C},
+ {"SEC_CHANNEL_RNG_REQ_THLD ", 0x302110},
};
/* define the SEC's dfx regs region and region length */
--
2.33.0
From: Wenkai Lin <[email protected]>
Unused parameter of static functions should be removed.
Signed-off-by: Wenkai Lin <[email protected]>
---
drivers/crypto/hisilicon/sec2/sec_crypto.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c
index 5d4facf62c86..ee6cc2e483ab 100644
--- a/drivers/crypto/hisilicon/sec2/sec_crypto.c
+++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c
@@ -485,8 +485,7 @@ static void sec_alg_resource_free(struct sec_ctx *ctx,
sec_free_mac_resource(dev, qp_ctx->res);
}
-static int sec_alloc_qp_ctx_resource(struct hisi_qm *qm, struct sec_ctx *ctx,
- struct sec_qp_ctx *qp_ctx)
+static int sec_alloc_qp_ctx_resource(struct sec_ctx *ctx, struct sec_qp_ctx *qp_ctx)
{
u16 q_depth = qp_ctx->qp->sq_depth;
struct device *dev = ctx->dev;
@@ -541,8 +540,7 @@ static void sec_free_qp_ctx_resource(struct sec_ctx *ctx, struct sec_qp_ctx *qp_
kfree(qp_ctx->req_list);
}
-static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,
- int qp_ctx_id, int alg_type)
+static int sec_create_qp_ctx(struct sec_ctx *ctx, int qp_ctx_id)
{
struct sec_qp_ctx *qp_ctx;
struct hisi_qp *qp;
@@ -561,7 +559,7 @@ static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,
idr_init(&qp_ctx->req_idr);
INIT_LIST_HEAD(&qp_ctx->backlog);
- ret = sec_alloc_qp_ctx_resource(qm, ctx, qp_ctx);
+ ret = sec_alloc_qp_ctx_resource(ctx, qp_ctx);
if (ret)
goto err_destroy_idr;
@@ -614,7 +612,7 @@ static int sec_ctx_base_init(struct sec_ctx *ctx)
}
for (i = 0; i < sec->ctx_q_num; i++) {
- ret = sec_create_qp_ctx(&sec->qm, ctx, i, 0);
+ ret = sec_create_qp_ctx(ctx, i);
if (ret)
goto err_sec_release_qp_ctx;
}
@@ -750,9 +748,7 @@ static void sec_skcipher_uninit(struct crypto_skcipher *tfm)
sec_ctx_base_uninit(ctx);
}
-static int sec_skcipher_3des_setkey(struct crypto_skcipher *tfm, const u8 *key,
- const u32 keylen,
- const enum sec_cmode c_mode)
+static int sec_skcipher_3des_setkey(struct crypto_skcipher *tfm, const u8 *key, const u32 keylen)
{
struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);
struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
@@ -843,7 +839,7 @@ static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key,
switch (c_alg) {
case SEC_CALG_3DES:
- ret = sec_skcipher_3des_setkey(tfm, key, keylen, c_mode);
+ ret = sec_skcipher_3des_setkey(tfm, key, keylen);
break;
case SEC_CALG_AES:
case SEC_CALG_SM4:
--
2.33.0
On 2023/12/29 14:44, Qi Tao wrote:
> This seires patch mainly add some RAS registers to enhance the
> DFX positioning function and fix some cleanup issues.
>
> Qi Tao (3):
> crypto: hisilicon/sec2 - updates the sec DFX function register
> crypto: hisilicon/sec2 - modify nested macro call
> crypto: hisilicon/sec2 - fix some cleanup issues
>
> Wenkai Lin (1):
> crypto: hisilicon/sec - remove unused parameter
>
> drivers/crypto/hisilicon/sec2/sec_crypto.c | 33 ++++++++--------------
> drivers/crypto/hisilicon/sec2/sec_main.c | 5 ++++
> 2 files changed, 17 insertions(+), 21 deletions(-)
>
Reviewed-by: Longfang Liu <[email protected]>
Thanks,
Longfang.
On 2023/12/29 14:44, Qi Tao wrote:
> This seires patch mainly add some RAS registers to enhance the
> DFX positioning function and fix some cleanup issues.
>
> Qi Tao (3):
> crypto: hisilicon/sec2 - updates the sec DFX function register
> crypto: hisilicon/sec2 - modify nested macro call
> crypto: hisilicon/sec2 - fix some cleanup issues
>
> Wenkai Lin (1):
> crypto: hisilicon/sec - remove unused parameter
>
> drivers/crypto/hisilicon/sec2/sec_crypto.c | 33 ++++++++--------------
> drivers/crypto/hisilicon/sec2/sec_main.c | 5 ++++
> 2 files changed, 17 insertions(+), 21 deletions(-)
>
I want to follow up on the patch I submitted three weeks ago.
please let me know if there is anything I can do to help move this
process forward.
Thanks，
Qi Tao