On 21/12/2022 10:08, Jia Jie Ho wrote:
> Adding StarFive TRNG controller node to VisionFive 2 SoC.
>
> Co-developed-by: Jenny Zhang <[email protected]>
> Signed-off-by: Jenny Zhang <[email protected]>
> Signed-off-by: Jia Jie Ho <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 4ac159d79d66..dd3ad19772a5 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -455,5 +455,16 @@ uart5: serial@12020000 {
> reg-shift = <2>;
> status = "disabled";
> };
> +
> + rng: rng@1600c000 {
> + compatible = "starfive,jh7110-trng";
> + reg = <0x0 0x1600C000 0x0 0x4000>;
> + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> + clock-names = "hclk", "ahb";
> + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> + interrupts = <30>;
> + status = "okay";
Drop. It's by default.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Wednesday, December 21, 2022 5:48 PM
> To: JiaJie Ho <[email protected]>; Olivia Mackall
> <[email protected]>; Herbert Xu <[email protected]>; Rob
> Herring <[email protected]>; Krzysztof Kozlowski
> <[email protected]>
> Cc: Emil Renner Berthing <[email protected]>; Conor Dooley
> <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]
> Subject: Re: [PATCH 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
>
> > +
> > + rng: rng@1600c000 {
> > + compatible = "starfive,jh7110-trng";
> > + reg = <0x0 0x1600C000 0x0 0x4000>;
> > + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> > + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> > + clock-names = "hclk", "ahb";
> > + resets = <&stgcrg
> JH7110_STGRST_SEC_TOP_HRESETN>;
> > + interrupts = <30>;
> > + status = "okay";
>
> Drop. It's by default.
>
I'll fix this in v2.
Thanks,
Jia Jie