Each of the drivers under rtlwifi contains its own copy of the macros described in
the subject. In addition, there are macros defined for each field even if those
particular bits are never accessed. The cleanup consists of moving all such
macros to a special file, eliminate duplication, and removing all macros that
are defined but not used. These changes remove over 1200 lines of source code.
Signed-off-by: Larry Finger <[email protected]>
---
Larry Finger (5):
rtlwifi: Move RX/TX macros into common file
rtl8192ce: Switch to use the combined macros file
rtl8192cu: Convert driver to use the new macros file
rtl8192de: Change driver to use new macros file
rtl8192se: Convert driver to use the new macro file
drivers/net/wireless/rtlwifi/macros.h | 460 ++++++++++++++++++++++++
drivers/net/wireless/rtlwifi/rtl8192ce/trx.h | 499 +-------------------------
drivers/net/wireless/rtlwifi/rtl8192cu/mac.c | 6 +-
drivers/net/wireless/rtlwifi/rtl8192cu/trx.c | 193 +++++-----
drivers/net/wireless/rtlwifi/rtl8192cu/trx.h | 310 +----------------
drivers/net/wireless/rtlwifi/rtl8192de/trx.c | 4 +-
drivers/net/wireless/rtlwifi/rtl8192de/trx.h | 499 +-------------------------
drivers/net/wireless/rtlwifi/rtl8192se/def.h | 406 +---------------------
drivers/net/wireless/rtlwifi/rtl8192se/trx.c | 121 ++++---
9 files changed, 635 insertions(+), 1863 deletions(-)
create mode 100644 drivers/net/wireless/rtlwifi/macros.h
--
1.7.7
Each of the 4 drivers that use rtlwifi maintains its own set of macros
that get and set the various fields in the RX and TX descriptors. To
reduce the size of the source, and to help maintainability, these
macros are combined into a single file. In addition, any macro that is
defined, but not used, is deleted.
This patch creates the new, combined macro file.
Signed-off-by: Larry Finger <[email protected]>
---
drivers/net/wireless/rtlwifi/macros.h | 460 +++++++++++++++++++++++++++++++++
1 files changed, 460 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/wireless/rtlwifi/macros.h
diff --git a/drivers/net/wireless/rtlwifi/macros.h b/drivers/net/wireless/rtlwifi/macros.h
new file mode 100644
index 0000000..19df8c9
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/macros.h
@@ -0,0 +1,460 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2012 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <[email protected]>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <[email protected]>
+ *
+ *****************************************************************************/
+
+#ifndef __RTLWIFI_MAC_H__
+#define __RTLWIFI_MAC_H__
+
+/* Define a macro that takes a le32 word, converts it to host ordering,
+ * right shifts by a specified count, creates a mask of the specified
+ * bit count, and extracts that number of bits.
+ */
+
+#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
+ ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
+ BIT_LEN_MASK_32(__mask))
+
+/* Define a macro that clears a bit field in an le32 word and
+ * sets the specified value into that bit field. The resulting
+ * value remains in le32 ordering; however, it is properly converted
+ * to host ordering for the clear and set operations before conversion
+ * back to le32.
+ */
+
+#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
+ (*(__le32 *)(__pdesc) = \
+ (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
+ (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
+ (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
+
+/* Because the PCI Tx descriptors are chained at the
+ * initialization and all the NextDescAddresses in
+ * these descriptors cannot not be cleared (or
+ * driver/HW cannot find the next descriptor), the
+ * offset 36 (NextDescAddresses) is reserved when
+ * the desc is cleared. */
+#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
+do { \
+ if (_size > TX_DESC_NEXT_DESC_OFFSET) \
+ memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
+ else \
+ memset(__pdesc, 0, _size); \
+} while (0)
+
+/* macros to read/write various fields in RX or TX descriptors
+ *
+ * The organization is as follows:
+ * 1. Macros that operate on the same dword are placed together.
+ * 2. The macros for rtl8192ce are first. Most of these are also
+ * used for rtl8192de, but the register layout is different
+ * for rtl8192cu and rtl8192se.
+ * 3. Special macros for other drivers will be given an _CU, _SE,
+ * and _DE suffix, and listed following those for rtl8192ce.
+ */
+
+/*********************** DWORD 0 ***********************/
+
+#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
+#define SET_TX_DESC_OFFSET(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
+#define SET_TX_DESC_BMC(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
+#define SET_TX_DESC_HTC(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
+#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
+#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
+#define SET_TX_DESC_LINIP(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
+#define SET_TX_DESC_OWN(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
+
+#define GET_RX_DESC_PKT_LEN(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 0, 14)
+#define GET_RX_DESC_CRC32(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 14, 1)
+#define GET_RX_DESC_ICV(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 15, 1)
+#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 16, 4)
+#define GET_RX_DESC_SHIFT(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 24, 2)
+#define GET_RX_DESC_PHYST(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 26, 1)
+#define GET_RX_DESC_SWDEC(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 27, 1)
+#define GET_RX_DESC_OWN(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 31, 1)
+#define GET_TX_DESC_OWN(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 31, 1)
+/* Special macros for rtl8192cu */
+#define GET_RX_DESC_PKT_LEN_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
+#define GET_RX_DESC_CRC32_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
+#define GET_RX_DESC_ICV_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
+#define GET_RX_DESC_DRVINFO_SIZE_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
+#define GET_RX_DESC_SHIFT_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
+#define GET_RX_DESC_PHY_STATUS_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
+#define GET_RX_DESC_SWDEC_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
+/* Special macros for rtl8192se */
+#define SET_RX_STATUS_DESC_PKT_LEN_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
+#define SET_RX_STATUS_DESC_EOR_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
+#define SET_RX_STATUS_DESC_OWN_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
+
+#define GET_RX_STATUS_DESC_PKT_LEN_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 0, 14)
+#define GET_RX_STATUS_DESC_CRC32_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 14, 1)
+#define GET_RX_STATUS_DESC_ICV_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 15, 1)
+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 16, 4)
+#define GET_RX_STATUS_DESC_SHIFT_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 24, 2)
+#define GET_RX_STATUS_DESC_PHY_STATUS_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 26, 1)
+#define GET_RX_STATUS_DESC_SWDEC_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 27, 1)
+#define GET_RX_STATUS_DESC_OWN_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc, 31, 1)
+
+/*********************** DWORD 1 ***********************/
+
+#define SET_TX_DESC_MACID(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
+#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
+#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
+#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
+#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
+#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
+#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
+
+#define GET_TX_DESC_MACID(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
+/* Special macros for rtl8192cu */
+#define SET_TX_DESC_MACID_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
+#define SET_TX_DESC_AGG_ENABLE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
+#define SET_TX_DESC_AGG_BREAK_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
+#define SET_TX_DESC_RDG_ENABLE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
+#define SET_TX_DESC_QUEUE_SEL_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
+#define GET_RX_DESC_PAGGR_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
+#define GET_RX_DESC_FAGGR_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
+#define SET_TX_DESC_RATE_ID_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
+#define SET_TX_DESC_NAV_USE_HDR_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
+#define SET_TX_DESC_SEC_TYPE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
+#define SET_TX_DESC_PKT_OFFSET_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
+/* Special macros for rtl8192de */
+#define SET_TX_DESC_AGG_ENABLE_DE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
+#define SET_TX_DESC_PKT_OFFSET_DE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_MACID_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
+#define SET_TX_DESC_QUEUE_SEL_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
+#define GET_RX_STATUS_DESC_PAGGR_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
+#define GET_RX_STATUS_DESC_FAGGR_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
+#define SET_TX_DESC_NON_QOS_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 16, 1, __val)
+#define SET_TX_DESC_SEC_TYPE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
+
+/*********************** DWORD 2 ***********************/
+
+#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
+#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
+/* Special macros for rtl8192cu */
+#define SET_TX_DESC_MORE_FRAG_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
+#define SET_TX_DESC_AMPDU_DENSITY_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_RSVD_MACID_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(((__pdesc)+8), 24, 5, __val)
+#define SET_TX_DESC_AGG_ENABLE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+8, 29, 1, __val)
+
+/*********************** DWORD 3 ***********************/
+
+#define SET_TX_DESC_SEQ(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
+#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
+/* Special macros for rtl8192cu */
+#define GET_RX_DESC_RX_MCS_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
+#define GET_RX_DESC_RX_HT_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
+#define GET_RX_DESC_SPLCP_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
+#define GET_RX_DESC_BW_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
+#define SET_TX_DESC_SEQ_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
+#define SET_TX_DESC_PKT_ID_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
+/* Special macros for rtl8192se */
+#define GET_RX_STATUS_DESC_RX_MCS_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
+#define GET_RX_STATUS_DESC_RX_HT_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
+#define GET_RX_STATUS_DESC_SPLCP_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
+#define GET_RX_STATUS_DESC_BW_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
+#define SET_TX_DESC_SEQ_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
+#define SET_TX_DESC_FRAG(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
+
+/*********************** DWORD 4 ***********************/
+
+#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
+#define SET_TX_DESC_QOS(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
+#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
+#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
+#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
+#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
+#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
+#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
+#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
+#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
+#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
+#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
+#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
+#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
+#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
+/* Special macros for rtl8192cu */
+#define SET_TX_DESC_RTS_RATE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
+#define SET_TX_DESC_QOS_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
+#define SET_TX_DESC_HWSEQ_EN_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
+#define SET_TX_DESC_USE_RATE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
+#define SET_TX_DESC_DISABLE_FB_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
+#define SET_TX_DESC_CTS2SELF_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
+#define SET_TX_DESC_RTS_ENABLE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
+#define SET_TX_DESC_HW_RTS_ENABLE_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
+#define SET_TX_DESC_DATA_SC_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
+#define SET_TX_DESC_DATA_BW_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
+#define SET_TX_DESC_RTS_SHORT_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
+#define SET_TX_DESC_RTS_BW_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
+#define SET_TX_DESC_RTS_SC_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
+#define SET_TX_DESC_RTS_STBC_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_RTS_RATE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 0, 6, __val)
+#define SET_TX_DESC_TXHT_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 16, 1, __val)
+#define SET_TX_DESC_CTS_ENABLE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
+#define SET_TX_DESC_RTS_ENABLE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
+#define SET_TX_DESC_RA_BRSR_ID_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 13, 3, __val)
+#define SET_TX_DESC_TX_SHORT_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 17, 1, __val)
+#define SET_TX_DESC_TX_BANDWIDTH_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
+#define SET_TX_DESC_TX_SUB_CARRIER_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 19, 2, __val)
+#define SET_TX_DESC_RTS_SHORT_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
+#define SET_TX_DESC_RTS_BANDWIDTH_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
+#define SET_TX_DESC_RTS_SUB_CARRIER_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 27, 2, __val)
+#define SET_TX_DESC_RTS_STBC_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 29, 2, __val)
+#define SET_TX_DESC_USER_RATE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+16, 31, 1, __val)
+
+/*********************** DWORD 5 ***********************/
+
+#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
+#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
+/* Special macros for rtl8192cu */
+#define GET_RX_DESC_TSFL_CU(__rxdesc) \
+ SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
+#define SET_TX_DESC_DATA_SHORTGI_CU(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_PACKET_ID_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 0, 9, __val)
+#define SET_TX_DESC_TX_RATE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 9, 6, __val)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+20, 16, 5, __val)
+#define GET_RX_STATUS_DESC_TSFL_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
+
+/*********************** DWORD 6 ***********************/
+
+#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
+/* Special macros for rtl8192cu */
+#define SET_TX_DESC_MAX_AGG_NUM_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
+/* Special macros for rtl8192se */
+#define SET_RX_STATUS__DESC_BUFF_ADDR_SE(__pdesc, __val)\
+ SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
+
+/*********************** DWORD 7 ***********************/
+
+#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
+/* Special macros for rtl8192cu */
+#define SET_TX_DESC_TX_DESC_CHECKSUM_CU(__txdesc, __value) \
+ SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_TX_BUFFER_SIZE_SE(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
+
+/*********************** DWORD 8 ***********************/
+
+#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
+
+#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_TX_BUFFER_ADDRESS_SE(__pdesc, __val)\
+ SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS_SE(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
+
+/*********************** DWORD 9 ***********************/
+/* Special macros for rtl8192se */
+#define SET_TX_DESC_NEXT_DESC_ADDRESS_SE(__pdesc, __val)\
+ SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
+
+/*********************** DWORD 10 ***********************/
+
+#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
+
+/*********************** DWORD 11 ***********************/
+
+#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
+#define SET_RX_DESC_EOR(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
+#define SET_RX_DESC_OWN(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
+
+#define GET_RX_DESC_PAGGR(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
+#define GET_RX_DESC_FAGGR(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
+
+#define GET_RX_DESC_RXMCS(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
+#define GET_RX_DESC_RXHT(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
+#define GET_RX_DESC_SPLCP(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
+#define GET_RX_DESC_BW(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
+
+#define GET_RX_DESC_TSFL(__pdesc) \
+ SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
+
+#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
+ SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
+
+#endif
--
1.7.7
This patch switches rtl8192se to use the new macros file.
Signed-off-by: Larry Finger <[email protected]>
---
drivers/net/wireless/rtlwifi/rtl8192se/def.h | 406 +-------------------------
drivers/net/wireless/rtlwifi/rtl8192se/trx.c | 121 ++++----
2 files changed, 67 insertions(+), 460 deletions(-)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/def.h b/drivers/net/wireless/rtlwifi/rtl8192se/def.h
index d1b0a1e..3a3a3d9 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/def.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/def.h
@@ -29,6 +29,8 @@
#ifndef __REALTEK_92S_DEF_H__
#define __REALTEK_92S_DEF_H__
+#include "../macros.h"
+
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
@@ -57,413 +59,17 @@
#define TX_DESC_SIZE_RTL8192S (16 * 4)
#define TX_CMDDESC_SIZE_RTL8192S (16 * 4)
-/* Define a macro that takes a le32 word, converts it to host ordering,
- * right shifts by a specified count, creates a mask of the specified
- * bit count, and extracts that number of bits.
- */
-
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
- ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
- BIT_LEN_MASK_32(__mask))
-
-/* Define a macro that clears a bit field in an le32 word and
- * sets the specified value into that bit field. The resulting
- * value remains in le32 ordering; however, it is properly converted
- * to host ordering for the clear and set operations before conversion
- * back to le32.
- */
-
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
- (*(__le32 *)(__pdesc) = \
- (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
- (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
- (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
-
-/* macros to read/write various fields in RX or TX descriptors */
-
-/* Dword 0 */
-#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
-#define SET_TX_DESC_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
-#define SET_TX_DESC_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
-#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
-#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
-#define SET_TX_DESC_LINIP(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
-#define SET_TX_DESC_AMSDU(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
-#define SET_TX_DESC_GREEN_FIELD(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_TX_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_TX_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-/* Dword 1 */
-#define SET_TX_DESC_MACID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
-#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
-#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
-#define SET_TX_DESC_PIFS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
-#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
-#define SET_TX_DESC_ACK_POLICY(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
-#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
-#define SET_TX_DESC_NON_QOS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
-#define SET_TX_DESC_KEY_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
-#define SET_TX_DESC_OUI(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
-#define SET_TX_DESC_PKT_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
-#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
-#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
-#define SET_TX_DESC_WDS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
-#define SET_TX_DESC_HTC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
-#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
-#define SET_TX_DESC_HWPC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
-
-/* Dword 2 */
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
-#define SET_TX_DESC_TSFL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
-#define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
-#define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
-#define SET_TX_DESC_RSVD_MACID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
-#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
-#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
-#define SET_TX_DESC_OWN_MAC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
-
-/* Dword 3 */
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
-#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
-#define SET_TX_DESC_SEQ(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
-#define SET_TX_DESC_FRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
-
-/* Dword 4 */
-#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
-#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
-#define SET_TX_DESC_CTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
-#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
-#define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
-#define SET_TX_DESC_TXHT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
-#define SET_TX_DESC_TX_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
-#define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
-#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
-#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
-#define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
-#define SET_TX_DESC_RTS_HT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
-#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
-#define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
-#define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
-#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
-#define SET_TX_DESC_USER_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
-
-/* Dword 5 */
-#define SET_TX_DESC_PACKET_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
-#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
-#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
-#define SET_TX_DESC_TX_AGC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
-
-/* Dword 6 */
-#define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
-#define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
-
-/* Dword 7 */
-#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
-#define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
-#define SET_TX_DESC_TCP_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
-
-/* Dword 8 */
-#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
-#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
-
-/* Dword 9 */
-#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
-
-/* Because the PCI Tx descriptors are chaied at the
- * initialization and all the NextDescAddresses in
- * these descriptors cannot not be cleared (,or
- * driver/HW cannot find the next descriptor), the
- * offset 36 (NextDescAddresses) is reserved when
- * the desc is cleared. */
#define TX_DESC_NEXT_DESC_OFFSET 36
-#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
-do { \
- if (_size > TX_DESC_NEXT_DESC_OFFSET) \
- memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
- else \
- memset(__pdesc, 0, _size); \
-} while (0);
/* Rx Desc */
#define RX_STATUS_DESC_SIZE 24
#define RX_DRV_INFO_SIZE_UNIT 8
-/* DWORD 0 */
-#define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
-#define SET_RX_STATUS_DESC_CRC32(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
-#define SET_RX_STATUS_DESC_ICV(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
-#define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
-#define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
-#define SET_RX_STATUS_DESC_QOS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
-#define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
-#define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
-#define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
-#define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
-#define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
-#define SET_RX_STATUS_DESC_EOR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_RX_STATUS_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_RX_STATUS_DESC_PKT_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 0, 14)
-#define GET_RX_STATUS_DESC_CRC32(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 14, 1)
-#define GET_RX_STATUS_DESC_ICV(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 15, 1)
-#define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 16, 4)
-#define GET_RX_STATUS_DESC_SECURITY(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 20, 3)
-#define GET_RX_STATUS_DESC_QOS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 23, 1)
-#define GET_RX_STATUS_DESC_SHIFT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 24, 2)
-#define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 26, 1)
-#define GET_RX_STATUS_DESC_SWDEC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 27, 1)
-#define GET_RX_STATUS_DESC_LAST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 28, 1)
-#define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 29, 1)
-#define GET_RX_STATUS_DESC_EOR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 30, 1)
-#define GET_RX_STATUS_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-/* DWORD 1 */
-#define SET_RX_STATUS_DESC_MACID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
-#define SET_RX_STATUS_DESC_TID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
-#define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
-#define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
-#define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
-#define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
-#define SET_RX_STATUS_DESC_PAM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
-#define SET_RX_STATUS_DESC_PWR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
-#define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
-#define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
-#define SET_RX_STATUS_DESC_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
-#define SET_RX_STATUS_DESC_MC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
-#define SET_RX_STATUS_DESC_BC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
-
-#define GET_RX_STATUS_DEC_MACID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
-#define GET_RX_STATUS_DESC_TID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
-#define GET_RX_STATUS_DESC_PAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
-#define GET_RX_STATUS_DESC_FAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
-#define GET_RX_STATUS_DESC_A1_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
-#define GET_RX_STATUS_DESC_A2_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
-#define GET_RX_STATUS_DESC_PAM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
-#define GET_RX_STATUS_DESC_PWR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
-#define GET_RX_STATUS_DESC_MORE_DATA(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
-#define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
-#define GET_RX_STATUS_DESC_TYPE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
-#define GET_RX_STATUS_DESC_MC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
-#define GET_RX_STATUS_DESC_BC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
-
-/* DWORD 2 */
-#define SET_RX_STATUS_DESC_SEQ(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
-#define SET_RX_STATUS_DESC_FRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
-#define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
-#define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
-
-#define GET_RX_STATUS_DESC_SEQ(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
-#define GET_RX_STATUS_DESC_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
-#define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
-#define GET_RX_STATUS_DESC_NEXT_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
-
-/* DWORD 3 */
-#define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
-#define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
-#define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
-#define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
-#define SET_RX_STATUS_DESC_BW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
-#define SET_RX_STATUS_DESC_HTC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
-#define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
-#define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
-#define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
-#define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
-#define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
-#define SET_RX_STATUS_DESC_IV0(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
-
-#define GET_RX_STATUS_DESC_RX_MCS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
-#define GET_RX_STATUS_DESC_RX_HT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
-#define GET_RX_STATUS_DESC_AMSDU(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
-#define GET_RX_STATUS_DESC_SPLCP(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
-#define GET_RX_STATUS_DESC_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
-#define GET_RX_STATUS_DESC_HTC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
-#define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
-#define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
-#define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
-#define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
-#define GET_RX_STATUS_DESC_HWPC_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
-#define GET_RX_STATUS_DESC_IV0(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
-
-/* DWORD 4 */
-#define SET_RX_STATUS_DESC_IV1(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
-#define GET_RX_STATUS_DESC_IV1(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
-
-/* DWORD 5 */
-#define SET_RX_STATUS_DESC_TSFL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
-#define GET_RX_STATUS_DESC_TSFL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
-
-/* DWORD 6 */
-#define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
-
#define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
- (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE1M || \
- GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE2M || \
- GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE5_5M ||\
- GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE11M)
+ (GET_RX_STATUS_DESC_RX_MCS_SE(_pdesc) == DESC92_RATE1M || \
+ GET_RX_STATUS_DESC_RX_MCS_SE(_pdesc) == DESC92_RATE2M || \
+ GET_RX_STATUS_DESC_RX_MCS_SE(_pdesc) == DESC92_RATE5_5M || \
+ GET_RX_STATUS_DESC_RX_MCS_SE(_pdesc) == DESC92_RATE11M)
enum rf_optype {
RF_OP_BY_SW_3WIRE = 0,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/trx.c b/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
index e58b80f..e742bf3 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
@@ -513,25 +513,26 @@ bool rtl92se_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
struct sk_buff *skb)
{
struct rx_fwinfo *p_drvinfo;
- u32 phystatus = (u32)GET_RX_STATUS_DESC_PHY_STATUS(pdesc);
+ u32 phystatus = (u32)GET_RX_STATUS_DESC_PHY_STATUS_SE(pdesc);
struct ieee80211_hdr *hdr;
- stats->length = (u16)GET_RX_STATUS_DESC_PKT_LEN(pdesc);
- stats->rx_drvinfo_size = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE(pdesc) * 8;
- stats->rx_bufshift = (u8)(GET_RX_STATUS_DESC_SHIFT(pdesc) & 0x03);
- stats->icv = (u16)GET_RX_STATUS_DESC_ICV(pdesc);
- stats->crc = (u16)GET_RX_STATUS_DESC_CRC32(pdesc);
+ stats->length = (u16)GET_RX_STATUS_DESC_PKT_LEN_SE(pdesc);
+ stats->rx_drvinfo_size = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_SE(pdesc)
+ * 8;
+ stats->rx_bufshift = (u8)(GET_RX_STATUS_DESC_SHIFT_SE(pdesc) & 0x03);
+ stats->icv = (u16)GET_RX_STATUS_DESC_ICV_SE(pdesc);
+ stats->crc = (u16)GET_RX_STATUS_DESC_CRC32_SE(pdesc);
stats->hwerror = (u16)(stats->crc | stats->icv);
- stats->decrypted = !GET_RX_STATUS_DESC_SWDEC(pdesc);
+ stats->decrypted = !GET_RX_STATUS_DESC_SWDEC_SE(pdesc);
- stats->rate = (u8)GET_RX_STATUS_DESC_RX_MCS(pdesc);
- stats->shortpreamble = (u16)GET_RX_STATUS_DESC_SPLCP(pdesc);
- stats->isampdu = (bool)(GET_RX_STATUS_DESC_PAGGR(pdesc) == 1);
- stats->isfirst_ampdu = (bool) ((GET_RX_STATUS_DESC_PAGGR(pdesc) == 1)
- && (GET_RX_STATUS_DESC_FAGGR(pdesc) == 1));
- stats->timestamp_low = GET_RX_STATUS_DESC_TSFL(pdesc);
- stats->rx_is40Mhzpacket = (bool)GET_RX_STATUS_DESC_BW(pdesc);
- stats->is_ht = (bool)GET_RX_STATUS_DESC_RX_HT(pdesc);
+ stats->rate = (u8)GET_RX_STATUS_DESC_RX_MCS_SE(pdesc);
+ stats->shortpreamble = (u16)GET_RX_STATUS_DESC_SPLCP_SE(pdesc);
+ stats->isampdu = (bool)(GET_RX_STATUS_DESC_PAGGR_SE(pdesc) == 1);
+ stats->isfirst_ampdu = (bool) ((GET_RX_STATUS_DESC_PAGGR_SE(pdesc) == 1)
+ && (GET_RX_STATUS_DESC_FAGGR_SE(pdesc) == 1));
+ stats->timestamp_low = GET_RX_STATUS_DESC_TSFL_SE(pdesc);
+ stats->rx_is40Mhzpacket = (bool)GET_RX_STATUS_DESC_BW_SE(pdesc);
+ stats->is_ht = (bool)GET_RX_STATUS_DESC_RX_HT_SE(pdesc);
stats->is_cck = SE_RX_HAL_IS_CCK_RATE(pdesc);
if (stats->hwerror)
@@ -628,13 +629,13 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
if (rtlpriv->dm.useramask) {
/* set txdesc macId */
if (ptcb_desc->mac_id < 32) {
- SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
+ SET_TX_DESC_MACID_SE(pdesc, ptcb_desc->mac_id);
reserved_macid |= ptcb_desc->mac_id;
}
}
- SET_TX_DESC_RSVD_MACID(pdesc, reserved_macid);
+ SET_TX_DESC_RSVD_MACID_SE(pdesc, reserved_macid);
- SET_TX_DESC_TXHT(pdesc, ((ptcb_desc->hw_rate >=
+ SET_TX_DESC_TXHT_SE(pdesc, ((ptcb_desc->hw_rate >=
DESC92_RATEMCS0) ? 1 : 0));
if (rtlhal->version == VERSION_8192S_ACUT) {
@@ -646,31 +647,31 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
}
}
- SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
+ SET_TX_DESC_TX_RATE_SE(pdesc, ptcb_desc->hw_rate);
if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
- SET_TX_DESC_TX_SHORT(pdesc, 0);
+ SET_TX_DESC_TX_SHORT_SE(pdesc, 0);
/* Aggregation related */
if (info->flags & IEEE80211_TX_CTL_AMPDU)
- SET_TX_DESC_AGG_ENABLE(pdesc, 1);
+ SET_TX_DESC_AGG_ENABLE_SE(pdesc, 1);
/* For AMPDU, we must insert SSN into TX_DESC */
- SET_TX_DESC_SEQ(pdesc, seq_number);
+ SET_TX_DESC_SEQ_SE(pdesc, seq_number);
/* Protection mode related */
/* For 92S, if RTS/CTS are set, HW will execute RTS. */
/* We choose only one protection mode to execute */
- SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
+ SET_TX_DESC_RTS_ENABLE_SE(pdesc, ((ptcb_desc->rts_enable &&
!ptcb_desc->cts_enable) ? 1 : 0));
- SET_TX_DESC_CTS_ENABLE(pdesc, ((ptcb_desc->cts_enable) ?
+ SET_TX_DESC_CTS_ENABLE_SE(pdesc, ((ptcb_desc->cts_enable) ?
1 : 0));
- SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
+ SET_TX_DESC_RTS_STBC_SE(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
- SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
- SET_TX_DESC_RTS_BANDWIDTH(pdesc, 0);
- SET_TX_DESC_RTS_SUB_CARRIER(pdesc, ptcb_desc->rts_sc);
- SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <=
+ SET_TX_DESC_RTS_RATE_SE(pdesc, ptcb_desc->rts_rate);
+ SET_TX_DESC_RTS_BANDWIDTH_SE(pdesc, 0);
+ SET_TX_DESC_RTS_SUB_CARRIER_SE(pdesc, ptcb_desc->rts_sc);
+ SET_TX_DESC_RTS_SHORT_SE(pdesc, ((ptcb_desc->rts_rate <=
DESC92_RATE54M) ?
(ptcb_desc->rts_use_shortpreamble ? 1 : 0)
: (ptcb_desc->rts_use_shortgi ? 1 : 0)));
@@ -679,17 +680,17 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
/* Set Bandwidth and sub-channel settings. */
if (bw_40) {
if (ptcb_desc->packet_bw) {
- SET_TX_DESC_TX_BANDWIDTH(pdesc, 1);
+ SET_TX_DESC_TX_BANDWIDTH_SE(pdesc, 1);
/* use duplicated mode */
- SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
+ SET_TX_DESC_TX_SUB_CARRIER_SE(pdesc, 0);
} else {
- SET_TX_DESC_TX_BANDWIDTH(pdesc, 0);
- SET_TX_DESC_TX_SUB_CARRIER(pdesc,
+ SET_TX_DESC_TX_BANDWIDTH_SE(pdesc, 0);
+ SET_TX_DESC_TX_SUB_CARRIER_SE(pdesc,
mac->cur_40_prime_sc);
}
} else {
- SET_TX_DESC_TX_BANDWIDTH(pdesc, 0);
- SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
+ SET_TX_DESC_TX_BANDWIDTH_SE(pdesc, 0);
+ SET_TX_DESC_TX_SUB_CARRIER_SE(pdesc, 0);
}
/* 3 Fill necessary field in First Descriptor */
@@ -699,7 +700,7 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len);
/*DWORD 1*/
- SET_TX_DESC_RA_BRSR_ID(pdesc, ptcb_desc->ratr_index);
+ SET_TX_DESC_RA_BRSR_ID_SE(pdesc, ptcb_desc->ratr_index);
/* Fill security related */
if (info->control.hw_key) {
@@ -709,37 +710,37 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
switch (keyconf->cipher) {
case WLAN_CIPHER_SUITE_WEP40:
case WLAN_CIPHER_SUITE_WEP104:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
+ SET_TX_DESC_SEC_TYPE_SE(pdesc, 0x1);
break;
case WLAN_CIPHER_SUITE_TKIP:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x2);
+ SET_TX_DESC_SEC_TYPE_SE(pdesc, 0x2);
break;
case WLAN_CIPHER_SUITE_CCMP:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
+ SET_TX_DESC_SEC_TYPE_SE(pdesc, 0x3);
break;
default:
- SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
+ SET_TX_DESC_SEC_TYPE_SE(pdesc, 0x0);
break;
}
}
/* Set Packet ID */
- SET_TX_DESC_PACKET_ID(pdesc, 0);
+ SET_TX_DESC_PACKET_ID_SE(pdesc, 0);
/* We will assign magement queue to BK. */
- SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
+ SET_TX_DESC_QUEUE_SEL_SE(pdesc, fw_qsel);
/* Alwasy enable all rate fallback range */
- SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
+ SET_TX_DESC_DATA_RATE_FB_LIMIT_SE(pdesc, 0x1F);
/* Fix: I don't kown why hw use 6.5M to tx when set it */
- SET_TX_DESC_USER_RATE(pdesc,
+ SET_TX_DESC_USER_RATE_SE(pdesc,
ptcb_desc->use_driver_rate ? 1 : 0);
/* Set NON_QOS bit. */
if (!ieee80211_is_data_qos(fc))
- SET_TX_DESC_NON_QOS(pdesc, 1);
+ SET_TX_DESC_NON_QOS_SE(pdesc, 1);
}
@@ -750,10 +751,10 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
/* DWORD 7 */
- SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len);
+ SET_TX_DESC_TX_BUFFER_SIZE_SE(pdesc, (u16) skb->len);
/* DOWRD 8 */
- SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
+ SET_TX_DESC_TX_BUFFER_ADDRESS_SE(pdesc, cpu_to_le32(mapping));
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
}
@@ -782,8 +783,8 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
/* 92SE need not to set TX packet size when firmware download */
SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len));
- SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
- SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
+ SET_TX_DESC_TX_BUFFER_SIZE_SE(pdesc, (u16)(skb->len));
+ SET_TX_DESC_TX_BUFFER_ADDRESS_SE(pdesc, cpu_to_le32(mapping));
wmb();
SET_TX_DESC_OWN(pdesc, 1);
@@ -797,12 +798,12 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
/* Buffer size + command header */
SET_TX_DESC_PKT_SIZE(pdesc, (u16)(skb->len));
/* Fixed queue of H2C command */
- SET_TX_DESC_QUEUE_SEL(pdesc, 0x13);
+ SET_TX_DESC_QUEUE_SEL_SE(pdesc, 0x13);
SET_BITS_TO_LE_4BYTE(skb->data, 24, 7, rtlhal->h2c_txcmd_seq);
- SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
- SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
+ SET_TX_DESC_TX_BUFFER_SIZE_SE(pdesc, (u16)(skb->len));
+ SET_TX_DESC_TX_BUFFER_ADDRESS_SE(pdesc, cpu_to_le32(mapping));
wmb();
SET_TX_DESC_OWN(pdesc, 1);
@@ -819,7 +820,7 @@ void rtl92se_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
SET_TX_DESC_OWN(pdesc, 1);
break;
case HW_DESC_TX_NEXTDESC_ADDR:
- SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
+ SET_TX_DESC_NEXT_DESC_ADDRESS_SE(pdesc, *(u32 *) val);
break;
default:
RT_ASSERT(false, "ERR txdesc :%d not process\n",
@@ -830,16 +831,16 @@ void rtl92se_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
switch (desc_name) {
case HW_DESC_RXOWN:
wmb();
- SET_RX_STATUS_DESC_OWN(pdesc, 1);
+ SET_RX_STATUS_DESC_OWN_SE(pdesc, 1);
break;
case HW_DESC_RXBUFF_ADDR:
- SET_RX_STATUS__DESC_BUFF_ADDR(pdesc, *(u32 *) val);
+ SET_RX_STATUS__DESC_BUFF_ADDR_SE(pdesc, *(u32 *) val);
break;
case HW_DESC_RXPKT_LEN:
- SET_RX_STATUS_DESC_PKT_LEN(pdesc, *(u32 *) val);
+ SET_RX_STATUS_DESC_PKT_LEN_SE(pdesc, *(u32 *) val);
break;
case HW_DESC_RXERO:
- SET_RX_STATUS_DESC_EOR(pdesc, 1);
+ SET_RX_STATUS_DESC_EOR_SE(pdesc, 1);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
@@ -859,7 +860,7 @@ u32 rtl92se_get_desc(u8 *desc, bool istx, u8 desc_name)
ret = GET_TX_DESC_OWN(desc);
break;
case HW_DESC_TXBUFF_ADDR:
- ret = GET_TX_DESC_TX_BUFFER_ADDRESS(desc);
+ ret = GET_TX_DESC_TX_BUFFER_ADDRESS_SE(desc);
break;
default:
RT_ASSERT(false, "ERR txdesc :%d not process\n",
@@ -869,10 +870,10 @@ u32 rtl92se_get_desc(u8 *desc, bool istx, u8 desc_name)
} else {
switch (desc_name) {
case HW_DESC_OWN:
- ret = GET_RX_STATUS_DESC_OWN(desc);
+ ret = GET_RX_STATUS_DESC_OWN_SE(desc);
break;
case HW_DESC_RXPKT_LEN:
- ret = GET_RX_STATUS_DESC_PKT_LEN(desc);
+ ret = GET_RX_STATUS_DESC_PKT_LEN_SE(desc);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
--
1.7.7
This patch switches rtl8192ce to use the new macros file.
Signed-off-by: Larry Finger <[email protected]>
---
drivers/net/wireless/rtlwifi/rtl8192ce/trx.h | 499 +-------------------------
1 files changed, 2 insertions(+), 497 deletions(-)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
index efb9ab2..03924e2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
@@ -30,6 +30,8 @@
#ifndef __RTL92CE_TRX_H__
#define __RTL92CE_TRX_H__
+#include "../macros.h"
+
#define TX_DESC_SIZE 64
#define TX_DESC_AGGR_SUBFRAME_SIZE 32
@@ -40,503 +42,6 @@
#define USB_HWDESC_HEADER_LEN 32
#define CRCLENGTH 4
-/* Define a macro that takes a le32 word, converts it to host ordering,
- * right shifts by a specified count, creates a mask of the specified
- * bit count, and extracts that number of bits.
- */
-
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
- ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
- BIT_LEN_MASK_32(__mask))
-
-/* Define a macro that clears a bit field in an le32 word and
- * sets the specified value into that bit field. The resulting
- * value remains in le32 ordering; however, it is properly converted
- * to host ordering for the clear and set operations before conversion
- * back to le32.
- */
-
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
- (*(__le32 *)(__pdesc) = \
- (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
- (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
- (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
-
-/* macros to read/write various fields in RX or TX descriptors */
-
-#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
-#define SET_TX_DESC_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
-#define SET_TX_DESC_BMC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
-#define SET_TX_DESC_HTC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
-#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
-#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
-#define SET_TX_DESC_LINIP(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
-#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
-#define SET_TX_DESC_GF(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_TX_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_TX_DESC_PKT_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 0, 16)
-#define GET_TX_DESC_OFFSET(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 16, 8)
-#define GET_TX_DESC_BMC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 24, 1)
-#define GET_TX_DESC_HTC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 25, 1)
-#define GET_TX_DESC_LAST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 26, 1)
-#define GET_TX_DESC_FIRST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 27, 1)
-#define GET_TX_DESC_LINIP(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 28, 1)
-#define GET_TX_DESC_NO_ACM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 29, 1)
-#define GET_TX_DESC_GF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 30, 1)
-#define GET_TX_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-#define SET_TX_DESC_MACID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
-#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
-#define SET_TX_DESC_BK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
-#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
-#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
-#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
-#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
-#define SET_TX_DESC_PIFS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
-#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
-#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
-#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
-#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
-#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
-
-#define GET_TX_DESC_MACID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
-#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
-#define GET_TX_DESC_AGG_BREAK(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
-#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
-#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
-#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
-#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
-#define GET_TX_DESC_PIFS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
-#define GET_TX_DESC_RATE_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
-#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
-#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
-#define GET_TX_DESC_SEC_TYPE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
-#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
-
-#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
-#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
-#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
-#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
-#define SET_TX_DESC_RAW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
-#define SET_TX_DESC_CCX(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
-#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
-#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
-#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
-#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
-#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
-#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
-
-#define GET_TX_DESC_RTS_RC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
-#define GET_TX_DESC_DATA_RC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
-#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
-#define GET_TX_DESC_MORE_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
-#define GET_TX_DESC_RAW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
-#define GET_TX_DESC_CCX(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
-#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
-#define GET_TX_DESC_ANTSEL_A(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
-#define GET_TX_DESC_ANTSEL_B(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
-#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
-#define GET_TX_DESC_TX_ANTL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
-#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
-
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
-#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
-#define SET_TX_DESC_SEQ(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
-#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
-
-#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
-#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
-#define GET_TX_DESC_SEQ(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
-#define GET_TX_DESC_PKT_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
-
-#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
-#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
-#define SET_TX_DESC_QOS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
-#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
-#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
-#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
-#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
-#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
-#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
-#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
-#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
-#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
-#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
-#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
-#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
-#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
-#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
-#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
-#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
-#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
-#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
-
-#define GET_TX_DESC_RTS_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
-#define GET_TX_DESC_AP_DCFE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
-#define GET_TX_DESC_QOS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
-#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
-#define GET_TX_DESC_USE_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
-#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
-#define GET_TX_DESC_DISABLE_FB(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
-#define GET_TX_DESC_CTS2SELF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
-#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
-#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
-#define GET_TX_DESC_PORT_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
-#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
-#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
-#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
-#define GET_TX_DESC_TX_STBC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
-#define GET_TX_DESC_DATA_SHORT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
-#define GET_TX_DESC_DATA_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
-#define GET_TX_DESC_RTS_SHORT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
-#define GET_TX_DESC_RTS_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
-#define GET_TX_DESC_RTS_SC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
-#define GET_TX_DESC_RTS_STBC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
-
-#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
-#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
-#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
-#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
-
-#define GET_TX_DESC_TX_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
-#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
-#define GET_TX_DESC_CCX_TAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
-#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
-#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
-#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
-#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
-#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
-
-#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
-#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
-#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
-#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
-#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
-#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
-#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
-#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
-
-#define GET_TX_DESC_TXAGC_A(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
-#define GET_TX_DESC_TXAGC_B(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
-#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
-#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
-#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
-#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
-#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
-#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
-
-#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
-#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
-#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
-#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
-#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
-
-#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
-#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
-#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
-#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
-#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
-
-#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
-#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
-
-#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
-#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
-
-#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
-#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
-
-#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
-#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
-
-#define GET_RX_DESC_PKT_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 0, 14)
-#define GET_RX_DESC_CRC32(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 14, 1)
-#define GET_RX_DESC_ICV(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 15, 1)
-#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 16, 4)
-#define GET_RX_DESC_SECURITY(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 20, 3)
-#define GET_RX_DESC_QOS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 23, 1)
-#define GET_RX_DESC_SHIFT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 24, 2)
-#define GET_RX_DESC_PHYST(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 26, 1)
-#define GET_RX_DESC_SWDEC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 27, 1)
-#define GET_RX_DESC_LS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 28, 1)
-#define GET_RX_DESC_FS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 29, 1)
-#define GET_RX_DESC_EOR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 30, 1)
-#define GET_RX_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
-#define SET_RX_DESC_EOR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_RX_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_RX_DESC_MACID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
-#define GET_RX_DESC_TID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
-#define GET_RX_DESC_HWRSVD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
-#define GET_RX_DESC_PAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
-#define GET_RX_DESC_FAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
-#define GET_RX_DESC_A1_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
-#define GET_RX_DESC_A2_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
-#define GET_RX_DESC_PAM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
-#define GET_RX_DESC_PWR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
-#define GET_RX_DESC_MD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
-#define GET_RX_DESC_MF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
-#define GET_RX_DESC_TYPE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
-#define GET_RX_DESC_MC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
-#define GET_RX_DESC_BC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
-#define GET_RX_DESC_SEQ(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
-#define GET_RX_DESC_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
-#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
-#define GET_RX_DESC_NEXT_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
-#define GET_RX_DESC_RSVD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
-
-#define GET_RX_DESC_RXMCS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
-#define GET_RX_DESC_RXHT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
-#define GET_RX_DESC_SPLCP(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
-#define GET_RX_DESC_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
-#define GET_RX_DESC_HTC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
-#define GET_RX_DESC_HWPC_ERR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
-#define GET_RX_DESC_HWPC_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
-#define GET_RX_DESC_IV0(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
-
-#define GET_RX_DESC_IV1(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
-#define GET_RX_DESC_TSFL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
-
-#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
-#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
-
-#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
-#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
-
-#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
-do { \
- if (_size > TX_DESC_NEXT_DESC_OFFSET) \
- memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
- else \
- memset(__pdesc, 0, _size); \
-} while (0);
-
struct rx_fwinfo_92c {
u8 gain_trsw[4];
u8 pwdb_all;
--
1.7.7
On 01/11/2012 06:27 PM, Joe Perches wrote:
> On Wed, 2012-01-11 at 17:07 -0600, Larry Finger wrote:
>> Each of the 4 drivers that use rtlwifi maintains its own set of macros
>> that get and set the various fields in the RX and TX descriptors. To
>> reduce the size of the source, and to help maintainability, these
>> macros are combined into a single file. In addition, any macro that is
>> defined, but not used, is deleted.
> []
>> diff --git a/drivers/net/wireless/rtlwifi/macros.h b/drivers/net/wireless/rtlwifi/macros.h
> []
>> +++ b/drivers/net/wireless/rtlwifi/macros.h
> []
>> +#ifndef __RTLWIFI_MAC_H__
>> +#define __RTLWIFI_MAC_H__
>
> That's an odd name guard for this file.
> There is a rtlwifi/rtl8192cu/mac.h file.
>
> RTIWIFI_MACROS_H might be more appropriate.
That is a good suggestion.
>> +
>> +/* Define a macro that takes a le32 word, converts it to host ordering,
>> + * right shifts by a specified count, creates a mask of the specified
>> + * bit count, and extracts that number of bits.
>> + */
>> +
>> +#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
>> + ((le32_to_cpu(*(((__le32 *)(__pdesc))))>> (__shift))& \
>> + BIT_LEN_MASK_32(__mask))
>
> This macro depends on wifi.h so why not just put
> all of these in wifi.h?
I felt that wifi.h was already large enough. For that reason, I selected a new file.
> And instead of a #define, perhaps
>
> static inline u32 le32p_to_cpu_shift_and_mask(__le32 *desc, int shift, u32 mask)
> {
> return (le32_to_cpu(*desc)>> shift)& BIT_LEN_MASK_32(mask);
> }
I need to think about this one some more.
>> +#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
>> +do { \
>> + if (_size> TX_DESC_NEXT_DESC_OFFSET) \
>> + memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
>> + else \
>> + memset(__pdesc, 0, _size); \
>> +} while (0)
>
> Perhaps
> memset(__pdesc, 0, min(size, TX_DESC_NEXT_DESC_OFFSET))
>
That is a good idea.
>> +
>> +/* macros to read/write various fields in RX or TX descriptors
>> + *
>> + * The organization is as follows:
>> + * 1. Macros that operate on the same dword are placed together.
>> + * 2. The macros for rtl8192ce are first. Most of these are also
>> + * used for rtl8192de, but the register layout is different
>> + * for rtl8192cu and rtl8192se.
>> + * 3. Special macros for other drivers will be given an _CU, _SE,
>> + * and _DE suffix, and listed following those for rtl8192ce.
>> + */
>
> I don't see how centralizing these non-shared
> macro names helps.
>
> Maybe if the code is actually common, have a
> separate #include for each card with common
> named #defines as appropriate.
The idea of centralizing the non-shared names was to have all these macros in
one place. If any need to be changes, that one file will have all of them.
Larry
On 01/12/2012 02:19 AM, Francois Romieu wrote:
> Larry Finger<[email protected]> :
>> On 01/11/2012 06:27 PM, Joe Perches wrote:
> [...]
>>> static inline u32 le32p_to_cpu_shift_and_mask(__le32 *desc, int shift, u32 mask)
>>> {
>>> return (le32_to_cpu(*desc)>> shift)& BIT_LEN_MASK_32(mask);
>>> }
>>
>> I need to think about this one some more.
>
> Joe only told a part of the story here : this change should eventually go
> along a definition of the descriptors as a __leXY struct and a specific
> registers / bits definition. It will be a bit tedious.
>
> [...]
>>> I don't see how centralizing these non-shared
>>> macro names helps.
>>>
>>> Maybe if the code is actually common, have a
>>> separate #include for each card with common
>>> named #defines as appropriate.
>>
>> The idea of centralizing the non-shared names was to have all these
>> macros in one place. If any need to be changes, that one file will
>> have all of them.
>
> It is paid at the price of the giant #include file and some irrelevant
> code pollution in chipset-dedicated parts of the driver. As the main
> driver maintainer, you may not win much -if anything- in return.
>
> Joe's suggestion can help with factoring out the code while exhibiting
> the differences in the data layout (i.e hardware registers). It is not
> automatic though.
John,
Please drop this set of patches. I'll decide how much of the refactoring I want
to do later.
Larry
On Wed, 2012-01-11 at 17:07 -0600, Larry Finger wrote:
> Each of the 4 drivers that use rtlwifi maintains its own set of macros
> that get and set the various fields in the RX and TX descriptors. To
> reduce the size of the source, and to help maintainability, these
> macros are combined into a single file. In addition, any macro that is
> defined, but not used, is deleted.
[]
> diff --git a/drivers/net/wireless/rtlwifi/macros.h b/drivers/net/wireless/rtlwifi/macros.h
[]
> +++ b/drivers/net/wireless/rtlwifi/macros.h
[]
> +#ifndef __RTLWIFI_MAC_H__
> +#define __RTLWIFI_MAC_H__
That's an odd name guard for this file.
There is a rtlwifi/rtl8192cu/mac.h file.
RTIWIFI_MACROS_H might be more appropriate.
> +
> +/* Define a macro that takes a le32 word, converts it to host ordering,
> + * right shifts by a specified count, creates a mask of the specified
> + * bit count, and extracts that number of bits.
> + */
> +
> +#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
> + ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
> + BIT_LEN_MASK_32(__mask))
This macro depends on wifi.h so why not just put
all of these in wifi.h?
And instead of a #define, perhaps
static inline u32 le32p_to_cpu_shift_and_mask(__le32 *desc, int shift, u32 mask)
{
return (le32_to_cpu(*desc) >> shift) & BIT_LEN_MASK_32(mask);
}
> +#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
> +do { \
> + if (_size > TX_DESC_NEXT_DESC_OFFSET) \
> + memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
> + else \
> + memset(__pdesc, 0, _size); \
> +} while (0)
Perhaps
memset(__pdesc, 0, min(size, TX_DESC_NEXT_DESC_OFFSET))
> +
> +/* macros to read/write various fields in RX or TX descriptors
> + *
> + * The organization is as follows:
> + * 1. Macros that operate on the same dword are placed together.
> + * 2. The macros for rtl8192ce are first. Most of these are also
> + * used for rtl8192de, but the register layout is different
> + * for rtl8192cu and rtl8192se.
> + * 3. Special macros for other drivers will be given an _CU, _SE,
> + * and _DE suffix, and listed following those for rtl8192ce.
> + */
I don't see how centralizing these non-shared
macro names helps.
Maybe if the code is actually common, have a
separate #include for each card with common
named #defines as appropriate.
> +
> +/*********************** DWORD 0 ***********************/
> +
> d+#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
> +#define SET_TX_DESC_OFFSET(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
> +#define SET_TX_DESC_BMC(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
> +#define SET_TX_DESC_HTC(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
> +#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
> +#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
> +#define SET_TX_DESC_LINIP(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
> +#define SET_TX_DESC_OWN(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
> +
> +#define GET_RX_DESC_PKT_LEN(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 0, 14)
> +#define GET_RX_DESC_CRC32(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 14, 1)
> +#define GET_RX_DESC_ICV(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 15, 1)
> +#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 16, 4)
> +#define GET_RX_DESC_SHIFT(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 24, 2)
> +#define GET_RX_DESC_PHYST(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 26, 1)
> +#define GET_RX_DESC_SWDEC(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 27, 1)
> +#define GET_RX_DESC_OWN(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 31, 1)
> +#define GET_TX_DESC_OWN(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 31, 1)
> +/* Special macros for rtl8192cu */
> +#define GET_RX_DESC_PKT_LEN_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
> +#define GET_RX_DESC_CRC32_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
> +#define GET_RX_DESC_ICV_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
> +#define GET_RX_DESC_DRVINFO_SIZE_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
> +#define GET_RX_DESC_SHIFT_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
> +#define GET_RX_DESC_PHY_STATUS_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
> +#define GET_RX_DESC_SWDEC_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
> +/* Special macros for rtl8192se */
> +#define SET_RX_STATUS_DESC_PKT_LEN_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
> +#define SET_RX_STATUS_DESC_EOR_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
> +#define SET_RX_STATUS_DESC_OWN_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
> +
> +#define GET_RX_STATUS_DESC_PKT_LEN_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 0, 14)
> +#define GET_RX_STATUS_DESC_CRC32_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 14, 1)
> +#define GET_RX_STATUS_DESC_ICV_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 15, 1)
> +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 16, 4)
> +#define GET_RX_STATUS_DESC_SHIFT_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 24, 2)
> +#define GET_RX_STATUS_DESC_PHY_STATUS_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 26, 1)
> +#define GET_RX_STATUS_DESC_SWDEC_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 27, 1)
> +#define GET_RX_STATUS_DESC_OWN_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc, 31, 1)
> +
> +/*********************** DWORD 1 ***********************/
> +
> +#define SET_TX_DESC_MACID(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
> +#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
> +#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
> +#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
> +#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
> +#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
> +#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
> +
> +#define GET_TX_DESC_MACID(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
> +/* Special macros for rtl8192cu */
> +#define SET_TX_DESC_MACID_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
> +#define SET_TX_DESC_AGG_ENABLE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
> +#define SET_TX_DESC_AGG_BREAK_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
> +#define SET_TX_DESC_RDG_ENABLE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
> +#define SET_TX_DESC_QUEUE_SEL_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
> +#define GET_RX_DESC_PAGGR_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
> +#define GET_RX_DESC_FAGGR_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
> +#define SET_TX_DESC_RATE_ID_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
> +#define SET_TX_DESC_NAV_USE_HDR_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
> +#define SET_TX_DESC_SEC_TYPE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
> +#define SET_TX_DESC_PKT_OFFSET_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
> +/* Special macros for rtl8192de */
> +#define SET_TX_DESC_AGG_ENABLE_DE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
> +#define SET_TX_DESC_PKT_OFFSET_DE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_MACID_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
> +#define SET_TX_DESC_QUEUE_SEL_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
> +#define GET_RX_STATUS_DESC_PAGGR_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
> +#define GET_RX_STATUS_DESC_FAGGR_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
> +#define SET_TX_DESC_NON_QOS_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 16, 1, __val)
> +#define SET_TX_DESC_SEC_TYPE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
> +
> +/*********************** DWORD 2 ***********************/
> +
> +#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
> +#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
> +/* Special macros for rtl8192cu */
> +#define SET_TX_DESC_MORE_FRAG_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
> +#define SET_TX_DESC_AMPDU_DENSITY_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_RSVD_MACID_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(((__pdesc)+8), 24, 5, __val)
> +#define SET_TX_DESC_AGG_ENABLE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+8, 29, 1, __val)
> +
> +/*********************** DWORD 3 ***********************/
> +
> +#define SET_TX_DESC_SEQ(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
> +#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
> +/* Special macros for rtl8192cu */
> +#define GET_RX_DESC_RX_MCS_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
> +#define GET_RX_DESC_RX_HT_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
> +#define GET_RX_DESC_SPLCP_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
> +#define GET_RX_DESC_BW_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
> +#define SET_TX_DESC_SEQ_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
> +#define SET_TX_DESC_PKT_ID_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
> +/* Special macros for rtl8192se */
> +#define GET_RX_STATUS_DESC_RX_MCS_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
> +#define GET_RX_STATUS_DESC_RX_HT_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
> +#define GET_RX_STATUS_DESC_SPLCP_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
> +#define GET_RX_STATUS_DESC_BW_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
> +#define SET_TX_DESC_SEQ_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
> +#define SET_TX_DESC_FRAG(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
> +
> +/*********************** DWORD 4 ***********************/
> +
> +#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
> +#define SET_TX_DESC_QOS(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
> +#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
> +#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
> +#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
> +#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
> +#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
> +#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
> +#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
> +#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
> +#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
> +#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
> +#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
> +#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
> +#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
> +/* Special macros for rtl8192cu */
> +#define SET_TX_DESC_RTS_RATE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
> +#define SET_TX_DESC_QOS_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
> +#define SET_TX_DESC_HWSEQ_EN_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
> +#define SET_TX_DESC_USE_RATE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
> +#define SET_TX_DESC_DISABLE_FB_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
> +#define SET_TX_DESC_CTS2SELF_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
> +#define SET_TX_DESC_RTS_ENABLE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
> +#define SET_TX_DESC_HW_RTS_ENABLE_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
> +#define SET_TX_DESC_DATA_SC_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
> +#define SET_TX_DESC_DATA_BW_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
> +#define SET_TX_DESC_RTS_SHORT_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
> +#define SET_TX_DESC_RTS_BW_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
> +#define SET_TX_DESC_RTS_SC_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
> +#define SET_TX_DESC_RTS_STBC_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_RTS_RATE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 0, 6, __val)
> +#define SET_TX_DESC_TXHT_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 16, 1, __val)
> +#define SET_TX_DESC_CTS_ENABLE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
> +#define SET_TX_DESC_RTS_ENABLE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
> +#define SET_TX_DESC_RA_BRSR_ID_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 13, 3, __val)
> +#define SET_TX_DESC_TX_SHORT_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 17, 1, __val)
> +#define SET_TX_DESC_TX_BANDWIDTH_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
> +#define SET_TX_DESC_TX_SUB_CARRIER_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 19, 2, __val)
> +#define SET_TX_DESC_RTS_SHORT_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
> +#define SET_TX_DESC_RTS_BANDWIDTH_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
> +#define SET_TX_DESC_RTS_SUB_CARRIER_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 27, 2, __val)
> +#define SET_TX_DESC_RTS_STBC_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 29, 2, __val)
> +#define SET_TX_DESC_USER_RATE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+16, 31, 1, __val)
> +
> +/*********************** DWORD 5 ***********************/
> +
> +#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
> +#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
> +#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
> +#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
> +/* Special macros for rtl8192cu */
> +#define GET_RX_DESC_TSFL_CU(__rxdesc) \
> + SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
> +#define SET_TX_DESC_DATA_SHORTGI_CU(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
> +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
> +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_PACKET_ID_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 0, 9, __val)
> +#define SET_TX_DESC_TX_RATE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 9, 6, __val)
> +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+20, 16, 5, __val)
> +#define GET_RX_STATUS_DESC_TSFL_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
> +
> +/*********************** DWORD 6 ***********************/
> +
> +#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
> +/* Special macros for rtl8192cu */
> +#define SET_TX_DESC_MAX_AGG_NUM_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
> +/* Special macros for rtl8192se */
> +#define SET_RX_STATUS__DESC_BUFF_ADDR_SE(__pdesc, __val)\
> + SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
> +
> +/*********************** DWORD 7 ***********************/
> +
> +#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
> +/* Special macros for rtl8192cu */
> +#define SET_TX_DESC_TX_DESC_CHECKSUM_CU(__txdesc, __value) \
> + SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_TX_BUFFER_SIZE_SE(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
> +
> +/*********************** DWORD 8 ***********************/
> +
> +#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
> +
> +#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_TX_BUFFER_ADDRESS_SE(__pdesc, __val)\
> + SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
> +#define GET_TX_DESC_TX_BUFFER_ADDRESS_SE(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
> +
> +/*********************** DWORD 9 ***********************/
> +/* Special macros for rtl8192se */
> +#define SET_TX_DESC_NEXT_DESC_ADDRESS_SE(__pdesc, __val)\
> + SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
> +
> +/*********************** DWORD 10 ***********************/
> +
> +#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
> +
> +/*********************** DWORD 11 ***********************/
> +
> +#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
> +#define SET_RX_DESC_EOR(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
> +#define SET_RX_DESC_OWN(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
> +
> +#define GET_RX_DESC_PAGGR(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
> +#define GET_RX_DESC_FAGGR(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
> +
> +#define GET_RX_DESC_RXMCS(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
> +#define GET_RX_DESC_RXHT(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
> +#define GET_RX_DESC_SPLCP(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
> +#define GET_RX_DESC_BW(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
> +
> +#define GET_RX_DESC_TSFL(__pdesc) \
> + SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
> +
> +#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
> + SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
> +
> +#endif
This patch switches rtl8192cu to use the new macros file.
Signed-off-by: Larry Finger <[email protected]>
---
drivers/net/wireless/rtlwifi/rtl8192cu/mac.c | 6 +-
drivers/net/wireless/rtlwifi/rtl8192cu/trx.c | 193 ++++++++--------
drivers/net/wireless/rtlwifi/rtl8192cu/trx.h | 310 +-------------------------
3 files changed, 102 insertions(+), 407 deletions(-)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index d028f6f..3dcdfd2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -873,9 +873,9 @@ static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
pstats->rx_pwdb_all = pwdb_all;
pstats->rxpower = rx_pwr_all;
pstats->recvsignalpower = rx_pwr_all;
- if (GET_RX_DESC_RX_MCS(pdesc) &&
- GET_RX_DESC_RX_MCS(pdesc) >= DESC92_RATEMCS8 &&
- GET_RX_DESC_RX_MCS(pdesc) <= DESC92_RATEMCS15)
+ if (GET_RX_DESC_RX_MCS_CU(pdesc) &&
+ GET_RX_DESC_RX_MCS_CU(pdesc) >= DESC92_RATEMCS8 &&
+ GET_RX_DESC_RX_MCS_CU(pdesc) <= DESC92_RATEMCS15)
max_spatial_stream = 2;
else
max_spatial_stream = 1;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
index bde3589..5a8cfd6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
@@ -307,40 +307,40 @@ bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
{
struct rx_fwinfo_92c *p_drvinfo;
struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
- u32 phystatus = GET_RX_DESC_PHY_STATUS(pdesc);
+ u32 phystatus = GET_RX_DESC_PHY_STATUS_CU(pdesc);
- stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
- stats->rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(pdesc) *
+ stats->length = (u16) GET_RX_DESC_PKT_LEN_CU(pdesc);
+ stats->rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE_CU(pdesc) *
RX_DRV_INFO_SIZE_UNIT;
- stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
- stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
- stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
+ stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT_CU(pdesc) & 0x03);
+ stats->icv = (u16) GET_RX_DESC_ICV_CU(pdesc);
+ stats->crc = (u16) GET_RX_DESC_CRC32_CU(pdesc);
stats->hwerror = (stats->crc | stats->icv);
- stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
- stats->rate = (u8) GET_RX_DESC_RX_MCS(pdesc);
- stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
- stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
- stats->isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
- && (GET_RX_DESC_FAGGR(pdesc) == 1));
- stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
- stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
+ stats->decrypted = !GET_RX_DESC_SWDEC_CU(pdesc);
+ stats->rate = (u8) GET_RX_DESC_RX_MCS_CU(pdesc);
+ stats->shortpreamble = (u16) GET_RX_DESC_SPLCP_CU(pdesc);
+ stats->isampdu = (bool) (GET_RX_DESC_PAGGR_CU(pdesc) == 1);
+ stats->isampdu = (bool) ((GET_RX_DESC_PAGGR_CU(pdesc) == 1)
+ && (GET_RX_DESC_FAGGR_CU(pdesc) == 1));
+ stats->timestamp_low = GET_RX_DESC_TSFL_CU(pdesc);
+ stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW_CU(pdesc);
rx_status->freq = hw->conf.channel->center_freq;
rx_status->band = hw->conf.channel->band;
- if (GET_RX_DESC_CRC32(pdesc))
+ if (GET_RX_DESC_CRC32_CU(pdesc))
rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
- if (!GET_RX_DESC_SWDEC(pdesc))
+ if (!GET_RX_DESC_SWDEC_CU(pdesc))
rx_status->flag |= RX_FLAG_DECRYPTED;
- if (GET_RX_DESC_BW(pdesc))
+ if (GET_RX_DESC_BW_CU(pdesc))
rx_status->flag |= RX_FLAG_40MHZ;
- if (GET_RX_DESC_RX_HT(pdesc))
+ if (GET_RX_DESC_RX_HT_CU(pdesc))
rx_status->flag |= RX_FLAG_HT;
rx_status->flag |= RX_FLAG_MACTIME_MPDU;
if (stats->decrypted)
rx_status->flag |= RX_FLAG_DECRYPTED;
rx_status->rate_idx = rtlwifi_rate_mapping(hw,
- (bool)GET_RX_DESC_RX_HT(pdesc),
- (u8)GET_RX_DESC_RX_MCS(pdesc));
- rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
+ (bool)GET_RX_DESC_RX_HT_CU(pdesc),
+ (u8)GET_RX_DESC_RX_MCS_CU(pdesc));
+ rx_status->mactime = GET_RX_DESC_TSFL_CU(pdesc);
if (phystatus) {
p_drvinfo = (struct rx_fwinfo_92c *)(pdesc + RTL_RX_DESC_SIZE);
rtl92c_translate_rx_signal_stuff(hw, skb, stats, pdesc,
@@ -374,42 +374,43 @@ static void _rtl_rx_process(struct ieee80211_hw *hw, struct sk_buff *skb)
memset(rx_status, 0, sizeof(*rx_status));
rxdesc = skb->data;
skb_len = skb->len;
- drvinfo_len = (GET_RX_DESC_DRVINFO_SIZE(rxdesc) * RTL_RX_DRV_INFO_UNIT);
- pkt_len = GET_RX_DESC_PKT_LEN(rxdesc);
+ drvinfo_len = (GET_RX_DESC_DRVINFO_SIZE_CU(rxdesc) *
+ RTL_RX_DRV_INFO_UNIT);
+ pkt_len = GET_RX_DESC_PKT_LEN_CU(rxdesc);
/* TODO: Error recovery. drop this skb or something. */
WARN_ON(skb_len < (pkt_len + RTL_RX_DESC_SIZE + drvinfo_len));
- stats.length = (u16) GET_RX_DESC_PKT_LEN(rxdesc);
- stats.rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(rxdesc) *
+ stats.length = (u16) GET_RX_DESC_PKT_LEN_CU(rxdesc);
+ stats.rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE_CU(rxdesc) *
RX_DRV_INFO_SIZE_UNIT;
- stats.rx_bufshift = (u8) (GET_RX_DESC_SHIFT(rxdesc) & 0x03);
- stats.icv = (u16) GET_RX_DESC_ICV(rxdesc);
- stats.crc = (u16) GET_RX_DESC_CRC32(rxdesc);
+ stats.rx_bufshift = (u8) (GET_RX_DESC_SHIFT_CU(rxdesc) & 0x03);
+ stats.icv = (u16) GET_RX_DESC_ICV_CU(rxdesc);
+ stats.crc = (u16) GET_RX_DESC_CRC32_CU(rxdesc);
stats.hwerror = (stats.crc | stats.icv);
- stats.decrypted = !GET_RX_DESC_SWDEC(rxdesc);
- stats.rate = (u8) GET_RX_DESC_RX_MCS(rxdesc);
- stats.shortpreamble = (u16) GET_RX_DESC_SPLCP(rxdesc);
- stats.isampdu = (bool) ((GET_RX_DESC_PAGGR(rxdesc) == 1)
- && (GET_RX_DESC_FAGGR(rxdesc) == 1));
- stats.timestamp_low = GET_RX_DESC_TSFL(rxdesc);
- stats.rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(rxdesc);
+ stats.decrypted = !GET_RX_DESC_SWDEC_CU(rxdesc);
+ stats.rate = (u8) GET_RX_DESC_RX_MCS_CU(rxdesc);
+ stats.shortpreamble = (u16) GET_RX_DESC_SPLCP_CU(rxdesc);
+ stats.isampdu = (bool) ((GET_RX_DESC_PAGGR_CU(rxdesc) == 1)
+ && (GET_RX_DESC_FAGGR_CU(rxdesc) == 1));
+ stats.timestamp_low = GET_RX_DESC_TSFL_CU(rxdesc);
+ stats.rx_is40Mhzpacket = (bool) GET_RX_DESC_BW_CU(rxdesc);
/* TODO: is center_freq changed when doing scan? */
/* TODO: Shall we add protection or just skip those two step? */
rx_status->freq = hw->conf.channel->center_freq;
rx_status->band = hw->conf.channel->band;
- if (GET_RX_DESC_CRC32(rxdesc))
+ if (GET_RX_DESC_CRC32_CU(rxdesc))
rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
- if (!GET_RX_DESC_SWDEC(rxdesc))
+ if (!GET_RX_DESC_SWDEC_CU(rxdesc))
rx_status->flag |= RX_FLAG_DECRYPTED;
- if (GET_RX_DESC_BW(rxdesc))
+ if (GET_RX_DESC_BW_CU(rxdesc))
rx_status->flag |= RX_FLAG_40MHZ;
- if (GET_RX_DESC_RX_HT(rxdesc))
+ if (GET_RX_DESC_RX_HT_CU(rxdesc))
rx_status->flag |= RX_FLAG_HT;
/* Data rate */
rx_status->rate_idx = rtlwifi_rate_mapping(hw,
- (bool)GET_RX_DESC_RX_HT(rxdesc),
- (u8)GET_RX_DESC_RX_MCS(rxdesc));
+ (bool)GET_RX_DESC_RX_HT_CU(rxdesc),
+ (u8)GET_RX_DESC_RX_MCS_CU(rxdesc));
/* There is a phy status after this rx descriptor. */
- if (GET_RX_DESC_PHY_STATUS(rxdesc)) {
+ if (GET_RX_DESC_PHY_STATUS_CU(rxdesc)) {
p_drvinfo = (struct rx_fwinfo_92c *)(rxdesc + RTL_RX_DESC_SIZE);
rtl92c_translate_rx_signal_stuff(hw, skb, &stats,
(struct rx_desc_92c *)rxdesc, p_drvinfo);
@@ -486,10 +487,10 @@ static void _rtl_tx_desc_checksum(u8 *txdesc)
u32 index;
/* Clear first */
- SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, 0);
+ SET_TX_DESC_TX_DESC_CHECKSUM_CU(txdesc, 0);
for (index = 0; index < 16; index++)
checksum = checksum ^ (*(ptr + index));
- SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, cpu_to_le16(checksum));
+ SET_TX_DESC_TX_DESC_CHECKSUM_CU(txdesc, cpu_to_le16(checksum));
}
void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
@@ -519,52 +520,52 @@ void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
memset(txdesc, 0, RTL_TX_HEADER_SIZE);
SET_TX_DESC_PKT_SIZE(txdesc, pktlen);
SET_TX_DESC_LINIP(txdesc, 0);
- SET_TX_DESC_PKT_OFFSET(txdesc, RTL_DUMMY_OFFSET);
+ SET_TX_DESC_PKT_OFFSET_CU(txdesc, RTL_DUMMY_OFFSET);
SET_TX_DESC_OFFSET(txdesc, RTL_TX_HEADER_SIZE);
SET_TX_DESC_TX_RATE(txdesc, tcb_desc->hw_rate);
if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble)
- SET_TX_DESC_DATA_SHORTGI(txdesc, 1);
+ SET_TX_DESC_DATA_SHORTGI_CU(txdesc, 1);
if (mac->tids[tid].agg.agg_state == RTL_AGG_ON &&
info->flags & IEEE80211_TX_CTL_AMPDU) {
- SET_TX_DESC_AGG_ENABLE(txdesc, 1);
- SET_TX_DESC_MAX_AGG_NUM(txdesc, 0x14);
+ SET_TX_DESC_AGG_ENABLE_CU(txdesc, 1);
+ SET_TX_DESC_MAX_AGG_NUM_CU(txdesc, 0x14);
} else {
- SET_TX_DESC_AGG_BREAK(txdesc, 1);
+ SET_TX_DESC_AGG_BREAK_CU(txdesc, 1);
}
- SET_TX_DESC_SEQ(txdesc, seq_number);
- SET_TX_DESC_RTS_ENABLE(txdesc, ((tcb_desc->rts_enable &&
+ SET_TX_DESC_SEQ_CU(txdesc, seq_number);
+ SET_TX_DESC_RTS_ENABLE_CU(txdesc, ((tcb_desc->rts_enable &&
!tcb_desc->cts_enable) ? 1 : 0));
- SET_TX_DESC_HW_RTS_ENABLE(txdesc, ((tcb_desc->rts_enable ||
+ SET_TX_DESC_HW_RTS_ENABLE_CU(txdesc, ((tcb_desc->rts_enable ||
tcb_desc->cts_enable) ? 1 : 0));
- SET_TX_DESC_CTS2SELF(txdesc, ((tcb_desc->cts_enable) ? 1 : 0));
- SET_TX_DESC_RTS_STBC(txdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
- SET_TX_DESC_RTS_RATE(txdesc, tcb_desc->rts_rate);
- SET_TX_DESC_RTS_BW(txdesc, 0);
- SET_TX_DESC_RTS_SC(txdesc, tcb_desc->rts_sc);
- SET_TX_DESC_RTS_SHORT(txdesc,
+ SET_TX_DESC_CTS2SELF_CU(txdesc, ((tcb_desc->cts_enable) ? 1 : 0));
+ SET_TX_DESC_RTS_STBC_CU(txdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
+ SET_TX_DESC_RTS_RATE_CU(txdesc, tcb_desc->rts_rate);
+ SET_TX_DESC_RTS_BW_CU(txdesc, 0);
+ SET_TX_DESC_RTS_SC_CU(txdesc, tcb_desc->rts_sc);
+ SET_TX_DESC_RTS_SHORT_CU(txdesc,
((tcb_desc->rts_rate <= DESC92_RATE54M) ?
(tcb_desc->rts_use_shortpreamble ? 1 : 0)
: (tcb_desc->rts_use_shortgi ? 1 : 0)));
if (mac->bw_40) {
if (rate_flag & IEEE80211_TX_RC_DUP_DATA) {
- SET_TX_DESC_DATA_BW(txdesc, 1);
- SET_TX_DESC_DATA_SC(txdesc, 3);
+ SET_TX_DESC_DATA_BW_CU(txdesc, 1);
+ SET_TX_DESC_DATA_SC_CU(txdesc, 3);
} else if(rate_flag & IEEE80211_TX_RC_40_MHZ_WIDTH){
- SET_TX_DESC_DATA_BW(txdesc, 1);
- SET_TX_DESC_DATA_SC(txdesc, mac->cur_40_prime_sc);
+ SET_TX_DESC_DATA_BW_CU(txdesc, 1);
+ SET_TX_DESC_DATA_SC_CU(txdesc, mac->cur_40_prime_sc);
} else {
- SET_TX_DESC_DATA_BW(txdesc, 0);
- SET_TX_DESC_DATA_SC(txdesc, 0);
+ SET_TX_DESC_DATA_BW_CU(txdesc, 0);
+ SET_TX_DESC_DATA_SC_CU(txdesc, 0);
}
} else {
- SET_TX_DESC_DATA_BW(txdesc, 0);
- SET_TX_DESC_DATA_SC(txdesc, 0);
+ SET_TX_DESC_DATA_BW_CU(txdesc, 0);
+ SET_TX_DESC_DATA_SC_CU(txdesc, 0);
}
rcu_read_lock();
sta = ieee80211_find_sta(mac->vif, mac->bssid);
if (sta) {
u8 ampdu_density = sta->ht_cap.ampdu_density;
- SET_TX_DESC_AMPDU_DENSITY(txdesc, ampdu_density);
+ SET_TX_DESC_AMPDU_DENSITY_CU(txdesc, ampdu_density);
}
rcu_read_unlock();
if (info->control.hw_key) {
@@ -573,46 +574,46 @@ void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
case WLAN_CIPHER_SUITE_WEP40:
case WLAN_CIPHER_SUITE_WEP104:
case WLAN_CIPHER_SUITE_TKIP:
- SET_TX_DESC_SEC_TYPE(txdesc, 0x1);
+ SET_TX_DESC_SEC_TYPE_CU(txdesc, 0x1);
break;
case WLAN_CIPHER_SUITE_CCMP:
- SET_TX_DESC_SEC_TYPE(txdesc, 0x3);
+ SET_TX_DESC_SEC_TYPE_CU(txdesc, 0x3);
break;
default:
- SET_TX_DESC_SEC_TYPE(txdesc, 0x0);
+ SET_TX_DESC_SEC_TYPE_CU(txdesc, 0x0);
break;
}
}
- SET_TX_DESC_PKT_ID(txdesc, 0);
- SET_TX_DESC_QUEUE_SEL(txdesc, fw_qsel);
- SET_TX_DESC_DATA_RATE_FB_LIMIT(txdesc, 0x1F);
- SET_TX_DESC_RTS_RATE_FB_LIMIT(txdesc, 0xF);
- SET_TX_DESC_DISABLE_FB(txdesc, 0);
- SET_TX_DESC_USE_RATE(txdesc, tcb_desc->use_driver_rate ? 1 : 0);
+ SET_TX_DESC_PKT_ID_CU(txdesc, 0);
+ SET_TX_DESC_QUEUE_SEL_CU(txdesc, fw_qsel);
+ SET_TX_DESC_DATA_RATE_FB_LIMIT_CU(txdesc, 0x1F);
+ SET_TX_DESC_RTS_RATE_FB_LIMIT_CU(txdesc, 0xF);
+ SET_TX_DESC_DISABLE_FB_CU(txdesc, 0);
+ SET_TX_DESC_USE_RATE_CU(txdesc, tcb_desc->use_driver_rate ? 1 : 0);
if (ieee80211_is_data_qos(fc)) {
if (mac->rdg_en) {
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
"Enable RDG function\n");
- SET_TX_DESC_RDG_ENABLE(txdesc, 1);
+ SET_TX_DESC_RDG_ENABLE_CU(txdesc, 1);
SET_TX_DESC_HTC(txdesc, 1);
}
}
if (rtlpriv->dm.useramask) {
- SET_TX_DESC_RATE_ID(txdesc, tcb_desc->ratr_index);
- SET_TX_DESC_MACID(txdesc, tcb_desc->mac_id);
+ SET_TX_DESC_RATE_ID_CU(txdesc, tcb_desc->ratr_index);
+ SET_TX_DESC_MACID_CU(txdesc, tcb_desc->mac_id);
} else {
- SET_TX_DESC_RATE_ID(txdesc, 0xC + tcb_desc->ratr_index);
- SET_TX_DESC_MACID(txdesc, tcb_desc->ratr_index);
+ SET_TX_DESC_RATE_ID_CU(txdesc, 0xC + tcb_desc->ratr_index);
+ SET_TX_DESC_MACID_CU(txdesc, tcb_desc->ratr_index);
}
if ((!ieee80211_is_data_qos(fc)) && ppsc->leisure_ps &&
ppsc->fwctrl_lps) {
- SET_TX_DESC_HWSEQ_EN(txdesc, 1);
- SET_TX_DESC_PKT_ID(txdesc, 8);
+ SET_TX_DESC_HWSEQ_EN_CU(txdesc, 1);
+ SET_TX_DESC_PKT_ID_CU(txdesc, 8);
if (!defaultadapter)
- SET_TX_DESC_QOS(txdesc, 1);
+ SET_TX_DESC_QOS_CU(txdesc, 1);
}
if (ieee80211_has_morefrags(fc))
- SET_TX_DESC_MORE_FRAG(txdesc, 1);
+ SET_TX_DESC_MORE_FRAG_CU(txdesc, 1);
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
SET_TX_DESC_BMC(txdesc, 1);
@@ -630,16 +631,16 @@ void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
SET_TX_DESC_LAST_SEG(pDesc, 1); /* bLastSeg; */
SET_TX_DESC_OFFSET(pDesc, RTL_TX_HEADER_SIZE); /* Offset = 32 */
SET_TX_DESC_PKT_SIZE(pDesc, buffer_len); /* Buffer size + command hdr */
- SET_TX_DESC_QUEUE_SEL(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
+ SET_TX_DESC_QUEUE_SEL_CU(pDesc, QSLT_MGNT); /* Fixed Mgnt queue */
/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error
* vlaue by Hw. */
if (bIsPsPoll) {
- SET_TX_DESC_NAV_USE_HDR(pDesc, 1);
+ SET_TX_DESC_NAV_USE_HDR_CU(pDesc, 1);
} else {
- SET_TX_DESC_HWSEQ_EN(pDesc, 1); /* Hw set sequence number */
- SET_TX_DESC_PKT_ID(pDesc, 0x100); /* set bit3 to 1. */
+ SET_TX_DESC_HWSEQ_EN_CU(pDesc, 1); /* Hw set sequence number */
+ SET_TX_DESC_PKT_ID_CU(pDesc, 0x100); /* set bit3 to 1. */
}
- SET_TX_DESC_USE_RATE(pDesc, 1); /* use data rate which is set by Sw */
+ SET_TX_DESC_USE_RATE_CU(pDesc, 1); /* use data rate set by Sw */
SET_TX_DESC_OWN(pDesc, 1);
SET_TX_DESC_TX_RATE(pDesc, DESC92_RATE1M);
_rtl_tx_desc_checksum(pDesc);
@@ -658,22 +659,22 @@ void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
if (firstseg)
SET_TX_DESC_OFFSET(pdesc, RTL_TX_HEADER_SIZE);
SET_TX_DESC_TX_RATE(pdesc, DESC92_RATE1M);
- SET_TX_DESC_SEQ(pdesc, 0);
+ SET_TX_DESC_SEQ_CU(pdesc, 0);
SET_TX_DESC_LINIP(pdesc, 0);
- SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
+ SET_TX_DESC_QUEUE_SEL_CU(pdesc, fw_queue);
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
- SET_TX_DESC_RATE_ID(pdesc, 7);
+ SET_TX_DESC_RATE_ID_CU(pdesc, 7);
SET_TX_DESC_MACID(pdesc, 0);
SET_TX_DESC_OWN(pdesc, 1);
SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
SET_TX_DESC_OFFSET(pdesc, 0x20);
- SET_TX_DESC_USE_RATE(pdesc, 1);
+ SET_TX_DESC_USE_RATE_CU(pdesc, 1);
if (!ieee80211_is_data_qos(fc)) {
- SET_TX_DESC_HWSEQ_EN(pdesc, 1);
- SET_TX_DESC_PKT_ID(pdesc, 8);
+ SET_TX_DESC_HWSEQ_EN_CU(pdesc, 1);
+ SET_TX_DESC_PKT_ID_CU(pdesc, 8);
}
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C Tx Cmd Content",
pdesc, RTL_TX_DESC_SIZE);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
index 332b06e..40fef00 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
@@ -30,6 +30,8 @@
#ifndef __RTL92CU_TRX_H__
#define __RTL92CU_TRX_H__
+#include "../macros.h"
+
#define RTL92C_USB_BULK_IN_NUM 1
#define RTL92C_NUM_RX_URBS 8
#define RTL92C_NUM_TX_URBS 32
@@ -96,314 +98,6 @@ struct rx_drv_info_92c {
u8 reserve:4;
} __packed;
-/* Define a macro that takes a le32 word, converts it to host ordering,
- * right shifts by a specified count, creates a mask of the specified
- * bit count, and extracts that number of bits.
- */
-
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __bits) \
- ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
- BIT_LEN_MASK_32(__bits))
-
-/* Define a macro that clears a bit field in an le32 word and
- * sets the specified value into that bit field. The resulting
- * value remains in le32 ordering; however, it is properly converted
- * to host ordering for the clear and set operations before conversion
- * back to le32.
- */
-
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
- (*(__le32 *)(__pdesc) = \
- (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
- (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
- (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
-
-/* macros to read various fields in RX descriptor */
-
-/* DWORD 0 */
-#define GET_RX_DESC_PKT_LEN(__rxdesc) \
- SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
-#define GET_RX_DESC_CRC32(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
-#define GET_RX_DESC_ICV(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
-#define GET_RX_DESC_DRVINFO_SIZE(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
-#define GET_RX_DESC_SECURITY(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 20, 3)
-#define GET_RX_DESC_QOS(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 23, 1)
-#define GET_RX_DESC_SHIFT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
-#define GET_RX_DESC_PHY_STATUS(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
-#define GET_RX_DESC_SWDEC(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
-#define GET_RX_DESC_LAST_SEG(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 28, 1)
-#define GET_RX_DESC_FIRST_SEG(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 29, 1)
-#define GET_RX_DESC_EOR(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 30, 1)
-#define GET_RX_DESC_OWN(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc, 31, 1)
-
-/* DWORD 1 */
-#define GET_RX_DESC_MACID(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 0, 5)
-#define GET_RX_DESC_TID(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 5, 4)
-#define GET_RX_DESC_PAGGR(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
-#define GET_RX_DESC_FAGGR(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
-#define GET_RX_DESC_A1_FIT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 16, 4)
-#define GET_RX_DESC_A2_FIT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 20, 4)
-#define GET_RX_DESC_PAM(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 24, 1)
-#define GET_RX_DESC_PWR(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 25, 1)
-#define GET_RX_DESC_MORE_DATA(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 26, 1)
-#define GET_RX_DESC_MORE_FRAG(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 27, 1)
-#define GET_RX_DESC_TYPE(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 28, 2)
-#define GET_RX_DESC_MC(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 30, 1)
-#define GET_RX_DESC_BC(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+4, 31, 1)
-
-/* DWORD 2 */
-#define GET_RX_DESC_SEQ(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+8, 0, 12)
-#define GET_RX_DESC_FRAG(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+8, 12, 4)
-#define GET_RX_DESC_USB_AGG_PKTNUM(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+8, 16, 8)
-#define GET_RX_DESC_NEXT_IND(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+8, 30, 1)
-
-/* DWORD 3 */
-#define GET_RX_DESC_RX_MCS(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
-#define GET_RX_DESC_RX_HT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
-#define GET_RX_DESC_AMSDU(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 7, 1)
-#define GET_RX_DESC_SPLCP(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
-#define GET_RX_DESC_BW(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
-#define GET_RX_DESC_HTC(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 10, 1)
-#define GET_RX_DESC_TCP_CHK_RPT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 11, 1)
-#define GET_RX_DESC_IP_CHK_RPT(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 12, 1)
-#define GET_RX_DESC_TCP_CHK_VALID(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 13, 1)
-#define GET_RX_DESC_HWPC_ERR(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 14, 1)
-#define GET_RX_DESC_HWPC_IND(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 15, 1)
-#define GET_RX_DESC_IV0(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+12, 16, 16)
-
-/* DWORD 4 */
-#define GET_RX_DESC_IV1(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+16, 0, 32)
-
-/* DWORD 5 */
-#define GET_RX_DESC_TSFL(__rxdesc) \
- SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
-
-/*======================= tx desc ============================================*/
-
-/* macros to set various fields in TX descriptor */
-
-/* Dword 0 */
-#define SET_TX_DESC_PKT_SIZE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 0, 16, __value)
-#define SET_TX_DESC_OFFSET(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 16, 8, __value)
-#define SET_TX_DESC_BMC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 24, 1, __value)
-#define SET_TX_DESC_HTC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 25, 1, __value)
-#define SET_TX_DESC_LAST_SEG(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 26, 1, __value)
-#define SET_TX_DESC_FIRST_SEG(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 27, 1, __value)
-#define SET_TX_DESC_LINIP(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 28, 1, __value)
-#define SET_TX_DESC_NO_ACM(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 29, 1, __value)
-#define SET_TX_DESC_GF(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 30, 1, __value)
-#define SET_TX_DESC_OWN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc, 31, 1, __value)
-
-
-/* Dword 1 */
-#define SET_TX_DESC_MACID(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
-#define SET_TX_DESC_AGG_ENABLE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
-#define SET_TX_DESC_AGG_BREAK(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
-#define SET_TX_DESC_RDG_ENABLE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
-#define SET_TX_DESC_QUEUE_SEL(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
-#define SET_TX_DESC_RDG_NAV_EXT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 13, 1, __value)
-#define SET_TX_DESC_LSIG_TXOP_EN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 14, 1, __value)
-#define SET_TX_DESC_PIFS(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 15, 1, __value)
-#define SET_TX_DESC_RATE_ID(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
-#define SET_TX_DESC_RA_BRSR_ID(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
-#define SET_TX_DESC_NAV_USE_HDR(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
-#define SET_TX_DESC_EN_DESC_ID(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 21, 1, __value)
-#define SET_TX_DESC_SEC_TYPE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
-#define SET_TX_DESC_PKT_OFFSET(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
-
-/* Dword 2 */
-#define SET_TX_DESC_RTS_RC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 0, 6, __value)
-#define SET_TX_DESC_DATA_RC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 6, 6, __value)
-#define SET_TX_DESC_BAR_RTY_TH(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 14, 2, __value)
-#define SET_TX_DESC_MORE_FRAG(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
-#define SET_TX_DESC_RAW(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 18, 1, __value)
-#define SET_TX_DESC_CCX(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 19, 1, __value)
-#define SET_TX_DESC_AMPDU_DENSITY(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
-#define SET_TX_DESC_ANTSEL_A(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 24, 1, __value)
-#define SET_TX_DESC_ANTSEL_B(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 25, 1, __value)
-#define SET_TX_DESC_TX_ANT_CCK(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 26, 2, __value)
-#define SET_TX_DESC_TX_ANTL(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 28, 2, __value)
-#define SET_TX_DESC_TX_ANT_HT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+8, 30, 2, __value)
-
-/* Dword 3 */
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+12, 0, 8, __value)
-#define SET_TX_DESC_TAIL_PAGE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+12, 8, 8, __value)
-#define SET_TX_DESC_SEQ(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
-#define SET_TX_DESC_PKT_ID(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
-
-/* Dword 4 */
-#define SET_TX_DESC_RTS_RATE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
-#define SET_TX_DESC_AP_DCFE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 5, 1, __value)
-#define SET_TX_DESC_QOS(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
-#define SET_TX_DESC_HWSEQ_EN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
-#define SET_TX_DESC_USE_RATE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
-#define SET_TX_DESC_DISABLE_RTS_FB(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 9, 1, __value)
-#define SET_TX_DESC_DISABLE_FB(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
-#define SET_TX_DESC_CTS2SELF(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
-#define SET_TX_DESC_RTS_ENABLE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
-#define SET_TX_DESC_HW_RTS_ENABLE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
-#define SET_TX_DESC_WAIT_DCTS(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 18, 1, __value)
-#define SET_TX_DESC_CTS2AP_EN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 19, 1, __value)
-#define SET_TX_DESC_DATA_SC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
-#define SET_TX_DESC_DATA_STBC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 22, 2, __value)
-#define SET_TX_DESC_DATA_SHORT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 24, 1, __value)
-#define SET_TX_DESC_DATA_BW(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
-#define SET_TX_DESC_RTS_SHORT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
-#define SET_TX_DESC_RTS_BW(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
-#define SET_TX_DESC_RTS_SC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
-#define SET_TX_DESC_RTS_STBC(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
-
-/* Dword 5 */
-#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
-#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
-#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+20, 17, 1, __value)
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+20, 18, 6, __value)
-#define SET_TX_DESC_USB_TXAGG_NUM(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+20, 24, 8, __value)
-
-/* Dword 6 */
-#define SET_TX_DESC_TXAGC_A(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 0, 5, __value)
-#define SET_TX_DESC_TXAGC_B(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 5, 5, __value)
-#define SET_TX_DESC_USB_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 10, 1, __value)
-#define SET_TX_DESC_MAX_AGG_NUM(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
-#define SET_TX_DESC_MCSG1_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 16, 4, __value)
-#define SET_TX_DESC_MCSG2_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 20, 4, __value)
-#define SET_TX_DESC_MCSG3_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 24, 4, __value)
-#define SET_TX_DESC_MCSG7_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+24, 28, 4, __value)
-
-/* Dword 7 */
-#define SET_TX_DESC_TX_DESC_CHECKSUM(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
-#define SET_TX_DESC_MCSG4_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+28, 16, 4, __value)
-#define SET_TX_DESC_MCSG5_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+28, 20, 4, __value)
-#define SET_TX_DESC_MCSG6_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+28, 24, 4, __value)
-#define SET_TX_DESC_MCSG15_MAX_LEN(__txdesc, __value) \
- SET_BITS_OFFSET_LE(__txdesc+28, 28, 4, __value)
-
-
int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw);
u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index);
bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
--
1.7.7
Larry Finger <[email protected]> :
> On 01/11/2012 06:27 PM, Joe Perches wrote:
[...]
> >static inline u32 le32p_to_cpu_shift_and_mask(__le32 *desc, int shift, u32 mask)
> >{
> > return (le32_to_cpu(*desc)>> shift)& BIT_LEN_MASK_32(mask);
> >}
>
> I need to think about this one some more.
Joe only told a part of the story here : this change should eventually go
along a definition of the descriptors as a __leXY struct and a specific
registers / bits definition. It will be a bit tedious.
[...]
> >I don't see how centralizing these non-shared
> >macro names helps.
> >
> >Maybe if the code is actually common, have a
> >separate #include for each card with common
> >named #defines as appropriate.
>
> The idea of centralizing the non-shared names was to have all these
> macros in one place. If any need to be changes, that one file will
> have all of them.
It is paid at the price of the giant #include file and some irrelevant
code pollution in chipset-dedicated parts of the driver. As the main
driver maintainer, you may not win much -if anything- in return.
Joe's suggestion can help with factoring out the code while exhibiting
the differences in the data layout (i.e hardware registers). It is not
automatic though.
--
Ueimor
This patch switches rtl8192de to use the new macros file.
Signed-off-by: Larry Finger <[email protected]>
---
drivers/net/wireless/rtlwifi/rtl8192de/trx.c | 4 +-
drivers/net/wireless/rtlwifi/rtl8192de/trx.h | 499 +-------------------------
2 files changed, 4 insertions(+), 499 deletions(-)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
index 9aacd2f..d3be745 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
@@ -596,7 +596,7 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
}
if (firstseg) {
if (rtlhal->earlymode_enable) {
- SET_TX_DESC_PKT_OFFSET(pdesc, 1);
+ SET_TX_DESC_PKT_OFFSET_DE(pdesc, 1);
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
EM_HDR_LEN);
if (ptcb_desc->empkt_num) {
@@ -622,7 +622,7 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
- SET_TX_DESC_AGG_ENABLE(pdesc, 1);
+ SET_TX_DESC_AGG_ENABLE_DE(pdesc, 1);
SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
}
SET_TX_DESC_SEQ(pdesc, seq_number);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
index 0dc736c..c08b98e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
@@ -30,6 +30,8 @@
#ifndef __RTL92DE_TRX_H__
#define __RTL92DE_TRX_H__
+#include "../macros.h"
+
#define TX_DESC_SIZE 64
#define TX_DESC_AGGR_SUBFRAME_SIZE 32
@@ -40,503 +42,6 @@
#define USB_HWDESC_HEADER_LEN 32
#define CRCLENGTH 4
-/* Define a macro that takes a le32 word, converts it to host ordering,
- * right shifts by a specified count, creates a mask of the specified
- * bit count, and extracts that number of bits.
- */
-
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
- ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
- BIT_LEN_MASK_32(__mask))
-
-/* Define a macro that clears a bit field in an le32 word and
- * sets the specified value into that bit field. The resulting
- * value remains in le32 ordering; however, it is properly converted
- * to host ordering for the clear and set operations before conversion
- * back to le32.
- */
-
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
- (*(__le32 *)(__pdesc) = \
- (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
- (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
- (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
-
-/* macros to read/write various fields in RX or TX descriptors */
-
-#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
-#define SET_TX_DESC_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
-#define SET_TX_DESC_BMC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
-#define SET_TX_DESC_HTC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
-#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
-#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
-#define SET_TX_DESC_LINIP(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
-#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
-#define SET_TX_DESC_GF(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_TX_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_TX_DESC_PKT_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 0, 16)
-#define GET_TX_DESC_OFFSET(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 16, 8)
-#define GET_TX_DESC_BMC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 24, 1)
-#define GET_TX_DESC_HTC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 25, 1)
-#define GET_TX_DESC_LAST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 26, 1)
-#define GET_TX_DESC_FIRST_SEG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 27, 1)
-#define GET_TX_DESC_LINIP(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 28, 1)
-#define GET_TX_DESC_NO_ACM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 29, 1)
-#define GET_TX_DESC_GF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 30, 1)
-#define GET_TX_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-#define SET_TX_DESC_MACID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
-#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
-#define SET_TX_DESC_BK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
-#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
-#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
-#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
-#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
-#define SET_TX_DESC_PIFS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
-#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
-#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
-#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
-#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
-#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
-
-#define GET_TX_DESC_MACID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
-#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
-#define GET_TX_DESC_AGG_BREAK(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
-#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
-#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
-#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
-#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
-#define GET_TX_DESC_PIFS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
-#define GET_TX_DESC_RATE_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
-#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
-#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
-#define GET_TX_DESC_SEC_TYPE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
-#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
-
-#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
-#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
-#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
-#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
-#define SET_TX_DESC_RAW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
-#define SET_TX_DESC_CCX(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
-#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
-#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
-#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
-#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
-#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
-#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
-
-#define GET_TX_DESC_RTS_RC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
-#define GET_TX_DESC_DATA_RC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
-#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
-#define GET_TX_DESC_MORE_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
-#define GET_TX_DESC_RAW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
-#define GET_TX_DESC_CCX(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
-#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
-#define GET_TX_DESC_ANTSEL_A(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
-#define GET_TX_DESC_ANTSEL_B(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
-#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
-#define GET_TX_DESC_TX_ANTL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
-#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
-
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
-#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
-#define SET_TX_DESC_SEQ(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
-#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
-
-#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
-#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
-#define GET_TX_DESC_SEQ(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
-#define GET_TX_DESC_PKT_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
-
-#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
-#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
-#define SET_TX_DESC_QOS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
-#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
-#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
-#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
-#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
-#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
-#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
-#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
-#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
-#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
-#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
-#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
-#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
-#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
-#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
-#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
-#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
-#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
-#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
-
-#define GET_TX_DESC_RTS_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
-#define GET_TX_DESC_AP_DCFE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
-#define GET_TX_DESC_QOS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
-#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
-#define GET_TX_DESC_USE_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
-#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
-#define GET_TX_DESC_DISABLE_FB(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
-#define GET_TX_DESC_CTS2SELF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
-#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
-#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
-#define GET_TX_DESC_PORT_ID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
-#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
-#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
-#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
-#define GET_TX_DESC_TX_STBC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
-#define GET_TX_DESC_DATA_SHORT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
-#define GET_TX_DESC_DATA_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
-#define GET_TX_DESC_RTS_SHORT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
-#define GET_TX_DESC_RTS_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
-#define GET_TX_DESC_RTS_SC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
-#define GET_TX_DESC_RTS_STBC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
-
-#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
-#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
-#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
-#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
-
-#define GET_TX_DESC_TX_RATE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
-#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
-#define GET_TX_DESC_CCX_TAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
-#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
-#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
-#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
-#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
-#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
-
-#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
-#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
-#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
-#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
-#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
-#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
-#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
-#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
-
-#define GET_TX_DESC_TXAGC_A(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
-#define GET_TX_DESC_TXAGC_B(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
-#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
-#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
-#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
-#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
-#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
-#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
-
-#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
-#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
-#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
-#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
-#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
-
-#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
-#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
-#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
-#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
-#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
-
-#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
-#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
-
-#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
-#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
-
-#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
-#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
-
-#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
-#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
-
-#define GET_RX_DESC_PKT_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 0, 14)
-#define GET_RX_DESC_CRC32(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 14, 1)
-#define GET_RX_DESC_ICV(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 15, 1)
-#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 16, 4)
-#define GET_RX_DESC_SECURITY(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 20, 3)
-#define GET_RX_DESC_QOS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 23, 1)
-#define GET_RX_DESC_SHIFT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 24, 2)
-#define GET_RX_DESC_PHYST(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 26, 1)
-#define GET_RX_DESC_SWDEC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 27, 1)
-#define GET_RX_DESC_LS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 28, 1)
-#define GET_RX_DESC_FS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 29, 1)
-#define GET_RX_DESC_EOR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 30, 1)
-#define GET_RX_DESC_OWN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc, 31, 1)
-
-#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
-#define SET_RX_DESC_EOR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
-#define SET_RX_DESC_OWN(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
-
-#define GET_RX_DESC_MACID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
-#define GET_RX_DESC_TID(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
-#define GET_RX_DESC_HWRSVD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
-#define GET_RX_DESC_PAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
-#define GET_RX_DESC_FAGGR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
-#define GET_RX_DESC_A1_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
-#define GET_RX_DESC_A2_FIT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
-#define GET_RX_DESC_PAM(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
-#define GET_RX_DESC_PWR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
-#define GET_RX_DESC_MD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
-#define GET_RX_DESC_MF(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
-#define GET_RX_DESC_TYPE(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
-#define GET_RX_DESC_MC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
-#define GET_RX_DESC_BC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
-#define GET_RX_DESC_SEQ(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
-#define GET_RX_DESC_FRAG(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
-#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
-#define GET_RX_DESC_NEXT_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
-#define GET_RX_DESC_RSVD(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
-
-#define GET_RX_DESC_RXMCS(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
-#define GET_RX_DESC_RXHT(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
-#define GET_RX_DESC_SPLCP(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
-#define GET_RX_DESC_BW(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
-#define GET_RX_DESC_HTC(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
-#define GET_RX_DESC_HWPC_ERR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
-#define GET_RX_DESC_HWPC_IND(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
-#define GET_RX_DESC_IV0(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
-
-#define GET_RX_DESC_IV1(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
-#define GET_RX_DESC_TSFL(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
-
-#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
-#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
- SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
-
-#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
-#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
- SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
-
-#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
-do { \
- if (_size > TX_DESC_NEXT_DESC_OFFSET) \
- memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
- else \
- memset((void *)__pdesc, 0, _size); \
-} while (0);
-
/* For 92D early mode */
#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
SET_BITS_OFFSET_LE(__paddr, 0, 3, __value)
--
1.7.7