This patch fixes these checkpatch.pl errors around a single switch-case block:
ERROR: switch and case should be at the same indent
ERROR: trailing statements should be on next line
More specifically, the fix has been applied to the five occurances of the errors listed below.
ERROR: switch and case should be at the same indent
#1100: FILE: adm8211.c:1100:
+ switch (cline) {
[...]
+ default: reg |= (0x0 << 14);
ERROR: trailing statements should be on next line
#1101: FILE: adm8211.c:1101:
+ case 0x8: reg |= (0x1 << 14);
ERROR: trailing statements should be on next line
#1103: FILE: adm8211.c:1103:
+ case 0x16: reg |= (0x2 << 14);
ERROR: trailing statements should be on next line
#1105: FILE: adm8211.c:1105:
+ case 0x32: reg |= (0x3 << 14);
ERROR: trailing statements should be on next line
#1107: FILE: adm8211.c:1107:
+ default: reg |= (0x0 << 14);
Signed-off-by: Okash Khawaja <[email protected]>
---
drivers/net/wireless/adm8211.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
index f07a618..058fb4b 100644
--- a/drivers/net/wireless/adm8211.c
+++ b/drivers/net/wireless/adm8211.c
@@ -1098,14 +1098,18 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
switch (cline) {
- case 0x8: reg |= (0x1 << 14);
- break;
- case 0x16: reg |= (0x2 << 14);
- break;
- case 0x32: reg |= (0x3 << 14);
- break;
- default: reg |= (0x0 << 14);
- break;
+ case 0x8:
+ reg |= (0x1 << 14);
+ break;
+ case 0x16:
+ reg |= (0x2 << 14);
+ break;
+ case 0x32:
+ reg |= (0x3 << 14);
+ break;
+ default:
+ reg |= (0x0 << 14);
+ break;
}
}
--
1.9.1
> diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
> index f07a618..058fb4b 100644
> --- a/drivers/net/wireless/adm8211.c
> +++ b/drivers/net/wireless/adm8211.c
> @@ -1098,14 +1098,18 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
> pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
>
> switch (cline) {
> - case 0x8: reg |= (0x1 << 14);
> - break;
> - case 0x16: reg |= (0x2 << 14);
> - break;
> - case 0x32: reg |= (0x3 << 14);
> - break;
> - default: reg |= (0x0 << 14);
> - break;
> + case 0x8:
> + reg |= (0x1 << 14);
> + break;
> + case 0x16:
> + reg |= (0x2 << 14);
> + break;
> + case 0x32:
> + reg |= (0x3 << 14);
> + break;
> + default:
> + reg |= (0x0 << 14);
> + break;
> }
> }
>
Those 0x16/0x32 hexadecimal case-selectors looking suspiciously like
decimal bits need a comment if they are in fact correct, which I doubt.
Cheers,
Peter
On Tue, 2015-05-05 at 14:03 +0200, Peter Rosin wrote:
> > diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
[]
> > @@ -1098,14 +1098,18 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
> > pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
> >
> > switch (cline) {
[]
> > + case 0x8:
> > + reg |= (0x1 << 14);
> > + break;
> > + case 0x16:
> > + reg |= (0x2 << 14);
> > + break;
> > + case 0x32:
> > + reg |= (0x3 << 14);
> > + break;
> > + default:
> > + reg |= (0x0 << 14);
> > + break;
> > }
> > }
> >
>
> Those 0x16/0x32 hexadecimal case-selectors looking suspiciously like
> decimal bits need a comment if they are in fact correct, which I doubt.
Good spot.
As it's testing PCI_CACHE_LINE_SIZE,
they seem very much broken.
> On 5 May 2015, at 14:50, Joe Perches <[email protected]> wrote:
>
> On Tue, 2015-05-05 at 14:03 +0200, Peter Rosin wrote:
>>> diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
> []
>>> @@ -1098,14 +1098,18 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
>>> pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
>>>
>>> switch (cline) {
> []
>>> + case 0x8:
>>> + reg |= (0x1 << 14);
>>> + break;
>>> + case 0x16:
>>> + reg |= (0x2 << 14);
>>> + break;
>>> + case 0x32:
>>> + reg |= (0x3 << 14);
>>> + break;
>>> + default:
>>> + reg |= (0x0 << 14);
>>> + break;
>>> }
>>> }
>>
>> Those 0x16/0x32 hexadecimal case-selectors looking suspiciously like
>> decimal bits need a comment if they are in fact correct, which I doubt.
>
> Good spot.
>
> As it's testing PCI_CACHE_LINE_SIZE,
> they seem very much broken.
>
>
Interesting. I'll be happy to fix that bit if someone could guide me on it. Looks like these values should be 0x10, 0x20 instead of 0x16, 0x32 respectively. But I am unable to understand their meaning in this code.
Thanks