This patch adds the initialisation of some PHY registers
from the modal_header[] values in the EEPROM (see otus/hal/hpmain.c, line 333 ff.)
Signed-off-by: Joerg Albert <[email protected]>
---
drivers/net/wireless/ath/ar9170/phy.c | 129 ++++++++++++++++++++++++++++++++-
1 files changed, 128 insertions(+), 1 deletions(-)
diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/ar9170/phy.c
index cb8b5cd..47a5e5c 100644
--- a/drivers/net/wireless/ath/ar9170/phy.c
+++ b/drivers/net/wireless/ath/ar9170/phy.c
@@ -396,6 +396,131 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
{ 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
};
+/* look up a certain register in ar5416_phy_init[] and return the init. value
+ for the band and bandwidth given. Return 0 if register address not found. */
+u32 ar9170_get_default_phy_reg_val(int reg, bool is_2ghz, bool is_40mhz)
+{
+ struct ar9170_phy_init *p;
+ struct ar9170_phy_init *endp =
+ ar5416_phy_init+ARRAY_SIZE(ar5416_phy_init);
+
+ for (p = ar5416_phy_init; p < endp; p++)
+ if (p->reg == reg) {
+ if (is_2ghz)
+ return is_40mhz ? p->_2ghz_40 : p->_2ghz_20;
+ else
+ return is_40mhz ? p->_5ghz_40 : p->_5ghz_20;
+ }
+ return 0;
+}
+
+/* initialize some phy regs from eeprom values in modal_header[]
+ acc. to band and bandwith */
+static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
+ bool is_2ghz, bool is_40mhz)
+{
+ const u8 xpd2pd[16] = {
+ 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
+ 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
+ };
+ u32 defval, newval; /* two separate for debugging the changes */
+ /* pointer to the modal_header acc. to band */
+ struct ar9170_eeprom_modal *m = ar->eeprom.modal_header +
+ (is_2ghz ? 1 : 0);
+
+ ar9170_regwrite_begin(ar);
+
+ /* ant common control (index 0) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5964, is_2ghz, is_40mhz);
+ newval = le32_to_cpu(m->antCtrlCommon);
+ ar9170_regwrite(0x1c5964, newval);
+
+ /* ant control chain 0 (index 1) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5960, is_2ghz, is_40mhz);
+ newval = le32_to_cpu(m->antCtrlChain[0]);
+ ar9170_regwrite(0x1c5960, newval);
+
+ /* ant control chain 2 (index 2) */
+ defval = ar9170_get_default_phy_reg_val(0x1c7960, is_2ghz, is_40mhz);
+ newval = le32_to_cpu(m->antCtrlChain[1]);
+ ar9170_regwrite(0x1c7960, newval);
+
+ /* SwSettle (index 3) */
+ if (!is_40mhz) {
+ defval = ar9170_get_default_phy_reg_val(0x1c5844,
+ is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f80) | ((m->switchSettling & 0x7f)<<7);
+ ar9170_regwrite(0x1c5844, newval);
+ }
+
+ /* adcDesired, pdaDesired (index 4) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
+ newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
+ ((u8)m->adcDesiredSize);
+ ar9170_regwrite(0x1c5850, newval);
+
+ /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
+ newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
+ (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
+ ar9170_regwrite(0x1c5834, newval);
+
+ /* TxEndToRxOn (index 6) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
+ newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
+ ar9170_regwrite(0x1c5828, newval);
+
+ /* thresh62 (index 7) */
+ defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7f000) | (m->thresh62 << 12);
+ ar9170_regwrite(0x1c8864, newval);
+
+ /* tx/rx attenuation chain 0 (index 8) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
+ ar9170_regwrite(0x1c5848, newval);
+
+ /* tx/rx attenuation chain 2 (index 9) */
+ defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
+ ar9170_regwrite(0x1c7848, newval);
+
+ /* tx/rx margin chain 0 (index 10) */
+ defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
+ newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
+ /* bsw margin chain 0 for 5GHz only */
+ if (!is_2ghz)
+ newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
+ ar9170_regwrite(0x1c620c, newval);
+
+ /* tx/rx margin chain 2 (index 11) */
+ defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
+ newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
+ ar9170_regwrite(0x1c820c, newval);
+
+ /* iqCall, iqCallq chain 0 (index 12) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
+ ((u8)m->iqCalQCh[0] & 0x1f);
+ ar9170_regwrite(0x1c5920, newval);
+
+ /* iqCall, iqCallq chain 2 (index 13) */
+ defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
+ ((u8)m->iqCalQCh[1] & 0x1f);
+ ar9170_regwrite(0x1c7920, newval);
+
+ /* xpd gain mask (index 14) */
+ defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
+ newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
+ ar9170_regwrite(0x1c6258, newval);
+
+
+ ar9170_regwrite_finish();
+
+ return ar9170_regwrite_result();
+}
+
int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
{
int i, err;
@@ -426,7 +551,9 @@ int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
if (err)
return err;
- /* XXX: use EEPROM data here! */
+ err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
+ if (err)
+ return err;
err = ar9170_init_power_cal(ar);
if (err)
--
1.6.0.4
On 08/31/2009 11:53 AM, [email protected] wrote:
> ...
> See Documentation/CodingStyle - Chapter 8
>
> The preferred style for long (multi-line) comments is:
> /*
> * look up a certain register in ar5416_phy_init[] and return the init. value
> * for the band and bandwidth given. Return 0 if register address not found.
> */
> ...
Thanks for the comments. I agree with all of them and will re-spin a patch.
> It's amazing how much **** you can _cut_ from the vendor driver.
Yes, at first sight it looks really complex but it isn't.
> BTW: does this patch help the 1-stage fw stability, or is it still broken?
Turned out I had a corrupt firmware file. After downloading from Luis' URL it works fine
with my WNDA3100. Guess I had an earlier version from before 2009/05/28 or firefox corrupted it during download.
What's your setup to get 80+ MBit/s throughput with the two-stage firmware?
I've used an 802.11g AP so far, but have access to an 802.11n dual-band AP now.
Guess I should use 5GHz as 2.4 is rather crowded here.
How can I put ar9170 into 802.11n/40MHz mode?
Regards,
J?rg.
(changed cc', web.de finally pissed me off with a 500 mail quota)
2009/8/31 Joerg Albert <[email protected]>:
> On 08/31/2009 11:53 AM, [email protected] wrote:
>> ...
>> See Documentation/CodingStyle - Chapter 8
>>
>> The preferred style for long (multi-line) comments is:
>> /*
>> ?* look up a certain register in ar5416_phy_init[] and return the init. value
>> ?* for the band and bandwidth given. Return 0 if register address not found.
>> ?*/
>> ...
>
> Thanks for the comments. I agree with all of them and will re-spin a patch.
Great!
>> It's amazing how much **** you can _cut_ from the vendor driver.
>
> Yes, at first sight it looks really complex but it isn't.
well, there's still a thing... we can only copy what's there in driver,
But since the two-stage fw is capable of reinitializing
the rf/phy we could do all sorts of stuff without breaking it.
>> BTW: does this patch help the 1-stage fw stability, or is it still broken?
>
> Turned out I had a corrupt firmware file. After downloading from Luis' URL it works fine
> with my WNDA3100. Guess I had an earlier version from before 2009/05/28 or firefox
> corrupted it during download.
>
> What's your setup to get 80+ MBit/s throughput with the two-stage firmware?
simply another 11n card a few meters away (but in the same room of course,
since the 5GHz band doesn't like to go through concrete)
I tested a few configurations and only with a rt2860pci was able to get a
satisfying result over a small distance (7 m, but still in the same room ;) )
Other cards: like the ar5416 also worked, but not that well (tx rates halved)
and iwl4965, iwl5300 didn't work at all in n. (but they're flying with 11a)
> I've used an 802.11g AP so far, but have access to an 802.11n dual-band AP now.
> Guess I should use 5GHz as 2.4 is rather crowded here.
> How can I put ar9170 into 802.11n/40MHz mode?
well you need a patch which lets you use the MCS rates and
kicks off BlockAck sessions. I posted a version some time
ago, (AFAIK initial RFC?). However due to fact that the code belongs
into the rc-algorithm and the lack of "out-house testing" feedback,
I had to drop it. I can send you an _updated_ (well, it should apply without
fuzz... but you still have to select the MCS by hand) version if you want,
however not until Friday. Of course, If you have free time on your hand,
you could do the fix-ups by yourself and start the madNess right on! ;-)
(Note: Felix is looking into minstrel/HT. I expect once the code is
available, that we only have to patch ar9170 just a _little_ bit to get
it _sort of_ working.
(it might never probably work with the current available firmwares,
since the BA tx_status is totally bogus)
Regards,
Chr
> "Joerg Albert" <[email protected]> wrote:
>
> This patch adds the initialisation of some PHY registers
> from the modal_header[] values in the EEPROM (see otus/hal/hpmain.c, line 333 ff.)
>
> Signed-off-by: Joerg Albert <[email protected]>
meh, no hardware... and only a shitty kiosk with web-interface here.
testing has to wait until the weekend.
> diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/ar9170/phy.c
> index cb8b5cd..47a5e5c 100644
> --- a/drivers/net/wireless/ath/ar9170/phy.c
> +++ b/drivers/net/wireless/ath/ar9170/phy.c
> @@ -396,6 +396,131 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
> { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
> };
>
> +/* look up a certain register in ar5416_phy_init[] and return the init. value
> + for the band and bandwidth given. Return 0 if register address not found. */
See Documentation/CodingStyle - Chapter 8
The preferred style for long (multi-line) comments is:
/*
* look up a certain register in ar5416_phy_init[] and return the init. value
* for the band and bandwidth given. Return 0 if register address not found.
*/
> +u32 ar9170_get_default_phy_reg_val(int reg, bool is_2ghz, bool is_40mhz)
please consider this instead:
static u32 ar9170_get_default_phy_reg_val(u32 reg, [...])
(static function, and reg is a u32)
> +{
> + struct ar9170_phy_init *p;
> + struct ar9170_phy_init *endp =
> + ar5416_phy_init+ARRAY_SIZE(ar5416_phy_init);
(see Codingstyle: 3.1: Spaces
=> Use one space around (on each side of) most binary [...] operators)
> +
> + for (p = ar5416_phy_init; p < endp; p++)
a extra { } wouldn't hurt. The following statements also has multiple lines.
> + if (p->reg == reg) {
> + if (is_2ghz)
> + return is_40mhz ? p->_2ghz_40 : p->_2ghz_20;
> + else
> + return is_40mhz ? p->_5ghz_40 : p->_5ghz_20;
> + }
> + return 0;
> +}
hmm, it's a bit odd to use pointers over a fixed array,
what about (unfortunately space and line damaged... and untested):
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
if (ar5416_phy_init[i].reg != reg)
continue;
if (is_2ghz) {
if (is_40mhz)
return ar5416_phy_init[i]._2ghz_40;
else
return ar5416_phy_init[i]._2ghz_20;
} else {
if (is_40mhz)
return ar5416_phy_init[i]._5ghz_40;
else
return ar5416_phy_init[i]._5ghz_20;
}
}
return 0;
}
this follows the looks of the rest of the code. (e.g ar9170_init_phy)
(of course, either version should be fine.
so stay with yours if you have doubts.)
> +/* initialize some phy regs from eeprom values in modal_header[]
> + acc. to band and bandwith */
(multi-line comment, but I guess you know what do here now...)
> +static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
> + bool is_2ghz, bool is_40mhz)
> +{
> + const u8 xpd2pd[16] = {
> + 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
> + 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
> + };
static const u8 xpd2pd ?
> + u32 defval, newval; /* two separate for debugging the changes */
> + /* pointer to the modal_header acc. to band */
> + struct ar9170_eeprom_modal *m = ar->eeprom.modal_header +
> + (is_2ghz ? 1 : 0);
what about:
struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz]; ?
> + ar9170_regwrite_begin(ar);
> +
> + /* ant common control (index 0) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5964, is_2ghz, is_40mhz);
> + newval = le32_to_cpu(m->antCtrlCommon);
> + ar9170_regwrite(0x1c5964, newval);
> +
> + /* ant control chain 0 (index 1) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5960, is_2ghz, is_40mhz);
> + newval = le32_to_cpu(m->antCtrlChain[0]);
> + ar9170_regwrite(0x1c5960, newval);
> +
> + /* ant control chain 2 (index 2) */
> + defval = ar9170_get_default_phy_reg_val(0x1c7960, is_2ghz, is_40mhz);
> + newval = le32_to_cpu(m->antCtrlChain[1]);
> + ar9170_regwrite(0x1c7960, newval);
> +
> + /* SwSettle (index 3) */
> + if (!is_40mhz) {
> + defval = ar9170_get_default_phy_reg_val(0x1c5844,
> + is_2ghz, is_40mhz);
> + newval = (defval & ~0x3f80) | ((m->switchSettling & 0x7f)<<7);
(well )<<7 is a bit tight, but it looks like you ran out of space in this line?)
> + ar9170_regwrite(0x1c5844, newval);
> + }
> +
> + /* adcDesired, pdaDesired (index 4) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
> + newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
> + ((u8)m->adcDesiredSize);
> + ar9170_regwrite(0x1c5850, newval);
> +
> + /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
> + newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
> + (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
> + ar9170_regwrite(0x1c5834, newval);
> +
> + /* TxEndToRxOn (index 6) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
> + newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
> + ar9170_regwrite(0x1c5828, newval);
> +
> + /* thresh62 (index 7) */
> + defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
> + newval = (defval & ~0x7f000) | (m->thresh62 << 12);
> + ar9170_regwrite(0x1c8864, newval);
> +
> + /* tx/rx attenuation chain 0 (index 8) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
> + newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
> + ar9170_regwrite(0x1c5848, newval);
> +
> + /* tx/rx attenuation chain 2 (index 9) */
> + defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
> + newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
> + ar9170_regwrite(0x1c7848, newval);
> +
> + /* tx/rx margin chain 0 (index 10) */
> + defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
> + newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
> + /* bsw margin chain 0 for 5GHz only */
> + if (!is_2ghz)
> + newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
> + ar9170_regwrite(0x1c620c, newval);
> +
> + /* tx/rx margin chain 2 (index 11) */
> + defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
> + newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
> + ar9170_regwrite(0x1c820c, newval);
> +
> + /* iqCall, iqCallq chain 0 (index 12) */
> + defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
> + newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
> + ((u8)m->iqCalQCh[0] & 0x1f);
> + ar9170_regwrite(0x1c5920, newval);
> +
> + /* iqCall, iqCallq chain 2 (index 13) */
> + defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
> + newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
> + ((u8)m->iqCalQCh[1] & 0x1f);
> + ar9170_regwrite(0x1c7920, newval);
> +
> + /* xpd gain mask (index 14) */
> + defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
> + newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
> + ar9170_regwrite(0x1c6258, newval);
(cannot test this now. it looks good, though.)
It's amazing how much **** you can _cut_ from the vendor driver.
BTW: does this patch help the 1-stage fw stability, or is it still broken?
Regards,
Chr
________________________________________________________________
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f?r nur 19,99 Euro/mtl.!* http://produkte.web.de/go/02/
This patch adds the initialisation of some PHY registers
from the modal_header[] values in the EEPROM
(see otus/hal/hpmain.c, line 333 ff.)
Signed-off-by: Joerg Albert <[email protected]>
---
Compared to v1 I've included Christian's suggestions and removed
three unnecessary defval assignments for "ant * control".
This patch seems to depend on Christian's
"[RFT] ar9170: use eeprom's frequency calibration values"
(2009-08-21), I get a poor throughput here without it (1-stage fw,
802.11g AP).
drivers/net/wireless/ath/ar9170/phy.c | 136 ++++++++++++++++++++++++++++++++-
1 files changed, 135 insertions(+), 1 deletions(-)
diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/ar9170/phy.c
index df86f70..8fb1fa8 100644
--- a/drivers/net/wireless/ath/ar9170/phy.c
+++ b/drivers/net/wireless/ath/ar9170/phy.c
@@ -396,6 +396,138 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
{ 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
};
+/*
+ * look up a certain register in ar5416_phy_init[] and return the init. value
+ * for the band and bandwidth given. Return 0 if register address not found.
+ */
+static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
+{
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
+ if (ar5416_phy_init[i].reg != reg)
+ continue;
+
+ if (is_2ghz) {
+ if (is_40mhz)
+ return ar5416_phy_init[i]._2ghz_40;
+ else
+ return ar5416_phy_init[i]._2ghz_20;
+ } else {
+ if (is_40mhz)
+ return ar5416_phy_init[i]._5ghz_40;
+ else
+ return ar5416_phy_init[i]._5ghz_20;
+ }
+ }
+ return 0;
+}
+
+/*
+ * initialize some phy regs from eeprom values in modal_header[]
+ * acc. to band and bandwith
+ */
+static int ar9170_init_phy_from_eeprom(struct ar9170 *ar,
+ bool is_2ghz, bool is_40mhz)
+{
+ static const u8 xpd2pd[16] = {
+ 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
+ 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
+ };
+ u32 defval, newval;
+ /* pointer to the modal_header acc. to band */
+ struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
+
+ ar9170_regwrite_begin(ar);
+
+ /* ant common control (index 0) */
+ newval = le32_to_cpu(m->antCtrlCommon);
+ ar9170_regwrite(0x1c5964, newval);
+
+ /* ant control chain 0 (index 1) */
+ newval = le32_to_cpu(m->antCtrlChain[0]);
+ ar9170_regwrite(0x1c5960, newval);
+
+ /* ant control chain 2 (index 2) */
+ newval = le32_to_cpu(m->antCtrlChain[1]);
+ ar9170_regwrite(0x1c7960, newval);
+
+ /* SwSettle (index 3) */
+ if (!is_40mhz) {
+ defval = ar9170_get_default_phy_reg_val(0x1c5844,
+ is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f80) |
+ ((m->switchSettling & 0x7f) << 7);
+ ar9170_regwrite(0x1c5844, newval);
+ }
+
+ /* adcDesired, pdaDesired (index 4) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5850, is_2ghz, is_40mhz);
+ newval = (defval & ~0xffff) | ((u8)m->pgaDesiredSize << 8) |
+ ((u8)m->adcDesiredSize);
+ ar9170_regwrite(0x1c5850, newval);
+
+ /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5834, is_2ghz, is_40mhz);
+ newval = (m->txEndToXpaOff << 24) | (m->txEndToXpaOff << 16) |
+ (m->txFrameToXpaOn << 8) | m->txFrameToXpaOn;
+ ar9170_regwrite(0x1c5834, newval);
+
+ /* TxEndToRxOn (index 6) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5828, is_2ghz, is_40mhz);
+ newval = (defval & ~0xff0000) | (m->txEndToRxOn << 16);
+ ar9170_regwrite(0x1c5828, newval);
+
+ /* thresh62 (index 7) */
+ defval = ar9170_get_default_phy_reg_val(0x1c8864, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7f000) | (m->thresh62 << 12);
+ ar9170_regwrite(0x1c8864, newval);
+
+ /* tx/rx attenuation chain 0 (index 8) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5848, is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f000) | ((m->txRxAttenCh[0] & 0x3f) << 12);
+ ar9170_regwrite(0x1c5848, newval);
+
+ /* tx/rx attenuation chain 2 (index 9) */
+ defval = ar9170_get_default_phy_reg_val(0x1c7848, is_2ghz, is_40mhz);
+ newval = (defval & ~0x3f000) | ((m->txRxAttenCh[1] & 0x3f) << 12);
+ ar9170_regwrite(0x1c7848, newval);
+
+ /* tx/rx margin chain 0 (index 10) */
+ defval = ar9170_get_default_phy_reg_val(0x1c620c, is_2ghz, is_40mhz);
+ newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[0] & 0x3f) << 18);
+ /* bsw margin chain 0 for 5GHz only */
+ if (!is_2ghz)
+ newval = (newval & ~0x3c00) | ((m->bswMargin[0] & 0xf) << 10);
+ ar9170_regwrite(0x1c620c, newval);
+
+ /* tx/rx margin chain 2 (index 11) */
+ defval = ar9170_get_default_phy_reg_val(0x1c820c, is_2ghz, is_40mhz);
+ newval = (defval & ~0xfc0000) | ((m->rxTxMarginCh[1] & 0x3f) << 18);
+ ar9170_regwrite(0x1c820c, newval);
+
+ /* iqCall, iqCallq chain 0 (index 12) */
+ defval = ar9170_get_default_phy_reg_val(0x1c5920, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[0] & 0x3f) << 5) |
+ ((u8)m->iqCalQCh[0] & 0x1f);
+ ar9170_regwrite(0x1c5920, newval);
+
+ /* iqCall, iqCallq chain 2 (index 13) */
+ defval = ar9170_get_default_phy_reg_val(0x1c7920, is_2ghz, is_40mhz);
+ newval = (defval & ~0x7ff) | (((u8)m->iqCalICh[1] & 0x3f) << 5) |
+ ((u8)m->iqCalQCh[1] & 0x1f);
+ ar9170_regwrite(0x1c7920, newval);
+
+ /* xpd gain mask (index 14) */
+ defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
+ newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
+ ar9170_regwrite(0x1c6258, newval);
+
+
+ ar9170_regwrite_finish();
+
+ return ar9170_regwrite_result();
+}
+
int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
{
int i, err;
@@ -426,7 +558,9 @@ int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
if (err)
return err;
- /* XXX: use EEPROM data here! */
+ err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
+ if (err)
+ return err;
err = ar9170_init_power_cal(ar);
if (err)
--
1.6.0.4
On Thursday 03 September 2009 01:02:59 Joerg Albert wrote:
>
> This patch adds the initialisation of some PHY registers
> from the modal_header[] values in the EEPROM
> (see otus/hal/hpmain.c, line 333 ff.)
>
> Signed-off-by: Joerg Albert <[email protected]>
Acked-by: Christian Lamparter <[email protected]>
> ---
>
> Compared to v1 I've included Christian's suggestions and removed
> three unnecessary defval assignments for "ant * control".
>
> This patch seems to depend on Christian's
> "[RFT] ar9170: use eeprom's frequency calibration values"
> (2009-08-21), I get a poor throughput here without it (1-stage fw,
> 802.11g AP).
Good work!
with both patches applied, my WNDA is finally able to pick up some
speed. But, it's still a mbit slower than the two-stage fw.
> drivers/net/wireless/ath/ar9170/phy.c | 136 ++++++++++++++++++++++++++++++++-
> 1 files changed, 135 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/ar9170/phy.c
> index df86f70..8fb1fa8 100644
> --- a/drivers/net/wireless/ath/ar9170/phy.c
> +++ b/drivers/net/wireless/ath/ar9170/phy.c
> @@ -396,6 +396,138 @@ static struct ar9170_phy_init ar5416_phy_init[] = {
> { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
> };
>
> +/*
> + * look up a certain register in ar5416_phy_init[] and return the init. value
> + * for the band and bandwidth given. Return 0 if register address not found.
> + */
> +static u32 ar9170_get_default_phy_reg_val(u32 reg, bool is_2ghz, bool is_40mhz)
[...]
> + /* xpd gain mask (index 14) */
> + defval = ar9170_get_default_phy_reg_val(0x1c6258, is_2ghz, is_40mhz);
> + newval = (defval & ~0xf0000) | (xpd2pd[m->xpdGain & 0xf] << 16);
> + ar9170_regwrite(0x1c6258, newval);
> +
> +
John, can you please nuke those two empty lines?
> + ar9170_regwrite_finish();
> +
> + return ar9170_regwrite_result();
> +}
> +
> int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
> {
> int i, err;
> @@ -426,7 +558,9 @@ int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
> if (err)
> return err;
>
> - /* XXX: use EEPROM data here! */
uh, I think we're still missing the heavy clip/conformance?
(otus/hal/hpmain.c, line 3723 ff.).
It should be modified to say something like:
/* TODO: (heavy clip) regulatory domain power level fine-tuning. */
> + err = ar9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
> + if (err)
> + return err;
>
> err = ar9170_init_power_cal(ar);
> if (err)
Regards,
Chr
(CC linux-wireless)
On Thursday 03 September 2009 00:44:02 Joerg Albert wrote:
> On 08/31/2009 11:37 PM, Christian Lamparter wrote:
>
> > well you need a patch which lets you use the MCS rates and
> > kicks off BlockAck sessions. I posted a version some time
> > ago, (AFAIK initial RFC?). However due to fact that the code belongs
> > into the rc-algorithm and the lack of "out-house testing" feedback,
> > I had to drop it. I can send you an _updated_ (well, it should apply without
> > fuzz... but you still have to select the MCS by hand) version if you want,
> > however not until Friday. Of course, If you have free time on your hand,
> > you could do the fix-ups by yourself and start the madNess right on! ;-)
>
> As I'm not that familiar with 802.11n (and always short of free time)
> I'd like to use your patch.
> Guess the old version is
> "[WIP][RFT][RFC] ar9170: aggregation xmit (aka the _other_ part)" from 2009/06/06?
exactly... it's old & buggy
this version even has a bogus rc.
(Of course, you can select your own MCS rate by changing)
+ rate->idx = sta_info->current_rate;
to a static value between 0 and 15.
(which is _translated_ into: MCS 0 - 15)
Regards,
Chr