Purpose of the patch series is to extract a portion of PCIe driver sources
that is common among Quantenna wifi devices. It will later be used to add
support for additional wifi card.
As a result, majority of changes here are moving code blocks around and
renaming without functional changes + several minor improvements.
Igor Mitsyanko (11):
qtnfmac_pcie: do not store FW name in driver state structure
qtnfmac_pcie: move Pearl pcie sources to pcie-specific directory
qtnfmac_pcie: rename private Pearl PCIe state structure
qtnfmac_pcie: indicate pearl-specific structures by their names
qtnfmac_pcie: pearl: rename spinlock tx0_lock to tx_lock
qtnfmac_pcie: separate platform-independent PCIe structure
qtnfmac_pcie: rename platform-specific functions
qtnfmac: add missing header includes to bus.h
qtnfmac_pcie: extract platform-independent PCIe code
qtnfmac: wait for FW load work to finish at PCIe remove
qtnfmac_pcie: check for correct CHIP ID at pcie probe
drivers/net/wireless/quantenna/qtnfmac/Makefile | 3 +-
drivers/net/wireless/quantenna/qtnfmac/bus.h | 5 +-
drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c | 404 ++++++
.../{pearl/pcie_bus_priv.h =3D> pcie/pcie_priv.h} | 71 +-
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 1261 ++++++++++++++++=
+
.../{pearl/pcie_ipc.h =3D> pcie/pearl_pcie_ipc.h} | 58 -
.../pcie_regs_pearl.h =3D> pcie/pearl_pcie_regs.h} | 0
.../net/wireless/quantenna/qtnfmac/pearl/pcie.c | 1494 ----------------=
----
.../net/wireless/quantenna/qtnfmac/qtn_hw_ids.h | 14 +
9 files changed, 1723 insertions(+), 1587 deletions(-)
create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_bus_priv.h =3D> =
pcie/pcie_priv.h} (51%)
create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.=
c
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_ipc.h =3D> pcie/=
pearl_pcie_ipc.h} (68%)
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_regs_pearl.h =3D=
> pcie/pearl_pcie_regs.h} (100%)
delete mode 100644 drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
--=20
2.9.5
Rename several functions to indicate that they are platform specific.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 100 +++++++++++------=
----
1 file changed, 51 insertions(+), 49 deletions(-)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 97f3001..f3655de 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -226,7 +226,7 @@ static void qtnf_deassert_intx(struct qtnf_pcie_pearl_s=
tate *ps)
qtnf_non_posted_write(cfg, reg);
}
=20
-static void qtnf_reset_card(struct qtnf_pcie_pearl_state *ps)
+static void qtnf_pearl_reset_ep(struct qtnf_pcie_pearl_state *ps)
{
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
void __iomem *reg =3D ps->base.sysctl_bar +
@@ -237,7 +237,7 @@ static void qtnf_reset_card(struct qtnf_pcie_pearl_stat=
e *ps)
pci_restore_state(ps->base.pdev);
}
=20
-static void qtnf_ipc_gen_ep_int(void *arg)
+static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg)
{
const struct qtnf_pcie_pearl_state *ps =3D arg;
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
@@ -297,7 +297,8 @@ static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pear=
l_state *ps)
{
struct qtnf_shm_ipc_region __iomem *ipc_tx_reg;
struct qtnf_shm_ipc_region __iomem *ipc_rx_reg;
- const struct qtnf_shm_ipc_int ipc_int =3D { qtnf_ipc_gen_ep_int, ps };
+ const struct qtnf_shm_ipc_int ipc_int =3D
+ { qtnf_pcie_pearl_ipc_gen_ep_int, ps };
const struct qtnf_shm_ipc_rx_callback rx_callback =3D {
qtnf_pcie_control_rx_callback, ps };
=20
@@ -442,7 +443,7 @@ static int alloc_skb_array(struct qtnf_pcie_bus_priv *p=
riv)
return 0;
}
=20
-static int alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
+static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
dma_addr_t paddr;
@@ -494,7 +495,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state =
*ps)
return 0;
}
=20
-static int skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index)
+static int pearl_skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 inde=
x)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_rx_bd *rxbd;
@@ -538,7 +539,7 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_state =
*ps, u16 index)
return 0;
}
=20
-static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps)
+static int pearl_alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps)
{
u16 i;
int ret =3D 0;
@@ -547,7 +548,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_stat=
e *ps)
ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
=20
for (i =3D 0; i < ps->base.rx_bd_num; i++) {
- ret =3D skb2rbd_attach(ps, i);
+ ret =3D pearl_skb2rbd_attach(ps, i);
if (ret)
break;
}
@@ -556,7 +557,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_stat=
e *ps)
}
=20
/* all rx/tx activity should have ceased before calling this function */
-static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps)
+static void qtnf_pearl_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_tx_bd *txbd;
@@ -594,7 +595,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pea=
rl_state *ps)
}
}
=20
-static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *ps)
+static int pearl_hhbm_init(struct qtnf_pcie_pearl_state *ps)
{
u32 val;
=20
@@ -612,7 +613,7 @@ static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state =
*ps)
return 0;
}
=20
-static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps)
+static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
int ret;
@@ -649,7 +650,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *ps)
return -EINVAL;
}
=20
- ret =3D qtnf_hhbm_init(ps);
+ ret =3D pearl_hhbm_init(ps);
if (ret) {
pr_err("failed to init h/w queues\n");
return ret;
@@ -661,13 +662,13 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl=
_state *ps)
return ret;
}
=20
- ret =3D alloc_bd_table(ps);
+ ret =3D pearl_alloc_bd_table(ps);
if (ret) {
pr_err("failed to allocate bd table\n");
return ret;
}
=20
- ret =3D alloc_rx_buffers(ps);
+ ret =3D pearl_alloc_rx_buffers(ps);
if (ret) {
pr_err("failed to allocate rx buffers\n");
return ret;
@@ -676,7 +677,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *ps)
return ret;
}
=20
-static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps)
+static void qtnf_pearl_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_tx_bd *txbd;
@@ -734,7 +735,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_s=
tate *ps)
=20
if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
priv->tx_bd_num)) {
- qtnf_pcie_data_tx_reclaim(ps);
+ qtnf_pearl_data_tx_reclaim(ps);
=20
if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
priv->tx_bd_num)) {
@@ -818,7 +819,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
priv->tx_done_count++;
spin_unlock_irqrestore(&priv->tx_lock, flags);
=20
- qtnf_pcie_data_tx_reclaim(ps);
+ qtnf_pearl_data_tx_reclaim(ps);
=20
return NETDEV_TX_OK;
}
@@ -838,7 +839,7 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus, s=
truct sk_buff *skb)
return ret;
}
=20
-static irqreturn_t qtnf_interrupt(int irq, void *data)
+static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data)
{
struct qtnf_bus *bus =3D (struct qtnf_bus *)data;
struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
@@ -898,7 +899,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_st=
ate *ps)
return 0;
}
=20
-static int qtnf_rx_poll(struct napi_struct *napi, int budget)
+static int qtnf_pcie_pearl_rx_poll(struct napi_struct *napi, int budget)
{
struct qtnf_bus *bus =3D container_of(napi, struct qtnf_bus, mux_napi);
struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
@@ -982,7 +983,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int b=
udget)
if (++w_idx >=3D priv->rx_bd_num)
w_idx =3D 0;
=20
- ret =3D skb2rbd_attach(ps, w_idx);
+ ret =3D pearl_skb2rbd_attach(ps, w_idx);
if (ret) {
pr_err("failed to allocate new rx_skb[%d]\n",
w_idx);
@@ -1026,7 +1027,7 @@ static void qtnf_pcie_data_rx_stop(struct qtnf_bus *b=
us)
qtnf_disable_hdp_irqs(ps);
}
=20
-static const struct qtnf_bus_ops qtnf_pcie_bus_ops =3D {
+static const struct qtnf_bus_ops qtnf_pcie_pearl_bus_ops =3D {
/* control path methods */
.control_tx =3D qtnf_pcie_control_tx,
=20
@@ -1234,7 +1235,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, con=
st u8 *fw, u32 fw_size)
continue;
}
=20
- qtnf_pcie_data_tx_reclaim(ps);
+ qtnf_pearl_data_tx_reclaim(ps);
}
=20
pblk +=3D len;
@@ -1245,7 +1246,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, con=
st u8 *fw, u32 fw_size)
return 0;
}
=20
-static void qtnf_fw_work_handler(struct work_struct *work)
+static void qtnf_pearl_fw_work_handler(struct work_struct *work)
{
struct qtnf_bus *bus =3D container_of(work, struct qtnf_bus, fw_work);
struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
@@ -1336,19 +1337,19 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *=
bus)
struct pci_dev *pdev =3D priv->pdev;
=20
get_device(&pdev->dev);
- INIT_WORK(&bus->fw_work, qtnf_fw_work_handler);
+ INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler);
schedule_work(&bus->fw_work);
}
=20
-static void qtnf_reclaim_tasklet_fn(unsigned long data)
+static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data)
{
struct qtnf_pcie_pearl_state *ps =3D (void *)data;
=20
- qtnf_pcie_data_tx_reclaim(ps);
+ qtnf_pearl_data_tx_reclaim(ps);
qtnf_en_txdone_irq(ps);
}
=20
-static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_i=
d *id)
+static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, const struct pci_de=
vice_id *id)
{
struct qtnf_pcie_pearl_state *ps;
struct qtnf_bus *bus;
@@ -1362,7 +1363,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
ps =3D get_bus_priv(bus);
=20
pci_set_drvdata(pdev, bus);
- bus->bus_ops =3D &qtnf_pcie_bus_ops;
+ bus->bus_ops =3D &qtnf_pcie_pearl_bus_ops;
bus->dev =3D &pdev->dev;
bus->fw_state =3D QTNF_FW_STATE_RESET;
ps->base.pdev =3D pdev;
@@ -1383,12 +1384,12 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, co=
nst struct pci_device_id *id)
ps->base.tx_reclaim_done =3D 0;
ps->base.tx_reclaim_req =3D 0;
=20
- tasklet_init(&ps->base.reclaim_tq, qtnf_reclaim_tasklet_fn,
+ tasklet_init(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn,
(unsigned long)ps);
=20
init_dummy_netdev(&bus->mux_dev);
netif_napi_add(&bus->mux_dev, &bus->mux_napi,
- qtnf_rx_poll, 10);
+ qtnf_pcie_pearl_rx_poll, 10);
=20
ps->base.workqueue =3D create_singlethread_workqueue("QTNF_PEARL_PCIE");
if (!ps->base.workqueue) {
@@ -1440,7 +1441,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
goto err_base;
}
=20
- ret =3D qtnf_pcie_init_xfer(ps);
+ ret =3D qtnf_pcie_pearl_init_xfer(ps);
if (ret) {
pr_err("PCIE xfer init failed\n");
goto err_ipc;
@@ -1452,7 +1453,8 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
/* start with disabled irqs */
qtnf_disable_hdp_irqs(ps);
=20
- ret =3D devm_request_irq(&pdev->dev, pdev->irq, &qtnf_interrupt, 0,
+ ret =3D devm_request_irq(&pdev->dev, pdev->irq,
+ &qtnf_pcie_pearl_interrupt, 0,
"qtnf_pcie_irq", (void *)bus);
if (ret) {
pr_err("failed to request pcie irq %d\n", pdev->irq);
@@ -1464,7 +1466,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
return 0;
=20
err_xfer:
- qtnf_free_xfer_buffers(ps);
+ qtnf_pearl_free_xfer_buffers(ps);
=20
err_ipc:
qtnf_pcie_free_shm_ipc(&ps->base);
@@ -1481,7 +1483,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
return ret;
}
=20
-static void qtnf_pcie_remove(struct pci_dev *pdev)
+static void qtnf_pcie_pearl_remove(struct pci_dev *pdev)
{
struct qtnf_pcie_pearl_state *ps;
struct qtnf_bus *bus;
@@ -1497,24 +1499,24 @@ static void qtnf_pcie_remove(struct pci_dev *pdev)
qtnf_core_detach(bus);
=20
ps =3D get_bus_priv(bus);
- qtnf_reset_card(ps);
+ qtnf_pearl_reset_ep(ps);
netif_napi_del(&bus->mux_napi);
flush_workqueue(ps->base.workqueue);
destroy_workqueue(ps->base.workqueue);
tasklet_kill(&ps->base.reclaim_tq);
=20
- qtnf_free_xfer_buffers(ps);
+ qtnf_pearl_free_xfer_buffers(ps);
qtnf_pcie_free_shm_ipc(&ps->base);
qtnf_debugfs_remove(bus);
}
=20
#ifdef CONFIG_PM_SLEEP
-static int qtnf_pcie_suspend(struct device *dev)
+static int qtnf_pcie_pearl_suspend(struct device *dev)
{
return -EOPNOTSUPP;
}
=20
-static int qtnf_pcie_resume(struct device *dev)
+static int qtnf_pcie_pearl_resume(struct device *dev)
{
return 0;
}
@@ -1522,8 +1524,8 @@ static int qtnf_pcie_resume(struct device *dev)
=20
#ifdef CONFIG_PM_SLEEP
/* Power Management Hooks */
-static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend,
- qtnf_pcie_resume);
+static SIMPLE_DEV_PM_OPS(qtnf_pcie_pearl_pm_ops, qtnf_pcie_pearl_suspend,
+ qtnf_pcie_pearl_resume);
#endif
=20
static const struct pci_device_id qtnf_pcie_devid_table[] =3D {
@@ -1536,32 +1538,32 @@ static const struct pci_device_id qtnf_pcie_devid_t=
able[] =3D {
=20
MODULE_DEVICE_TABLE(pci, qtnf_pcie_devid_table);
=20
-static struct pci_driver qtnf_pcie_drv_data =3D {
+static struct pci_driver qtnf_pcie_pearl_drv_data =3D {
.name =3D DRV_NAME,
.id_table =3D qtnf_pcie_devid_table,
- .probe =3D qtnf_pcie_probe,
- .remove =3D qtnf_pcie_remove,
+ .probe =3D qtnf_pcie_pearl_probe,
+ .remove =3D qtnf_pcie_pearl_remove,
#ifdef CONFIG_PM_SLEEP
.driver =3D {
- .pm =3D &qtnf_pcie_pm_ops,
+ .pm =3D &qtnf_pcie_pearl_pm_ops,
},
#endif
};
=20
-static int __init qtnf_pcie_register(void)
+static int __init qtnf_pcie_pearl_register(void)
{
pr_info("register Quantenna QSR10g FullMAC PCIE driver\n");
- return pci_register_driver(&qtnf_pcie_drv_data);
+ return pci_register_driver(&qtnf_pcie_pearl_drv_data);
}
=20
-static void __exit qtnf_pcie_exit(void)
+static void __exit qtnf_pcie_pearl_exit(void)
{
pr_info("unregister Quantenna QSR10g FullMAC PCIE driver\n");
- pci_unregister_driver(&qtnf_pcie_drv_data);
+ pci_unregister_driver(&qtnf_pcie_pearl_drv_data);
}
=20
-module_init(qtnf_pcie_register);
-module_exit(qtnf_pcie_exit);
+module_init(qtnf_pcie_pearl_register);
+module_exit(qtnf_pcie_pearl_exit);
=20
MODULE_AUTHOR("Quantenna Communications");
MODULE_DESCRIPTION("Quantenna QSR10g PCIe bus driver for 802.11 wireless L=
AN.");
--=20
2.9.5
Firmware name is only needed at probe stage, no point in keeping it in
driver state structure.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/bus.h | 1 -
drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wir=
eless/quantenna/qtnfmac/bus.h
index 323e47c..2beca5b 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/bus.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h
@@ -57,7 +57,6 @@ struct qtnf_bus {
struct qtnf_wmac *mac[QTNF_MAX_MAC];
struct qtnf_qlink_transport trans;
struct qtnf_hw_info hw_info;
- char fwname[32];
struct napi_struct mux_napi;
struct net_device mux_dev;
struct completion firmware_init_complete;
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c b/drivers/=
net/wireless/quantenna/qtnfmac/pearl/pcie.c
index 3120d49..97cc7f2 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
@@ -1177,13 +1177,14 @@ static void qtnf_fw_work_handler(struct work_struct=
*work)
const struct firmware *fw;
int ret;
u32 state =3D QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK;
+ const char *fwname =3D QTN_PCI_PEARL_FW_NAME;
=20
if (flashboot) {
state |=3D QTN_RC_FW_FLASHBOOT;
} else {
- ret =3D request_firmware(&fw, bus->fwname, &pdev->dev);
+ ret =3D request_firmware(&fw, fwname, &pdev->dev);
if (ret < 0) {
- pr_err("failed to get firmware %s\n", bus->fwname);
+ pr_err("failed to get firmware %s\n", fwname);
goto fw_load_fail;
}
}
@@ -1205,7 +1206,7 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
if (flashboot) {
pr_info("booting firmware from flash\n");
} else {
- pr_info("starting firmware upload: %s\n", bus->fwname);
+ pr_info("starting firmware upload: %s\n", fwname);
=20
ret =3D qtnf_ep_fw_load(priv, fw->data, fw->size);
release_firmware(fw);
@@ -1290,7 +1291,6 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
bus->fw_state =3D QTNF_FW_STATE_RESET;
pcie_priv->pdev =3D pdev;
=20
- strcpy(bus->fwname, QTN_PCI_PEARL_FW_NAME);
init_completion(&bus->firmware_init_complete);
mutex_init(&bus->bus_lock);
spin_lock_init(&pcie_priv->tx0_lock);
--=20
2.9.5
Move platform-independent PCIe data structure to a separate header file
so it can be reused by different devices.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
.../wireless/quantenna/qtnfmac/pcie/pcie_priv.h | 83 ++++
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 471 ++++++++++-------=
----
.../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 7 -
3 files changed, 300 insertions(+), 261 deletions(-)
create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h b/driv=
ers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
new file mode 100644
index 0000000..1ad5eb8
--- /dev/null
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Quantenna Communications, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _QTN_FMAC_PCIE_H_
+#define _QTN_FMAC_PCIE_H_
+
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/skbuff.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+
+#include "shm_ipc.h"
+
+#define SKB_BUF_SIZE 2048
+
+#define QTN_FW_DL_TIMEOUT_MS 3000
+#define QTN_FW_QLINK_TIMEOUT_MS 30000
+#define QTN_EP_RESET_WAIT_MS 1000
+
+struct qtnf_pcie_bus_priv {
+ struct pci_dev *pdev;
+
+ spinlock_t tx_reclaim_lock;
+ spinlock_t tx_lock;
+ int mps;
+
+ struct workqueue_struct *workqueue;
+ struct tasklet_struct reclaim_tq;
+
+ void __iomem *sysctl_bar;
+ void __iomem *epmem_bar;
+ void __iomem *dmareg_bar;
+
+ struct qtnf_shm_ipc shm_ipc_ep_in;
+ struct qtnf_shm_ipc shm_ipc_ep_out;
+
+ u16 tx_bd_num;
+ u16 rx_bd_num;
+
+ struct sk_buff **tx_skb;
+ struct sk_buff **rx_skb;
+
+ u32 rx_bd_w_index;
+ u32 rx_bd_r_index;
+
+ u32 tx_bd_w_index;
+ u32 tx_bd_r_index;
+
+ /* diagnostics stats */
+ u32 pcie_irq_count;
+ u32 tx_full_count;
+ u32 tx_done_count;
+ u32 tx_reclaim_done;
+ u32 tx_reclaim_req;
+
+ u8 msi_enabled;
+ u8 tx_stopped;
+};
+
+static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
+{
+ writel(val, basereg);
+
+ /* flush posted write */
+ readl(basereg);
+}
+
+#endif /* _QTN_FMAC_PCIE_H_ */
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 791a1e3..97f3001 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -28,6 +28,7 @@
#include <linux/circ_buf.h>
#include <linux/log2.h>
=20
+#include "pcie_priv.h"
#include "pearl_pcie_regs.h"
#include "pearl_pcie_ipc.h"
#include "qtn_hw_ids.h"
@@ -102,38 +103,14 @@ struct qtnf_pearl_fw_hdr {
} __packed;
=20
struct qtnf_pcie_pearl_state {
- struct pci_dev *pdev;
+ struct qtnf_pcie_bus_priv base;
=20
/* lock for irq configuration changes */
spinlock_t irq_lock;
=20
- /* lock for tx reclaim operations */
- spinlock_t tx_reclaim_lock;
- /* lock for tx0 operations */
- spinlock_t tx_lock;
- u8 msi_enabled;
- u8 tx_stopped;
- int mps;
-
- struct workqueue_struct *workqueue;
- struct tasklet_struct reclaim_tq;
-
- void __iomem *sysctl_bar;
- void __iomem *epmem_bar;
- void __iomem *dmareg_bar;
-
- struct qtnf_shm_ipc shm_ipc_ep_in;
- struct qtnf_shm_ipc shm_ipc_ep_out;
-
struct qtnf_pearl_bda __iomem *bda;
void __iomem *pcie_reg_base;
=20
- u16 tx_bd_num;
- u16 rx_bd_num;
-
- struct sk_buff **tx_skb;
- struct sk_buff **rx_skb;
-
struct qtnf_pearl_tx_bd *tx_bd_vbase;
dma_addr_t tx_bd_pbase;
=20
@@ -143,102 +120,80 @@ struct qtnf_pcie_pearl_state {
dma_addr_t bd_table_paddr;
void *bd_table_vaddr;
u32 bd_table_len;
-
- u32 rx_bd_w_index;
- u32 rx_bd_r_index;
-
- u32 tx_bd_w_index;
- u32 tx_bd_r_index;
-
u32 pcie_irq_mask;
-
- /* diagnostics stats */
- u32 pcie_irq_count;
u32 pcie_irq_rx_count;
u32 pcie_irq_tx_count;
u32 pcie_irq_uf_count;
- u32 tx_full_count;
- u32 tx_done_count;
- u32 tx_reclaim_done;
- u32 tx_reclaim_req;
};
=20
-static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
-{
- writel(val, basereg);
-
- /* flush posted write */
- readl(basereg);
-}
-
-static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *priv)
+static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- priv->pcie_irq_mask =3D (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS);
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ ps->pcie_irq_mask =3D (PCIE_HDP_INT_RX_BITS | PCIE_HDP_INT_TX_BITS);
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *priv=
)
+static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *pri=
v)
+static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- writel(0x0, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *priv)
+static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- priv->pcie_irq_mask |=3D PCIE_HDP_INT_RX_BITS;
- writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ ps->pcie_irq_mask |=3D PCIE_HDP_INT_RX_BITS;
+ writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *priv)
+static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- priv->pcie_irq_mask &=3D ~PCIE_HDP_INT_RX_BITS;
- writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ ps->pcie_irq_mask &=3D ~PCIE_HDP_INT_RX_BITS;
+ writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *priv)
+static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- priv->pcie_irq_mask |=3D PCIE_HDP_INT_TX_BITS;
- writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ ps->pcie_irq_mask |=3D PCIE_HDP_INT_TX_BITS;
+ writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *priv)
+static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *ps)
{
unsigned long flags;
=20
- spin_lock_irqsave(&priv->irq_lock, flags);
- priv->pcie_irq_mask &=3D ~PCIE_HDP_INT_TX_BITS;
- writel(priv->pcie_irq_mask, PCIE_HDP_INT_EN(priv->pcie_reg_base));
- spin_unlock_irqrestore(&priv->irq_lock, flags);
+ spin_lock_irqsave(&ps->irq_lock, flags);
+ ps->pcie_irq_mask &=3D ~PCIE_HDP_INT_TX_BITS;
+ writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
+ spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv)
{
struct pci_dev *pdev =3D priv->pdev;
=20
@@ -261,9 +216,9 @@ static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_s=
tate *priv)
}
}
=20
-static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps)
{
- void __iomem *reg =3D priv->sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
+ void __iomem *reg =3D ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
u32 cfg;
=20
cfg =3D readl(reg);
@@ -271,28 +226,28 @@ static void qtnf_deassert_intx(struct qtnf_pcie_pearl=
_state *priv)
qtnf_non_posted_write(cfg, reg);
}
=20
-static void qtnf_reset_card(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_reset_card(struct qtnf_pcie_pearl_state *ps)
{
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
- void __iomem *reg =3D priv->sysctl_bar +
+ void __iomem *reg =3D ps->base.sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
=20
qtnf_non_posted_write(data, reg);
msleep(QTN_EP_RESET_WAIT_MS);
- pci_restore_state(priv->pdev);
+ pci_restore_state(ps->base.pdev);
}
=20
static void qtnf_ipc_gen_ep_int(void *arg)
{
- const struct qtnf_pcie_pearl_state *priv =3D arg;
+ const struct qtnf_pcie_pearl_state *ps =3D arg;
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
- void __iomem *reg =3D priv->sysctl_bar +
+ void __iomem *reg =3D ps->base.sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
=20
qtnf_non_posted_write(data, reg);
}
=20
-static void __iomem *qtnf_map_bar(struct qtnf_pcie_pearl_state *priv, u8 i=
ndex)
+static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 inde=
x)
{
void __iomem *vaddr;
dma_addr_t busaddr;
@@ -317,7 +272,7 @@ static void __iomem *qtnf_map_bar(struct qtnf_pcie_pear=
l_state *priv, u8 index)
=20
static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t=
len)
{
- struct qtnf_pcie_pearl_state *priv =3D arg;
+ struct qtnf_pcie_bus_priv *priv =3D arg;
struct qtnf_bus *bus =3D pci_get_drvdata(priv->pdev);
struct sk_buff *skb;
=20
@@ -338,35 +293,36 @@ static void qtnf_pcie_control_rx_callback(void *arg, =
const u8 *buf, size_t len)
qtnf_trans_handle_rx_ctl_packet(bus, skb);
}
=20
-static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_shm_ipc_region __iomem *ipc_tx_reg;
struct qtnf_shm_ipc_region __iomem *ipc_rx_reg;
- const struct qtnf_shm_ipc_int ipc_int =3D { qtnf_ipc_gen_ep_int, priv };
+ const struct qtnf_shm_ipc_int ipc_int =3D { qtnf_ipc_gen_ep_int, ps };
const struct qtnf_shm_ipc_rx_callback rx_callback =3D {
- qtnf_pcie_control_rx_callback, priv };
+ qtnf_pcie_control_rx_callback, ps };
=20
- ipc_tx_reg =3D &priv->bda->bda_shm_reg1;
- ipc_rx_reg =3D &priv->bda->bda_shm_reg2;
+ ipc_tx_reg =3D &ps->bda->bda_shm_reg1;
+ ipc_rx_reg =3D &ps->bda->bda_shm_reg2;
=20
- qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
- ipc_tx_reg, priv->workqueue,
+ qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
+ ipc_tx_reg, ps->base.workqueue,
&ipc_int, &rx_callback);
- qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
- ipc_rx_reg, priv->workqueue,
+ qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
+ ipc_rx_reg, ps->base.workqueue,
&ipc_int, &rx_callback);
=20
return 0;
}
=20
-static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
{
qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
}
=20
-static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
int ret =3D -ENOMEM;
=20
priv->sysctl_bar =3D qtnf_map_bar(priv, QTN_SYSCTL_BAR);
@@ -387,14 +343,14 @@ static int qtnf_pcie_init_memory(struct qtnf_pcie_pea=
rl_state *priv)
return ret;
}
=20
- priv->pcie_reg_base =3D priv->dmareg_bar;
- priv->bda =3D priv->epmem_bar;
- writel(priv->msi_enabled, &priv->bda->bda_rc_msi_enabled);
+ ps->pcie_reg_base =3D priv->dmareg_bar;
+ ps->bda =3D priv->epmem_bar;
+ writel(priv->msi_enabled, &ps->bda->bda_rc_msi_enabled);
=20
return 0;
}
=20
-static void qtnf_tune_pcie_mps(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv)
{
struct pci_dev *pdev =3D priv->pdev;
struct pci_dev *parent;
@@ -466,7 +422,7 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 sta=
te, u32 delay_in_ms)
return 0;
}
=20
-static int alloc_skb_array(struct qtnf_pcie_pearl_state *priv)
+static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
{
struct sk_buff **vaddr;
int len;
@@ -486,8 +442,9 @@ static int alloc_skb_array(struct qtnf_pcie_pearl_state=
*priv)
return 0;
}
=20
-static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv)
+static int alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
dma_addr_t paddr;
void *vaddr;
int len;
@@ -503,12 +460,12 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_stat=
e *priv)
=20
memset(vaddr, 0, len);
=20
- priv->bd_table_vaddr =3D vaddr;
- priv->bd_table_paddr =3D paddr;
- priv->bd_table_len =3D len;
+ ps->bd_table_vaddr =3D vaddr;
+ ps->bd_table_paddr =3D paddr;
+ ps->bd_table_len =3D len;
=20
- priv->tx_bd_vbase =3D vaddr;
- priv->tx_bd_pbase =3D paddr;
+ ps->tx_bd_vbase =3D vaddr;
+ ps->tx_bd_pbase =3D paddr;
=20
pr_debug("TX descriptor table: vaddr=3D0x%p paddr=3D%pad\n", vaddr, &padd=
r);
=20
@@ -520,25 +477,26 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_stat=
e *priv)
vaddr =3D ((struct qtnf_pearl_tx_bd *)vaddr) + priv->tx_bd_num;
paddr +=3D priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd);
=20
- priv->rx_bd_vbase =3D vaddr;
- priv->rx_bd_pbase =3D paddr;
+ ps->rx_bd_vbase =3D vaddr;
+ ps->rx_bd_pbase =3D paddr;
=20
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
writel(QTN_HOST_HI32(paddr),
- PCIE_HDP_TX_HOST_Q_BASE_H(priv->pcie_reg_base));
+ PCIE_HDP_TX_HOST_Q_BASE_H(ps->pcie_reg_base));
#endif
writel(QTN_HOST_LO32(paddr),
- PCIE_HDP_TX_HOST_Q_BASE_L(priv->pcie_reg_base));
+ PCIE_HDP_TX_HOST_Q_BASE_L(ps->pcie_reg_base));
writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16,
- PCIE_HDP_TX_HOST_Q_SZ_CTRL(priv->pcie_reg_base));
+ PCIE_HDP_TX_HOST_Q_SZ_CTRL(ps->pcie_reg_base));
=20
pr_debug("RX descriptor table: vaddr=3D0x%p paddr=3D%pad\n", vaddr, &padd=
r);
=20
return 0;
}
=20
-static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index)
+static int skb2rbd_attach(struct qtnf_pcie_pearl_state *ps, u16 index)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_rx_bd *rxbd;
struct sk_buff *skb;
dma_addr_t paddr;
@@ -550,7 +508,7 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_state =
*priv, u16 index)
}
=20
priv->rx_skb[index] =3D skb;
- rxbd =3D &priv->rx_bd_vbase[index];
+ rxbd =3D &ps->rx_bd_vbase[index];
=20
paddr =3D pci_map_single(priv->pdev, skb->data,
SKB_BUF_SIZE, PCI_DMA_FROMDEVICE);
@@ -571,25 +529,25 @@ static int skb2rbd_attach(struct qtnf_pcie_pearl_stat=
e *priv, u16 index)
=20
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
writel(QTN_HOST_HI32(paddr),
- PCIE_HDP_HHBM_BUF_PTR_H(priv->pcie_reg_base));
+ PCIE_HDP_HHBM_BUF_PTR_H(ps->pcie_reg_base));
#endif
writel(QTN_HOST_LO32(paddr),
- PCIE_HDP_HHBM_BUF_PTR(priv->pcie_reg_base));
+ PCIE_HDP_HHBM_BUF_PTR(ps->pcie_reg_base));
=20
- writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(priv->pcie_reg_base));
+ writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(ps->pcie_reg_base));
return 0;
}
=20
-static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv)
+static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *ps)
{
u16 i;
int ret =3D 0;
=20
- memset(priv->rx_bd_vbase, 0x0,
- priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
+ memset(ps->rx_bd_vbase, 0x0,
+ ps->base.rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
=20
- for (i =3D 0; i < priv->rx_bd_num; i++) {
- ret =3D skb2rbd_attach(priv, i);
+ for (i =3D 0; i < ps->base.rx_bd_num; i++) {
+ ret =3D skb2rbd_attach(ps, i);
if (ret)
break;
}
@@ -598,8 +556,9 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_stat=
e *priv)
}
=20
/* all rx/tx activity should have ceased before calling this function */
-static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_tx_bd *txbd;
struct qtnf_pearl_rx_bd *rxbd;
struct sk_buff *skb;
@@ -609,7 +568,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pea=
rl_state *priv)
/* free rx buffers */
for (i =3D 0; i < priv->rx_bd_num; i++) {
if (priv->rx_skb && priv->rx_skb[i]) {
- rxbd =3D &priv->rx_bd_vbase[i];
+ rxbd =3D &ps->rx_bd_vbase[i];
skb =3D priv->rx_skb[i];
paddr =3D QTN_HOST_ADDR(le32_to_cpu(rxbd->addr_h),
le32_to_cpu(rxbd->addr));
@@ -623,7 +582,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_pea=
rl_state *priv)
/* free tx buffers */
for (i =3D 0; i < priv->tx_bd_num; i++) {
if (priv->tx_skb && priv->tx_skb[i]) {
- txbd =3D &priv->tx_bd_vbase[i];
+ txbd =3D &ps->tx_bd_vbase[i];
skb =3D priv->tx_skb[i];
paddr =3D QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h),
le32_to_cpu(txbd->addr));
@@ -635,26 +594,27 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_p=
earl_state *priv)
}
}
=20
-static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *ps)
{
u32 val;
=20
- val =3D readl(PCIE_HHBM_CONFIG(priv->pcie_reg_base));
+ val =3D readl(PCIE_HHBM_CONFIG(ps->pcie_reg_base));
val |=3D HHBM_CONFIG_SOFT_RESET;
- writel(val, PCIE_HHBM_CONFIG(priv->pcie_reg_base));
+ writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
usleep_range(50, 100);
val &=3D ~HHBM_CONFIG_SOFT_RESET;
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
val |=3D HHBM_64BIT;
#endif
- writel(val, PCIE_HHBM_CONFIG(priv->pcie_reg_base));
- writel(priv->rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(priv->pcie_reg_base));
+ writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
+ writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base));
=20
return 0;
}
=20
-static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
int ret;
u32 val;
=20
@@ -689,7 +649,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *priv)
return -EINVAL;
}
=20
- ret =3D qtnf_hhbm_init(priv);
+ ret =3D qtnf_hhbm_init(ps);
if (ret) {
pr_err("failed to init h/w queues\n");
return ret;
@@ -701,13 +661,13 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl=
_state *priv)
return ret;
}
=20
- ret =3D alloc_bd_table(priv);
+ ret =3D alloc_bd_table(ps);
if (ret) {
pr_err("failed to allocate bd table\n");
return ret;
}
=20
- ret =3D alloc_rx_buffers(priv);
+ ret =3D alloc_rx_buffers(ps);
if (ret) {
pr_err("failed to allocate rx buffers\n");
return ret;
@@ -716,8 +676,9 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *priv)
return ret;
}
=20
-static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv)
+static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct qtnf_pearl_tx_bd *txbd;
struct sk_buff *skb;
unsigned long flags;
@@ -728,7 +689,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_=
pearl_state *priv)
=20
spin_lock_irqsave(&priv->tx_reclaim_lock, flags);
=20
- tx_done_index =3D readl(PCIE_HDP_RX0DMA_CNT(priv->pcie_reg_base))
+ tx_done_index =3D readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
& (priv->tx_bd_num - 1);
=20
i =3D priv->tx_bd_r_index;
@@ -736,7 +697,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_=
pearl_state *priv)
while (CIRC_CNT(tx_done_index, i, priv->tx_bd_num)) {
skb =3D priv->tx_skb[i];
if (likely(skb)) {
- txbd =3D &priv->tx_bd_vbase[i];
+ txbd =3D &ps->tx_bd_vbase[i];
paddr =3D QTN_HOST_ADDR(le32_to_cpu(txbd->addr_h),
le32_to_cpu(txbd->addr));
pci_unmap_single(priv->pdev, paddr, skb->len,
@@ -767,11 +728,13 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pci=
e_pearl_state *priv)
spin_unlock_irqrestore(&priv->tx_reclaim_lock, flags);
}
=20
-static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *ps)
{
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
+
if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
priv->tx_bd_num)) {
- qtnf_pcie_data_tx_reclaim(priv);
+ qtnf_pcie_data_tx_reclaim(ps);
=20
if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
priv->tx_bd_num)) {
@@ -786,7 +749,8 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_s=
tate *priv)
=20
static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
dma_addr_t txbd_paddr, skb_paddr;
struct qtnf_pearl_tx_bd *txbd;
unsigned long flags;
@@ -796,7 +760,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
=20
spin_lock_irqsave(&priv->tx_lock, flags);
=20
- if (!qtnf_tx_queue_ready(priv)) {
+ if (!qtnf_tx_queue_ready(ps)) {
if (skb->dev) {
netif_tx_stop_all_queues(skb->dev);
priv->tx_stopped =3D 1;
@@ -818,7 +782,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
goto tx_done;
}
=20
- txbd =3D &priv->tx_bd_vbase[i];
+ txbd =3D &ps->tx_bd_vbase[i];
txbd->addr =3D cpu_to_le32(QTN_HOST_LO32(skb_paddr));
txbd->addr_h =3D cpu_to_le32(QTN_HOST_HI32(skb_paddr));
=20
@@ -829,14 +793,14 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, st=
ruct sk_buff *skb)
dma_wmb();
=20
/* write new TX descriptor to PCIE_RX_FIFO on EP */
- txbd_paddr =3D priv->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd);
+ txbd_paddr =3D ps->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd);
=20
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
writel(QTN_HOST_HI32(txbd_paddr),
- PCIE_HDP_HOST_WR_DESC0_H(priv->pcie_reg_base));
+ PCIE_HDP_HOST_WR_DESC0_H(ps->pcie_reg_base));
#endif
writel(QTN_HOST_LO32(txbd_paddr),
- PCIE_HDP_HOST_WR_DESC0(priv->pcie_reg_base));
+ PCIE_HDP_HOST_WR_DESC0(ps->pcie_reg_base));
=20
if (++i >=3D priv->tx_bd_num)
i =3D 0;
@@ -854,14 +818,14 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, st=
ruct sk_buff *skb)
priv->tx_done_count++;
spin_unlock_irqrestore(&priv->tx_lock, flags);
=20
- qtnf_pcie_data_tx_reclaim(priv);
+ qtnf_pcie_data_tx_reclaim(ps);
=20
return NETDEV_TX_OK;
}
=20
static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
int ret;
=20
ret =3D qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
@@ -877,54 +841,55 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus,=
struct sk_buff *skb)
static irqreturn_t qtnf_interrupt(int irq, void *data)
{
struct qtnf_bus *bus =3D (struct qtnf_bus *)data;
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
u32 status;
=20
priv->pcie_irq_count++;
- status =3D readl(PCIE_HDP_INT_STATUS(priv->pcie_reg_base));
+ status =3D readl(PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
=20
qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_in);
qtnf_shm_ipc_irq_handler(&priv->shm_ipc_ep_out);
=20
- if (!(status & priv->pcie_irq_mask))
+ if (!(status & ps->pcie_irq_mask))
goto irq_done;
=20
if (status & PCIE_HDP_INT_RX_BITS)
- priv->pcie_irq_rx_count++;
+ ps->pcie_irq_rx_count++;
=20
if (status & PCIE_HDP_INT_TX_BITS)
- priv->pcie_irq_tx_count++;
+ ps->pcie_irq_tx_count++;
=20
if (status & PCIE_HDP_INT_HHBM_UF)
- priv->pcie_irq_uf_count++;
+ ps->pcie_irq_uf_count++;
=20
if (status & PCIE_HDP_INT_RX_BITS) {
- qtnf_dis_rxdone_irq(priv);
+ qtnf_dis_rxdone_irq(ps);
napi_schedule(&bus->mux_napi);
}
=20
if (status & PCIE_HDP_INT_TX_BITS) {
- qtnf_dis_txdone_irq(priv);
+ qtnf_dis_txdone_irq(ps);
tasklet_hi_schedule(&priv->reclaim_tq);
}
=20
irq_done:
/* H/W workaround: clean all bits, not only enabled */
- qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(priv->pcie_reg_base));
+ qtnf_non_posted_write(~0U, PCIE_HDP_INT_STATUS(ps->pcie_reg_base));
=20
if (!priv->msi_enabled)
- qtnf_deassert_intx(priv);
+ qtnf_deassert_intx(ps);
=20
return IRQ_HANDLED;
}
=20
-static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv)
+static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *ps)
{
- u16 index =3D priv->rx_bd_r_index;
+ u16 index =3D ps->base.rx_bd_r_index;
struct qtnf_pearl_rx_bd *rxbd;
u32 descw;
=20
- rxbd =3D &priv->rx_bd_vbase[index];
+ rxbd =3D &ps->rx_bd_vbase[index];
descw =3D le32_to_cpu(rxbd->info);
=20
if (descw & QTN_TXDONE_MASK)
@@ -936,7 +901,8 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_st=
ate *priv)
static int qtnf_rx_poll(struct napi_struct *napi, int budget)
{
struct qtnf_bus *bus =3D container_of(napi, struct qtnf_bus, mux_napi);
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct net_device *ndev =3D NULL;
struct sk_buff *skb =3D NULL;
int processed =3D 0;
@@ -950,13 +916,11 @@ static int qtnf_rx_poll(struct napi_struct *napi, int=
budget)
int ret;
=20
while (processed < budget) {
-
-
- if (!qtnf_rx_data_ready(priv))
+ if (!qtnf_rx_data_ready(ps))
goto rx_out;
=20
r_idx =3D priv->rx_bd_r_index;
- rxbd =3D &priv->rx_bd_vbase[r_idx];
+ rxbd =3D &ps->rx_bd_vbase[r_idx];
descw =3D le32_to_cpu(rxbd->info);
=20
skb =3D priv->rx_skb[r_idx];
@@ -1018,7 +982,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int =
budget)
if (++w_idx >=3D priv->rx_bd_num)
w_idx =3D 0;
=20
- ret =3D skb2rbd_attach(priv, w_idx);
+ ret =3D skb2rbd_attach(ps, w_idx);
if (ret) {
pr_err("failed to allocate new rx_skb[%d]\n",
w_idx);
@@ -1032,7 +996,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int =
budget)
rx_out:
if (processed < budget) {
napi_complete(napi);
- qtnf_en_rxdone_irq(priv);
+ qtnf_en_rxdone_irq(ps);
}
=20
return processed;
@@ -1041,25 +1005,25 @@ static int qtnf_rx_poll(struct napi_struct *napi, i=
nt budget)
static void
qtnf_pcie_data_tx_timeout(struct qtnf_bus *bus, struct net_device *ndev)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
=20
- tasklet_hi_schedule(&priv->reclaim_tq);
+ tasklet_hi_schedule(&ps->base.reclaim_tq);
}
=20
static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
=20
- qtnf_enable_hdp_irqs(priv);
+ qtnf_enable_hdp_irqs(ps);
napi_enable(&bus->mux_napi);
}
=20
static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
=20
napi_disable(&bus->mux_napi);
- qtnf_disable_hdp_irqs(priv);
+ qtnf_disable_hdp_irqs(ps);
}
=20
static const struct qtnf_bus_ops qtnf_pcie_bus_ops =3D {
@@ -1076,7 +1040,7 @@ static const struct qtnf_bus_ops qtnf_pcie_bus_ops =
=3D {
static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "%d\n", priv->mps);
=20
@@ -1086,7 +1050,7 @@ static int qtnf_dbg_mps_show(struct seq_file *s, void=
*data)
static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "%u\n", priv->msi_enabled);
=20
@@ -1096,20 +1060,20 @@ static int qtnf_dbg_msi_show(struct seq_file *s, vo=
id *data)
static int qtnf_dbg_irq_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
- u32 reg =3D readl(PCIE_HDP_INT_EN(priv->pcie_reg_base));
+ struct qtnf_pcie_pearl_state *ps =3D get_bus_priv(bus);
+ u32 reg =3D readl(PCIE_HDP_INT_EN(ps->pcie_reg_base));
u32 status;
=20
- seq_printf(s, "pcie_irq_count(%u)\n", priv->pcie_irq_count);
- seq_printf(s, "pcie_irq_tx_count(%u)\n", priv->pcie_irq_tx_count);
+ seq_printf(s, "pcie_irq_count(%u)\n", ps->base.pcie_irq_count);
+ seq_printf(s, "pcie_irq_tx_count(%u)\n", ps->pcie_irq_tx_count);
status =3D reg & PCIE_HDP_INT_TX_BITS;
seq_printf(s, "pcie_irq_tx_status(%s)\n",
(status =3D=3D PCIE_HDP_INT_TX_BITS) ? "EN" : "DIS");
- seq_printf(s, "pcie_irq_rx_count(%u)\n", priv->pcie_irq_rx_count);
+ seq_printf(s, "pcie_irq_rx_count(%u)\n", ps->pcie_irq_rx_count);
status =3D reg & PCIE_HDP_INT_RX_BITS;
seq_printf(s, "pcie_irq_rx_status(%s)\n",
(status =3D=3D PCIE_HDP_INT_RX_BITS) ? "EN" : "DIS");
- seq_printf(s, "pcie_irq_uf_count(%u)\n", priv->pcie_irq_uf_count);
+ seq_printf(s, "pcie_irq_uf_count(%u)\n", ps->pcie_irq_uf_count);
status =3D reg & PCIE_HDP_INT_HHBM_UF;
seq_printf(s, "pcie_irq_hhbm_uf_status(%s)\n",
(status =3D=3D PCIE_HDP_INT_HHBM_UF) ? "EN" : "DIS");
@@ -1120,7 +1084,8 @@ static int qtnf_dbg_irq_stats(struct seq_file *s, voi=
d *data)
static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D &ps->base;
=20
seq_printf(s, "tx_full_count(%u)\n", priv->tx_full_count);
seq_printf(s, "tx_done_count(%u)\n", priv->tx_done_count);
@@ -1129,7 +1094,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, voi=
d *data)
=20
seq_printf(s, "tx_bd_r_index(%u)\n", priv->tx_bd_r_index);
seq_printf(s, "tx_bd_p_index(%u)\n",
- readl(PCIE_HDP_RX0DMA_CNT(priv->pcie_reg_base))
+ readl(PCIE_HDP_RX0DMA_CNT(ps->pcie_reg_base))
& (priv->tx_bd_num - 1));
seq_printf(s, "tx_bd_w_index(%u)\n", priv->tx_bd_w_index);
seq_printf(s, "tx queue len(%u)\n",
@@ -1138,7 +1103,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, voi=
d *data)
=20
seq_printf(s, "rx_bd_r_index(%u)\n", priv->rx_bd_r_index);
seq_printf(s, "rx_bd_p_index(%u)\n",
- readl(PCIE_HDP_TX0DMA_CNT(priv->pcie_reg_base))
+ readl(PCIE_HDP_TX0DMA_CNT(ps->pcie_reg_base))
& (priv->rx_bd_num - 1));
seq_printf(s, "rx_bd_w_index(%u)\n", priv->rx_bd_w_index);
seq_printf(s, "rx alloc queue len(%u)\n",
@@ -1151,7 +1116,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, voi=
d *data)
static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
priv->shm_ipc_ep_in.tx_packet_count);
@@ -1165,10 +1130,10 @@ static int qtnf_dbg_shm_stats(struct seq_file *s, v=
oid *data)
return 0;
}
=20
-static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t si=
ze,
+static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *ps, uint32_t size=
,
int blk, const u8 *pblk, const u8 *fw)
{
- struct pci_dev *pdev =3D priv->pdev;
+ struct pci_dev *pdev =3D ps->base.pdev;
struct qtnf_bus *bus =3D pci_get_drvdata(pdev);
=20
struct qtnf_pearl_fw_hdr *hdr;
@@ -1214,7 +1179,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_sta=
te *priv, uint32_t size,
}
=20
static int
-qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_s=
ize)
+qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, const u8 *fw, u32 fw_siz=
e)
{
int blk_size =3D QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pearl_fw_hdr);
int blk_count =3D fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0);
@@ -1231,25 +1196,25 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv,=
const u8 *fw, u32 fw_size)
return -ETIMEDOUT;
}
=20
- len =3D qtnf_ep_fw_send(priv, fw_size, blk, pblk, fw);
+ len =3D qtnf_ep_fw_send(ps, fw_size, blk, pblk, fw);
if (len <=3D 0)
continue;
=20
if (!((blk + 1) & QTN_PCIE_FW_DLMASK) ||
(blk =3D=3D (blk_count - 1))) {
- qtnf_set_state(&priv->bda->bda_rc_state,
+ qtnf_set_state(&ps->bda->bda_rc_state,
QTN_RC_FW_SYNC);
- if (qtnf_poll_state(&priv->bda->bda_ep_state,
+ if (qtnf_poll_state(&ps->bda->bda_ep_state,
QTN_EP_FW_SYNC,
QTN_FW_DL_TIMEOUT_MS)) {
pr_err("FW upload failed: SYNC timed out\n");
return -ETIMEDOUT;
}
=20
- qtnf_clear_state(&priv->bda->bda_ep_state,
+ qtnf_clear_state(&ps->bda->bda_ep_state,
QTN_EP_FW_SYNC);
=20
- if (qtnf_is_state(&priv->bda->bda_ep_state,
+ if (qtnf_is_state(&ps->bda->bda_ep_state,
QTN_EP_FW_RETRY)) {
if (blk =3D=3D (blk_count - 1)) {
int last_round =3D
@@ -1262,14 +1227,14 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv,=
const u8 *fw, u32 fw_size)
pblk -=3D QTN_PCIE_FW_DLMASK * blk_size;
}
=20
- qtnf_clear_state(&priv->bda->bda_ep_state,
+ qtnf_clear_state(&ps->bda->bda_ep_state,
QTN_EP_FW_RETRY);
=20
pr_warn("FW upload retry: block #%d\n", blk);
continue;
}
=20
- qtnf_pcie_data_tx_reclaim(priv);
+ qtnf_pcie_data_tx_reclaim(ps);
}
=20
pblk +=3D len;
@@ -1283,8 +1248,8 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, c=
onst u8 *fw, u32 fw_size)
static void qtnf_fw_work_handler(struct work_struct *work)
{
struct qtnf_bus *bus =3D container_of(work, struct qtnf_bus, fw_work);
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
- struct pci_dev *pdev =3D priv->pdev;
+ struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct pci_dev *pdev =3D ps->base.pdev;
const struct firmware *fw;
int ret;
u32 state =3D QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK;
@@ -1300,9 +1265,9 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
}
}
=20
- qtnf_set_state(&priv->bda->bda_rc_state, state);
+ qtnf_set_state(&ps->bda->bda_rc_state, state);
=20
- if (qtnf_poll_state(&priv->bda->bda_ep_state, QTN_EP_FW_LOADRDY,
+ if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY,
QTN_FW_DL_TIMEOUT_MS)) {
pr_err("card is not ready\n");
=20
@@ -1312,14 +1277,14 @@ static void qtnf_fw_work_handler(struct work_struct=
*work)
goto fw_load_fail;
}
=20
- qtnf_clear_state(&priv->bda->bda_ep_state, QTN_EP_FW_LOADRDY);
+ qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY);
=20
if (flashboot) {
pr_info("booting firmware from flash\n");
} else {
pr_info("starting firmware upload: %s\n", fwname);
=20
- ret =3D qtnf_ep_fw_load(priv, fw->data, fw->size);
+ ret =3D qtnf_ep_fw_load(ps, fw->data, fw->size);
release_firmware(fw);
if (ret) {
pr_err("firmware upload error\n");
@@ -1327,7 +1292,7 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
}
}
=20
- if (qtnf_poll_state(&priv->bda->bda_ep_state, QTN_EP_FW_DONE,
+ if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE,
QTN_FW_DL_TIMEOUT_MS)) {
pr_err("firmware bringup timed out\n");
goto fw_load_fail;
@@ -1336,7 +1301,7 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
bus->fw_state =3D QTNF_FW_STATE_FW_DNLD_DONE;
pr_info("firmware is up and running\n");
=20
- if (qtnf_poll_state(&priv->bda->bda_ep_state,
+ if (qtnf_poll_state(&ps->bda->bda_ep_state,
QTN_EP_FW_QLINK_DONE, QTN_FW_QLINK_TIMEOUT_MS)) {
pr_err("firmware runtime failure\n");
goto fw_load_fail;
@@ -1367,7 +1332,7 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
=20
static void qtnf_bringup_fw_async(struct qtnf_bus *bus)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
struct pci_dev *pdev =3D priv->pdev;
=20
get_device(&pdev->dev);
@@ -1377,56 +1342,56 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *=
bus)
=20
static void qtnf_reclaim_tasklet_fn(unsigned long data)
{
- struct qtnf_pcie_pearl_state *priv =3D (void *)data;
+ struct qtnf_pcie_pearl_state *ps =3D (void *)data;
=20
- qtnf_pcie_data_tx_reclaim(priv);
- qtnf_en_txdone_irq(priv);
+ qtnf_pcie_data_tx_reclaim(ps);
+ qtnf_en_txdone_irq(ps);
}
=20
static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_i=
d *id)
{
- struct qtnf_pcie_pearl_state *pcie_priv;
+ struct qtnf_pcie_pearl_state *ps;
struct qtnf_bus *bus;
int ret;
=20
bus =3D devm_kzalloc(&pdev->dev,
- sizeof(*bus) + sizeof(*pcie_priv), GFP_KERNEL);
+ sizeof(*bus) + sizeof(*ps), GFP_KERNEL);
if (!bus)
return -ENOMEM;
=20
- pcie_priv =3D get_bus_priv(bus);
+ ps =3D get_bus_priv(bus);
=20
pci_set_drvdata(pdev, bus);
bus->bus_ops =3D &qtnf_pcie_bus_ops;
bus->dev =3D &pdev->dev;
bus->fw_state =3D QTNF_FW_STATE_RESET;
- pcie_priv->pdev =3D pdev;
+ ps->base.pdev =3D pdev;
=20
init_completion(&bus->firmware_init_complete);
mutex_init(&bus->bus_lock);
- spin_lock_init(&pcie_priv->tx_lock);
- spin_lock_init(&pcie_priv->irq_lock);
- spin_lock_init(&pcie_priv->tx_reclaim_lock);
+ spin_lock_init(&ps->base.tx_lock);
+ spin_lock_init(&ps->irq_lock);
+ spin_lock_init(&ps->base.tx_reclaim_lock);
=20
/* init stats */
- pcie_priv->tx_full_count =3D 0;
- pcie_priv->tx_done_count =3D 0;
- pcie_priv->pcie_irq_count =3D 0;
- pcie_priv->pcie_irq_rx_count =3D 0;
- pcie_priv->pcie_irq_tx_count =3D 0;
- pcie_priv->pcie_irq_uf_count =3D 0;
- pcie_priv->tx_reclaim_done =3D 0;
- pcie_priv->tx_reclaim_req =3D 0;
-
- tasklet_init(&pcie_priv->reclaim_tq, qtnf_reclaim_tasklet_fn,
- (unsigned long)pcie_priv);
+ ps->base.tx_full_count =3D 0;
+ ps->base.tx_done_count =3D 0;
+ ps->base.pcie_irq_count =3D 0;
+ ps->pcie_irq_rx_count =3D 0;
+ ps->pcie_irq_tx_count =3D 0;
+ ps->pcie_irq_uf_count =3D 0;
+ ps->base.tx_reclaim_done =3D 0;
+ ps->base.tx_reclaim_req =3D 0;
+
+ tasklet_init(&ps->base.reclaim_tq, qtnf_reclaim_tasklet_fn,
+ (unsigned long)ps);
=20
init_dummy_netdev(&bus->mux_dev);
netif_napi_add(&bus->mux_dev, &bus->mux_napi,
qtnf_rx_poll, 10);
=20
- pcie_priv->workqueue =3D create_singlethread_workqueue("QTNF_PEARL_PCIE")=
;
- if (!pcie_priv->workqueue) {
+ ps->base.workqueue =3D create_singlethread_workqueue("QTNF_PEARL_PCIE");
+ if (!ps->base.workqueue) {
pr_err("failed to alloc bus workqueue\n");
ret =3D -ENODEV;
goto err_init;
@@ -1438,7 +1403,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
goto err_base;
}
=20
- qtnf_tune_pcie_mps(pcie_priv);
+ qtnf_tune_pcie_mps(&ps->base);
=20
ret =3D pcim_enable_device(pdev);
if (ret) {
@@ -1459,9 +1424,9 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
}
=20
pci_set_master(pdev);
- qtnf_pcie_init_irq(pcie_priv);
+ qtnf_pcie_init_irq(&ps->base);
=20
- ret =3D qtnf_pcie_init_memory(pcie_priv);
+ ret =3D qtnf_pcie_init_memory(ps);
if (ret < 0) {
pr_err("PCIE memory init failed\n");
goto err_base;
@@ -1469,23 +1434,23 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, co=
nst struct pci_device_id *id)
=20
pci_save_state(pdev);
=20
- ret =3D qtnf_pcie_init_shm_ipc(pcie_priv);
+ ret =3D qtnf_pcie_init_shm_ipc(ps);
if (ret < 0) {
pr_err("PCIE SHM IPC init failed\n");
goto err_base;
}
=20
- ret =3D qtnf_pcie_init_xfer(pcie_priv);
+ ret =3D qtnf_pcie_init_xfer(ps);
if (ret) {
pr_err("PCIE xfer init failed\n");
goto err_ipc;
}
=20
/* init default irq settings */
- qtnf_init_hdp_irqs(pcie_priv);
+ qtnf_init_hdp_irqs(ps);
=20
/* start with disabled irqs */
- qtnf_disable_hdp_irqs(pcie_priv);
+ qtnf_disable_hdp_irqs(ps);
=20
ret =3D devm_request_irq(&pdev->dev, pdev->irq, &qtnf_interrupt, 0,
"qtnf_pcie_irq", (void *)bus);
@@ -1499,18 +1464,18 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, co=
nst struct pci_device_id *id)
return 0;
=20
err_xfer:
- qtnf_free_xfer_buffers(pcie_priv);
+ qtnf_free_xfer_buffers(ps);
=20
err_ipc:
- qtnf_pcie_free_shm_ipc(pcie_priv);
+ qtnf_pcie_free_shm_ipc(&ps->base);
=20
err_base:
- flush_workqueue(pcie_priv->workqueue);
- destroy_workqueue(pcie_priv->workqueue);
- netif_napi_del(&bus->mux_napi);
+ flush_workqueue(ps->base.workqueue);
+ destroy_workqueue(ps->base.workqueue);
=20
err_init:
- tasklet_kill(&pcie_priv->reclaim_tq);
+ tasklet_kill(&ps->base.reclaim_tq);
+ netif_napi_del(&bus->mux_napi);
pci_set_drvdata(pdev, NULL);
=20
return ret;
@@ -1518,7 +1483,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
=20
static void qtnf_pcie_remove(struct pci_dev *pdev)
{
- struct qtnf_pcie_pearl_state *priv;
+ struct qtnf_pcie_pearl_state *ps;
struct qtnf_bus *bus;
=20
bus =3D pci_get_drvdata(pdev);
@@ -1531,18 +1496,16 @@ static void qtnf_pcie_remove(struct pci_dev *pdev)
bus->fw_state =3D=3D QTNF_FW_STATE_EP_DEAD)
qtnf_core_detach(bus);
=20
- priv =3D get_bus_priv(bus);
-
+ ps =3D get_bus_priv(bus);
+ qtnf_reset_card(ps);
netif_napi_del(&bus->mux_napi);
- flush_workqueue(priv->workqueue);
- destroy_workqueue(priv->workqueue);
- tasklet_kill(&priv->reclaim_tq);
+ flush_workqueue(ps->base.workqueue);
+ destroy_workqueue(ps->base.workqueue);
+ tasklet_kill(&ps->base.reclaim_tq);
=20
- qtnf_free_xfer_buffers(priv);
+ qtnf_free_xfer_buffers(ps);
+ qtnf_pcie_free_shm_ipc(&ps->base);
qtnf_debugfs_remove(bus);
-
- qtnf_pcie_free_shm_ipc(priv);
- qtnf_reset_card(priv);
}
=20
#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b=
/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
index af528b8..b87505d 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
@@ -43,11 +43,6 @@
#define QTN_RC_FW_LOADRDY BIT(8)
#define QTN_RC_FW_SYNC BIT(9)
=20
-/* state transition timeouts */
-#define QTN_FW_DL_TIMEOUT_MS 3000
-#define QTN_FW_QLINK_TIMEOUT_MS 30000
-#define QTN_EP_RESET_WAIT_MS 1000
-
#define PCIE_HDP_INT_RX_BITS (0 \
| PCIE_HDP_INT_EP_TXDMA \
| PCIE_HDP_INT_EP_TXEMPTY \
@@ -77,8 +72,6 @@
#define PCIE_BDA_NAMELEN 32
#define PCIE_HHBM_MAX_SIZE 2048
=20
-#define SKB_BUF_SIZE 2048
-
#define QTN_PCIE_BOARDFLG "PCIEQTN"
#define QTN_PCIE_FW_DLMASK 0xF
#define QTN_PCIE_FW_BUFSZ 2048
--=20
2.9.5
tx_lock name will later be reused when common pcie code is extracted to
separate files.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 4e9eb46..791a1e3 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -110,7 +110,7 @@ struct qtnf_pcie_pearl_state {
/* lock for tx reclaim operations */
spinlock_t tx_reclaim_lock;
/* lock for tx0 operations */
- spinlock_t tx0_lock;
+ spinlock_t tx_lock;
u8 msi_enabled;
u8 tx_stopped;
int mps;
@@ -794,7 +794,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
u32 info;
int ret =3D 0;
=20
- spin_lock_irqsave(&priv->tx0_lock, flags);
+ spin_lock_irqsave(&priv->tx_lock, flags);
=20
if (!qtnf_tx_queue_ready(priv)) {
if (skb->dev) {
@@ -802,7 +802,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
priv->tx_stopped =3D 1;
}
=20
- spin_unlock_irqrestore(&priv->tx0_lock, flags);
+ spin_unlock_irqrestore(&priv->tx_lock, flags);
return NETDEV_TX_BUSY;
}
=20
@@ -852,7 +852,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
}
=20
priv->tx_done_count++;
- spin_unlock_irqrestore(&priv->tx0_lock, flags);
+ spin_unlock_irqrestore(&priv->tx_lock, flags);
=20
qtnf_pcie_data_tx_reclaim(priv);
=20
@@ -1404,7 +1404,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
=20
init_completion(&bus->firmware_init_complete);
mutex_init(&bus->bus_lock);
- spin_lock_init(&pcie_priv->tx0_lock);
+ spin_lock_init(&pcie_priv->tx_lock);
spin_lock_init(&pcie_priv->irq_lock);
spin_lock_init(&pcie_priv->tx_reclaim_lock);
=20
--=20
2.9.5
Extract platform-independent PCIe driver code into a separate file, and
use it from platform-specific modules.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/Makefile | 1 +
drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c | 406 +++++++++++++++++=
+++
.../wireless/quantenna/qtnfmac/pcie/pcie_priv.h | 15 +
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 425 +++--------------=
----
.../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 4 -
5 files changed, 468 insertions(+), 383 deletions(-)
create mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
diff --git a/drivers/net/wireless/quantenna/qtnfmac/Makefile b/drivers/net/=
wireless/quantenna/qtnfmac/Makefile
index 9eeddea..17cd7ad 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/Makefile
+++ b/drivers/net/wireless/quantenna/qtnfmac/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_QTNFMAC_PEARL_PCIE) +=3D qtnfmac_pearl_pcie.=
o
=20
qtnfmac_pearl_pcie-objs +=3D \
shm_ipc.o \
+ pcie/pcie.o \
pcie/pearl_pcie.o
=20
qtnfmac_pearl_pcie-$(CONFIG_DEBUG_FS) +=3D debug.o
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c b/drivers/n=
et/wireless/quantenna/qtnfmac/pcie/pcie.c
new file mode 100644
index 0000000..ab42d11
--- /dev/null
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2018 Quantenna Communications, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/printk.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/netdevice.h>
+#include <linux/seq_file.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+
+#include "pcie_priv.h"
+#include "bus.h"
+#include "shm_ipc.h"
+#include "core.h"
+#include "debug.h"
+
+#undef pr_fmt
+#define pr_fmt(fmt) "qtnf_pcie: %s: " fmt, __func__
+
+#define QTN_SYSCTL_BAR 0
+#define QTN_SHMEM_BAR 2
+#define QTN_DMA_BAR 3
+
+int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
+{
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ int ret;
+
+ ret =3D qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
+
+ if (ret =3D=3D -ETIMEDOUT) {
+ pr_err("EP firmware is dead\n");
+ bus->fw_state =3D QTNF_FW_STATE_EP_DEAD;
+ }
+
+ return ret;
+}
+
+int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
+{
+ struct sk_buff **vaddr;
+ int len;
+
+ len =3D priv->tx_bd_num * sizeof(*priv->tx_skb) +
+ priv->rx_bd_num * sizeof(*priv->rx_skb);
+ vaddr =3D devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL);
+
+ if (!vaddr)
+ return -ENOMEM;
+
+ priv->tx_skb =3D vaddr;
+
+ vaddr +=3D priv->tx_bd_num;
+ priv->rx_skb =3D vaddr;
+
+ return 0;
+}
+
+void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus)
+{
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct pci_dev *pdev =3D priv->pdev;
+
+ get_device(&pdev->dev);
+ schedule_work(&bus->fw_work);
+}
+
+static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
+{
+ struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+
+ seq_printf(s, "%d\n", priv->mps);
+
+ return 0;
+}
+
+static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
+{
+ struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+
+ seq_printf(s, "%u\n", priv->msi_enabled);
+
+ return 0;
+}
+
+static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
+{
+ struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+
+ seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
+ priv->shm_ipc_ep_in.tx_packet_count);
+ seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n",
+ priv->shm_ipc_ep_in.rx_packet_count);
+ seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n",
+ priv->shm_ipc_ep_out.tx_timeout_count);
+ seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n",
+ priv->shm_ipc_ep_out.rx_packet_count);
+
+ return 0;
+}
+
+void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success,
+ const char *drv_name)
+{
+ struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct pci_dev *pdev =3D priv->pdev;
+ int ret;
+
+ if (boot_success) {
+ bus->fw_state =3D QTNF_FW_STATE_FW_DNLD_DONE;
+
+ ret =3D qtnf_core_attach(bus);
+ if (ret) {
+ pr_err("failed to attach core\n");
+ boot_success =3D false;
+ }
+ }
+
+ if (boot_success) {
+ qtnf_debugfs_init(bus, drv_name);
+ qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show);
+ qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show);
+ qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats);
+ } else {
+ bus->fw_state =3D QTNF_FW_STATE_DETACHED;
+ }
+
+ complete(&bus->firmware_init_complete);
+ put_device(&pdev->dev);
+}
+
+static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv)
+{
+ struct pci_dev *pdev =3D priv->pdev;
+ struct pci_dev *parent;
+ int mps_p, mps_o, mps_m, mps;
+ int ret;
+
+ /* current mps */
+ mps_o =3D pcie_get_mps(pdev);
+
+ /* maximum supported mps */
+ mps_m =3D 128 << pdev->pcie_mpss;
+
+ /* suggested new mps value */
+ mps =3D mps_m;
+
+ if (pdev->bus && pdev->bus->self) {
+ /* parent (bus) mps */
+ parent =3D pdev->bus->self;
+
+ if (pci_is_pcie(parent)) {
+ mps_p =3D pcie_get_mps(parent);
+ mps =3D min(mps_m, mps_p);
+ }
+ }
+
+ ret =3D pcie_set_mps(pdev, mps);
+ if (ret) {
+ pr_err("failed to set mps to %d, keep using current %d\n",
+ mps, mps_o);
+ priv->mps =3D mps_o;
+ return;
+ }
+
+ pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m);
+ priv->mps =3D mps;
+}
+
+static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv, bool use_m=
si)
+{
+ struct pci_dev *pdev =3D priv->pdev;
+
+ /* fall back to legacy INTx interrupts by default */
+ priv->msi_enabled =3D 0;
+
+ /* check if MSI capability is available */
+ if (use_msi) {
+ if (!pci_enable_msi(pdev)) {
+ pr_debug("enabled MSI interrupt\n");
+ priv->msi_enabled =3D 1;
+ } else {
+ pr_warn("failed to enable MSI interrupts");
+ }
+ }
+
+ if (!priv->msi_enabled) {
+ pr_warn("legacy PCIE interrupts enabled\n");
+ pci_intx(pdev, 1);
+ }
+}
+
+static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 inde=
x)
+{
+ void __iomem *vaddr;
+ dma_addr_t busaddr;
+ size_t len;
+ int ret;
+
+ ret =3D pcim_iomap_regions(priv->pdev, 1 << index, "qtnfmac_pcie");
+ if (ret)
+ return IOMEM_ERR_PTR(ret);
+
+ busaddr =3D pci_resource_start(priv->pdev, index);
+ len =3D pci_resource_len(priv->pdev, index);
+ vaddr =3D pcim_iomap_table(priv->pdev)[index];
+ if (!vaddr)
+ return IOMEM_ERR_PTR(-ENOMEM);
+
+ pr_debug("BAR%u vaddr=3D0x%p busaddr=3D%pad len=3D%u\n",
+ index, vaddr, &busaddr, (int)len);
+
+ return vaddr;
+}
+
+static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv)
+{
+ int ret =3D -ENOMEM;
+
+ priv->sysctl_bar =3D qtnf_map_bar(priv, QTN_SYSCTL_BAR);
+ if (IS_ERR(priv->sysctl_bar)) {
+ pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR);
+ return ret;
+ }
+
+ priv->dmareg_bar =3D qtnf_map_bar(priv, QTN_DMA_BAR);
+ if (IS_ERR(priv->dmareg_bar)) {
+ pr_err("failed to map BAR%u\n", QTN_DMA_BAR);
+ return ret;
+ }
+
+ priv->epmem_bar =3D qtnf_map_bar(priv, QTN_SHMEM_BAR);
+ if (IS_ERR(priv->epmem_bar)) {
+ pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t=
len)
+{
+ struct qtnf_pcie_bus_priv *priv =3D arg;
+ struct qtnf_bus *bus =3D pci_get_drvdata(priv->pdev);
+ struct sk_buff *skb;
+
+ if (unlikely(len =3D=3D 0)) {
+ pr_warn("zero length packet received\n");
+ return;
+ }
+
+ skb =3D __dev_alloc_skb(len, GFP_KERNEL);
+
+ if (unlikely(!skb)) {
+ pr_err("failed to allocate skb\n");
+ return;
+ }
+
+ skb_put_data(skb, buf, len);
+
+ qtnf_trans_handle_rx_ctl_packet(bus, skb);
+}
+
+void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
+ struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
+ struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
+ const struct qtnf_shm_ipc_int *ipc_int)
+{
+ const struct qtnf_shm_ipc_rx_callback rx_callback =3D {
+ qtnf_pcie_control_rx_callback, priv };
+
+ qtnf_shm_ipc_init(&priv->shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
+ ipc_tx_reg, priv->workqueue,
+ ipc_int, &rx_callback);
+ qtnf_shm_ipc_init(&priv->shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
+ ipc_rx_reg, priv->workqueue,
+ ipc_int, &rx_callback);
+}
+
+int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size,
+ const struct qtnf_bus_ops *bus_ops, u64 dma_mask,
+ bool use_msi)
+{
+ struct qtnf_pcie_bus_priv *pcie_priv;
+ struct qtnf_bus *bus;
+ int ret;
+
+ bus =3D devm_kzalloc(&pdev->dev,
+ sizeof(*bus) + priv_size, GFP_KERNEL);
+ if (!bus)
+ return -ENOMEM;
+
+ pcie_priv =3D get_bus_priv(bus);
+
+ pci_set_drvdata(pdev, bus);
+ bus->bus_ops =3D bus_ops;
+ bus->dev =3D &pdev->dev;
+ bus->fw_state =3D QTNF_FW_STATE_RESET;
+ pcie_priv->pdev =3D pdev;
+ pcie_priv->tx_stopped =3D 0;
+
+ init_completion(&bus->firmware_init_complete);
+ mutex_init(&bus->bus_lock);
+ spin_lock_init(&pcie_priv->tx_lock);
+ spin_lock_init(&pcie_priv->tx_reclaim_lock);
+
+ pcie_priv->tx_full_count =3D 0;
+ pcie_priv->tx_done_count =3D 0;
+ pcie_priv->pcie_irq_count =3D 0;
+ pcie_priv->tx_reclaim_done =3D 0;
+ pcie_priv->tx_reclaim_req =3D 0;
+
+ pcie_priv->workqueue =3D create_singlethread_workqueue("QTNF_PCIE");
+ if (!pcie_priv->workqueue) {
+ pr_err("failed to alloc bus workqueue\n");
+ ret =3D -ENODEV;
+ goto err_init;
+ }
+
+ init_dummy_netdev(&bus->mux_dev);
+
+ if (!pci_is_pcie(pdev)) {
+ pr_err("device %s is not PCI Express\n", pci_name(pdev));
+ ret =3D -EIO;
+ goto err_base;
+ }
+
+ qtnf_tune_pcie_mps(pcie_priv);
+
+ ret =3D pcim_enable_device(pdev);
+ if (ret) {
+ pr_err("failed to init PCI device %x\n", pdev->device);
+ goto err_base;
+ } else {
+ pr_debug("successful init of PCI device %x\n", pdev->device);
+ }
+
+ ret =3D dma_set_mask_and_coherent(&pdev->dev, dma_mask);
+ if (ret) {
+ pr_err("PCIE DMA coherent mask init failed\n");
+ goto err_base;
+ }
+
+ pci_set_master(pdev);
+ qtnf_pcie_init_irq(pcie_priv, use_msi);
+
+ ret =3D qtnf_pcie_init_memory(pcie_priv);
+ if (ret < 0) {
+ pr_err("PCIE memory init failed\n");
+ goto err_base;
+ }
+
+ pci_save_state(pdev);
+
+ return 0;
+
+err_base:
+ flush_workqueue(pcie_priv->workqueue);
+ destroy_workqueue(pcie_priv->workqueue);
+err_init:
+ pci_set_drvdata(pdev, NULL);
+
+ return ret;
+}
+
+static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
+{
+ qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
+ qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
+}
+
+void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *pri=
v)
+{
+ wait_for_completion(&bus->firmware_init_complete);
+
+ if (bus->fw_state =3D=3D QTNF_FW_STATE_ACTIVE ||
+ bus->fw_state =3D=3D QTNF_FW_STATE_EP_DEAD)
+ qtnf_core_detach(bus);
+
+ netif_napi_del(&bus->mux_napi);
+ flush_workqueue(priv->workqueue);
+ destroy_workqueue(priv->workqueue);
+ tasklet_kill(&priv->reclaim_tq);
+
+ qtnf_pcie_free_shm_ipc(priv);
+ qtnf_debugfs_remove(bus);
+ pci_set_drvdata(priv->pdev, NULL);
+}
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h b/driv=
ers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
index 1ad5eb8..d3b52f0 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
@@ -25,6 +25,7 @@
#include <linux/interrupt.h>
=20
#include "shm_ipc.h"
+#include "bus.h"
=20
#define SKB_BUF_SIZE 2048
=20
@@ -72,6 +73,20 @@ struct qtnf_pcie_bus_priv {
u8 tx_stopped;
};
=20
+int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb);
+int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv);
+void qtnf_pcie_bringup_fw_async(struct qtnf_bus *bus);
+void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool boot_success,
+ const char *drv_name);
+void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
+ struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
+ struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
+ const struct qtnf_shm_ipc_int *ipc_int);
+int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_size,
+ const struct qtnf_bus_ops *bus_ops, u64 dma_mask,
+ bool use_msi);
+void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *pri=
v);
+
static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
{
writel(val, basereg);
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index f3655de..424e367 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -193,29 +193,6 @@ static inline void qtnf_dis_txdone_irq(struct qtnf_pci=
e_pearl_state *ps)
spin_unlock_irqrestore(&ps->irq_lock, flags);
}
=20
-static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv)
-{
- struct pci_dev *pdev =3D priv->pdev;
-
- /* fall back to legacy INTx interrupts by default */
- priv->msi_enabled =3D 0;
-
- /* check if MSI capability is available */
- if (use_msi) {
- if (!pci_enable_msi(pdev)) {
- pr_debug("MSI interrupt enabled\n");
- priv->msi_enabled =3D 1;
- } else {
- pr_warn("failed to enable MSI interrupts");
- }
- }
-
- if (!priv->msi_enabled) {
- pr_warn("legacy PCIE interrupts enabled\n");
- pci_intx(pdev, 1);
- }
-}
-
static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *ps)
{
void __iomem *reg =3D ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
@@ -247,148 +224,6 @@ static void qtnf_pcie_pearl_ipc_gen_ep_int(void *arg)
qtnf_non_posted_write(data, reg);
}
=20
-static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 inde=
x)
-{
- void __iomem *vaddr;
- dma_addr_t busaddr;
- size_t len;
- int ret;
-
- ret =3D pcim_iomap_regions(priv->pdev, 1 << index, DRV_NAME);
- if (ret)
- return IOMEM_ERR_PTR(ret);
-
- busaddr =3D pci_resource_start(priv->pdev, index);
- len =3D pci_resource_len(priv->pdev, index);
- vaddr =3D pcim_iomap_table(priv->pdev)[index];
- if (!vaddr)
- return IOMEM_ERR_PTR(-ENOMEM);
-
- pr_debug("BAR%u vaddr=3D0x%p busaddr=3D%pad len=3D%u\n",
- index, vaddr, &busaddr, (int)len);
-
- return vaddr;
-}
-
-static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t=
len)
-{
- struct qtnf_pcie_bus_priv *priv =3D arg;
- struct qtnf_bus *bus =3D pci_get_drvdata(priv->pdev);
- struct sk_buff *skb;
-
- if (unlikely(len =3D=3D 0)) {
- pr_warn("zero length packet received\n");
- return;
- }
-
- skb =3D __dev_alloc_skb(len, GFP_KERNEL);
-
- if (unlikely(!skb)) {
- pr_err("failed to allocate skb\n");
- return;
- }
-
- skb_put_data(skb, buf, len);
-
- qtnf_trans_handle_rx_ctl_packet(bus, skb);
-}
-
-static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *ps)
-{
- struct qtnf_shm_ipc_region __iomem *ipc_tx_reg;
- struct qtnf_shm_ipc_region __iomem *ipc_rx_reg;
- const struct qtnf_shm_ipc_int ipc_int =3D
- { qtnf_pcie_pearl_ipc_gen_ep_int, ps };
- const struct qtnf_shm_ipc_rx_callback rx_callback =3D {
- qtnf_pcie_control_rx_callback, ps };
-
- ipc_tx_reg =3D &ps->bda->bda_shm_reg1;
- ipc_rx_reg =3D &ps->bda->bda_shm_reg2;
-
- qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_in, QTNF_SHM_IPC_OUTBOUND,
- ipc_tx_reg, ps->base.workqueue,
- &ipc_int, &rx_callback);
- qtnf_shm_ipc_init(&ps->base.shm_ipc_ep_out, QTNF_SHM_IPC_INBOUND,
- ipc_rx_reg, ps->base.workqueue,
- &ipc_int, &rx_callback);
-
- return 0;
-}
-
-static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
-{
- qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
- qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
-}
-
-static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *ps)
-{
- struct qtnf_pcie_bus_priv *priv =3D &ps->base;
- int ret =3D -ENOMEM;
-
- priv->sysctl_bar =3D qtnf_map_bar(priv, QTN_SYSCTL_BAR);
- if (IS_ERR(priv->sysctl_bar)) {
- pr_err("failed to map BAR%u\n", QTN_SYSCTL_BAR);
- return ret;
- }
-
- priv->dmareg_bar =3D qtnf_map_bar(priv, QTN_DMA_BAR);
- if (IS_ERR(priv->dmareg_bar)) {
- pr_err("failed to map BAR%u\n", QTN_DMA_BAR);
- return ret;
- }
-
- priv->epmem_bar =3D qtnf_map_bar(priv, QTN_SHMEM_BAR);
- if (IS_ERR(priv->epmem_bar)) {
- pr_err("failed to map BAR%u\n", QTN_SHMEM_BAR);
- return ret;
- }
-
- ps->pcie_reg_base =3D priv->dmareg_bar;
- ps->bda =3D priv->epmem_bar;
- writel(priv->msi_enabled, &ps->bda->bda_rc_msi_enabled);
-
- return 0;
-}
-
-static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv)
-{
- struct pci_dev *pdev =3D priv->pdev;
- struct pci_dev *parent;
- int mps_p, mps_o, mps_m, mps;
- int ret;
-
- /* current mps */
- mps_o =3D pcie_get_mps(pdev);
-
- /* maximum supported mps */
- mps_m =3D 128 << pdev->pcie_mpss;
-
- /* suggested new mps value */
- mps =3D mps_m;
-
- if (pdev->bus && pdev->bus->self) {
- /* parent (bus) mps */
- parent =3D pdev->bus->self;
-
- if (pci_is_pcie(parent)) {
- mps_p =3D pcie_get_mps(parent);
- mps =3D min(mps_m, mps_p);
- }
- }
-
- ret =3D pcie_set_mps(pdev, mps);
- if (ret) {
- pr_err("failed to set mps to %d, keep using current %d\n",
- mps, mps_o);
- priv->mps =3D mps_o;
- return;
- }
-
- pr_debug("set mps to %d (was %d, max %d)\n", mps, mps_o, mps_m);
- priv->mps =3D mps;
-}
-
static int qtnf_is_state(__le32 __iomem *reg, u32 state)
{
u32 s =3D readl(reg);
@@ -423,26 +258,6 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 st=
ate, u32 delay_in_ms)
return 0;
}
=20
-static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
-{
- struct sk_buff **vaddr;
- int len;
-
- len =3D priv->tx_bd_num * sizeof(*priv->tx_skb) +
- priv->rx_bd_num * sizeof(*priv->rx_skb);
- vaddr =3D devm_kzalloc(&priv->pdev->dev, len, GFP_KERNEL);
-
- if (!vaddr)
- return -ENOMEM;
-
- priv->tx_skb =3D vaddr;
-
- vaddr +=3D priv->tx_bd_num;
- priv->rx_skb =3D vaddr;
-
- return 0;
-}
-
static int pearl_alloc_bd_table(struct qtnf_pcie_pearl_state *ps)
{
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
@@ -656,7 +471,7 @@ static int qtnf_pcie_pearl_init_xfer(struct qtnf_pcie_p=
earl_state *ps)
return ret;
}
=20
- ret =3D alloc_skb_array(priv);
+ ret =3D qtnf_pcie_alloc_skb_array(priv);
if (ret) {
pr_err("failed to allocate skb array\n");
return ret;
@@ -750,7 +565,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_s=
tate *ps)
=20
static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
- struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D get_bus_priv(bus);
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
dma_addr_t txbd_paddr, skb_paddr;
struct qtnf_pearl_tx_bd *txbd;
@@ -824,25 +639,10 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, st=
ruct sk_buff *skb)
return NETDEV_TX_OK;
}
=20
-static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
-{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
- int ret;
-
- ret =3D qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
-
- if (ret =3D=3D -ETIMEDOUT) {
- pr_err("EP firmware is dead\n");
- bus->fw_state =3D QTNF_FW_STATE_EP_DEAD;
- }
-
- return ret;
-}
-
static irqreturn_t qtnf_pcie_pearl_interrupt(int irq, void *data)
{
struct qtnf_bus *bus =3D (struct qtnf_bus *)data;
- struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D get_bus_priv(bus);
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
u32 status;
=20
@@ -902,7 +702,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_st=
ate *ps)
static int qtnf_pcie_pearl_rx_poll(struct napi_struct *napi, int budget)
{
struct qtnf_bus *bus =3D container_of(napi, struct qtnf_bus, mux_napi);
- struct qtnf_pcie_pearl_state *ps =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *ps =3D get_bus_priv(bus);
struct qtnf_pcie_bus_priv *priv =3D &ps->base;
struct net_device *ndev =3D NULL;
struct sk_buff *skb =3D NULL;
@@ -1038,26 +838,6 @@ static const struct qtnf_bus_ops qtnf_pcie_pearl_bus_=
ops =3D {
.data_rx_stop =3D qtnf_pcie_data_rx_stop,
};
=20
-static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
-{
- struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
-
- seq_printf(s, "%d\n", priv->mps);
-
- return 0;
-}
-
-static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
-{
- struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
-
- seq_printf(s, "%u\n", priv->msi_enabled);
-
- return 0;
-}
-
static int qtnf_dbg_irq_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
@@ -1114,27 +894,9 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, voi=
d *data)
return 0;
}
=20
-static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
-{
- struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
-
- seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
- priv->shm_ipc_ep_in.tx_packet_count);
- seq_printf(s, "shm_ipc_ep_in.rx_packet_count(%zu)\n",
- priv->shm_ipc_ep_in.rx_packet_count);
- seq_printf(s, "shm_ipc_ep_out.tx_packet_count(%zu)\n",
- priv->shm_ipc_ep_out.tx_timeout_count);
- seq_printf(s, "shm_ipc_ep_out.rx_packet_count(%zu)\n",
- priv->shm_ipc_ep_out.rx_packet_count);
-
- return 0;
-}
-
-static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *ps, uint32_t size=
,
+static int qtnf_ep_fw_send(struct pci_dev *pdev, uint32_t size,
int blk, const u8 *pblk, const u8 *fw)
{
- struct pci_dev *pdev =3D ps->base.pdev;
struct qtnf_bus *bus =3D pci_get_drvdata(pdev);
=20
struct qtnf_pearl_fw_hdr *hdr;
@@ -1197,7 +959,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *ps, cons=
t u8 *fw, u32 fw_size)
return -ETIMEDOUT;
}
=20
- len =3D qtnf_ep_fw_send(ps, fw_size, blk, pblk, fw);
+ len =3D qtnf_ep_fw_send(ps->base.pdev, fw_size, blk, pblk, fw);
if (len <=3D 0)
continue;
=20
@@ -1255,6 +1017,7 @@ static void qtnf_pearl_fw_work_handler(struct work_st=
ruct *work)
int ret;
u32 state =3D QTN_RC_FW_LOADRDY | QTN_RC_FW_QLINK;
const char *fwname =3D QTN_PCI_PEARL_FW_NAME;
+ bool fw_boot_success =3D false;
=20
if (flashboot) {
state |=3D QTN_RC_FW_FLASHBOOT;
@@ -1262,7 +1025,7 @@ static void qtnf_pearl_fw_work_handler(struct work_st=
ruct *work)
ret =3D request_firmware(&fw, fwname, &pdev->dev);
if (ret < 0) {
pr_err("failed to get firmware %s\n", fwname);
- goto fw_load_fail;
+ goto fw_load_exit;
}
}
=20
@@ -1275,13 +1038,14 @@ static void qtnf_pearl_fw_work_handler(struct work_=
struct *work)
if (!flashboot)
release_firmware(fw);
=20
- goto fw_load_fail;
+ goto fw_load_exit;
}
=20
qtnf_clear_state(&ps->bda->bda_ep_state, QTN_EP_FW_LOADRDY);
=20
if (flashboot) {
pr_info("booting firmware from flash\n");
+
} else {
pr_info("starting firmware upload: %s\n", fwname);
=20
@@ -1289,56 +1053,33 @@ static void qtnf_pearl_fw_work_handler(struct work_=
struct *work)
release_firmware(fw);
if (ret) {
pr_err("firmware upload error\n");
- goto fw_load_fail;
+ goto fw_load_exit;
}
}
=20
if (qtnf_poll_state(&ps->bda->bda_ep_state, QTN_EP_FW_DONE,
QTN_FW_DL_TIMEOUT_MS)) {
pr_err("firmware bringup timed out\n");
- goto fw_load_fail;
+ goto fw_load_exit;
}
=20
- bus->fw_state =3D QTNF_FW_STATE_FW_DNLD_DONE;
pr_info("firmware is up and running\n");
=20
if (qtnf_poll_state(&ps->bda->bda_ep_state,
QTN_EP_FW_QLINK_DONE, QTN_FW_QLINK_TIMEOUT_MS)) {
pr_err("firmware runtime failure\n");
- goto fw_load_fail;
- }
-
- ret =3D qtnf_core_attach(bus);
- if (ret) {
- pr_err("failed to attach core\n");
- goto fw_load_fail;
+ goto fw_load_exit;
}
=20
- qtnf_debugfs_init(bus, DRV_NAME);
- qtnf_debugfs_add_entry(bus, "mps", qtnf_dbg_mps_show);
- qtnf_debugfs_add_entry(bus, "msi_enabled", qtnf_dbg_msi_show);
- qtnf_debugfs_add_entry(bus, "hdp_stats", qtnf_dbg_hdp_stats);
- qtnf_debugfs_add_entry(bus, "irq_stats", qtnf_dbg_irq_stats);
- qtnf_debugfs_add_entry(bus, "shm_stats", qtnf_dbg_shm_stats);
-
- goto fw_load_exit;
-
-fw_load_fail:
- bus->fw_state =3D QTNF_FW_STATE_DETACHED;
+ fw_boot_success =3D true;
=20
fw_load_exit:
- complete(&bus->firmware_init_complete);
- put_device(&pdev->dev);
-}
+ qtnf_pcie_fw_boot_done(bus, fw_boot_success, DRV_NAME);
=20
-static void qtnf_bringup_fw_async(struct qtnf_bus *bus)
-{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
- struct pci_dev *pdev =3D priv->pdev;
-
- get_device(&pdev->dev);
- INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler);
- schedule_work(&bus->fw_work);
+ if (fw_boot_success) {
+ qtnf_debugfs_add_entry(bus, "hdp_stats", qtnf_dbg_hdp_stats);
+ qtnf_debugfs_add_entry(bus, "irq_stats", qtnf_dbg_irq_stats);
+ }
}
=20
static void qtnf_pearl_reclaim_tasklet_fn(unsigned long data)
@@ -1351,100 +1092,47 @@ static void qtnf_pearl_reclaim_tasklet_fn(unsigned=
long data)
=20
static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, const struct pci_de=
vice_id *id)
{
+ struct qtnf_shm_ipc_int ipc_int;
struct qtnf_pcie_pearl_state *ps;
struct qtnf_bus *bus;
int ret;
+ u64 dma_mask;
=20
- bus =3D devm_kzalloc(&pdev->dev,
- sizeof(*bus) + sizeof(*ps), GFP_KERNEL);
- if (!bus)
- return -ENOMEM;
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+ dma_mask =3D DMA_BIT_MASK(64);
+#else
+ dma_mask =3D DMA_BIT_MASK(32);
+#endif
=20
- ps =3D get_bus_priv(bus);
+ ret =3D qtnf_pcie_probe(pdev, sizeof(*ps), &qtnf_pcie_pearl_bus_ops,
+ dma_mask, use_msi);
+ if (ret)
+ return ret;
=20
- pci_set_drvdata(pdev, bus);
- bus->bus_ops =3D &qtnf_pcie_pearl_bus_ops;
- bus->dev =3D &pdev->dev;
- bus->fw_state =3D QTNF_FW_STATE_RESET;
- ps->base.pdev =3D pdev;
+ bus =3D pci_get_drvdata(pdev);
+ ps =3D get_bus_priv(bus);
=20
- init_completion(&bus->firmware_init_complete);
- mutex_init(&bus->bus_lock);
- spin_lock_init(&ps->base.tx_lock);
spin_lock_init(&ps->irq_lock);
- spin_lock_init(&ps->base.tx_reclaim_lock);
-
- /* init stats */
- ps->base.tx_full_count =3D 0;
- ps->base.tx_done_count =3D 0;
- ps->base.pcie_irq_count =3D 0;
- ps->pcie_irq_rx_count =3D 0;
- ps->pcie_irq_tx_count =3D 0;
- ps->pcie_irq_uf_count =3D 0;
- ps->base.tx_reclaim_done =3D 0;
- ps->base.tx_reclaim_req =3D 0;
=20
tasklet_init(&ps->base.reclaim_tq, qtnf_pearl_reclaim_tasklet_fn,
(unsigned long)ps);
-
- init_dummy_netdev(&bus->mux_dev);
netif_napi_add(&bus->mux_dev, &bus->mux_napi,
qtnf_pcie_pearl_rx_poll, 10);
+ INIT_WORK(&bus->fw_work, qtnf_pearl_fw_work_handler);
=20
- ps->base.workqueue =3D create_singlethread_workqueue("QTNF_PEARL_PCIE");
- if (!ps->base.workqueue) {
- pr_err("failed to alloc bus workqueue\n");
- ret =3D -ENODEV;
- goto err_init;
- }
-
- if (!pci_is_pcie(pdev)) {
- pr_err("device %s is not PCI Express\n", pci_name(pdev));
- ret =3D -EIO;
- goto err_base;
- }
-
- qtnf_tune_pcie_mps(&ps->base);
-
- ret =3D pcim_enable_device(pdev);
- if (ret) {
- pr_err("failed to init PCI device %x\n", pdev->device);
- goto err_base;
- } else {
- pr_debug("successful init of PCI device %x\n", pdev->device);
- }
-
-#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
- ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
-#else
- ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
-#endif
- if (ret) {
- pr_err("PCIE DMA coherent mask init failed\n");
- goto err_base;
- }
-
- pci_set_master(pdev);
- qtnf_pcie_init_irq(&ps->base);
-
- ret =3D qtnf_pcie_init_memory(ps);
- if (ret < 0) {
- pr_err("PCIE memory init failed\n");
- goto err_base;
- }
-
- pci_save_state(pdev);
+ ps->pcie_reg_base =3D ps->base.dmareg_bar;
+ ps->bda =3D ps->base.epmem_bar;
+ writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled);
=20
- ret =3D qtnf_pcie_init_shm_ipc(ps);
- if (ret < 0) {
- pr_err("PCIE SHM IPC init failed\n");
- goto err_base;
- }
+ ipc_int.fn =3D qtnf_pcie_pearl_ipc_gen_ep_int;
+ ipc_int.arg =3D ps;
+ qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1,
+ &ps->bda->bda_shm_reg2, &ipc_int);
=20
ret =3D qtnf_pcie_pearl_init_xfer(ps);
if (ret) {
pr_err("PCIE xfer init failed\n");
- goto err_ipc;
+ goto error;
}
=20
/* init default irq settings */
@@ -1461,24 +1149,14 @@ static int qtnf_pcie_pearl_probe(struct pci_dev *pd=
ev, const struct pci_device_i
goto err_xfer;
}
=20
- qtnf_bringup_fw_async(bus);
+ qtnf_pcie_bringup_fw_async(bus);
=20
return 0;
=20
err_xfer:
qtnf_pearl_free_xfer_buffers(ps);
-
-err_ipc:
- qtnf_pcie_free_shm_ipc(&ps->base);
-
-err_base:
- flush_workqueue(ps->base.workqueue);
- destroy_workqueue(ps->base.workqueue);
-
-err_init:
- tasklet_kill(&ps->base.reclaim_tq);
- netif_napi_del(&bus->mux_napi);
- pci_set_drvdata(pdev, NULL);
+error:
+ qtnf_pcie_remove(bus, &ps->base);
=20
return ret;
}
@@ -1492,22 +1170,11 @@ static void qtnf_pcie_pearl_remove(struct pci_dev *=
pdev)
if (!bus)
return;
=20
- wait_for_completion(&bus->firmware_init_complete);
-
- if (bus->fw_state =3D=3D QTNF_FW_STATE_ACTIVE ||
- bus->fw_state =3D=3D QTNF_FW_STATE_EP_DEAD)
- qtnf_core_detach(bus);
-
ps =3D get_bus_priv(bus);
- qtnf_pearl_reset_ep(ps);
- netif_napi_del(&bus->mux_napi);
- flush_workqueue(ps->base.workqueue);
- destroy_workqueue(ps->base.workqueue);
- tasklet_kill(&ps->base.reclaim_tq);
=20
+ qtnf_pcie_remove(bus, &ps->base);
+ qtnf_pearl_reset_ep(ps);
qtnf_pearl_free_xfer_buffers(ps);
- qtnf_pcie_free_shm_ipc(&ps->base);
- qtnf_debugfs_remove(bus);
}
=20
#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b=
/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
index b87505d..f21e97e 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
@@ -63,10 +63,6 @@
#define QTN_HOST_ADDR(h, l) ((u32)l)
#endif
=20
-#define QTN_SYSCTL_BAR 0
-#define QTN_SHMEM_BAR 2
-#define QTN_DMA_BAR 3
-
#define QTN_PCIE_BDA_VERSION 0x1002
=20
#define PCIE_BDA_NAMELEN 32
--=20
2.9.5
A few include directives were missing in bus.h resulting in dependency
of include order in other modules. Add missing includes.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/bus.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wir=
eless/quantenna/qtnfmac/bus.h
index 2beca5b..7c4f856 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/bus.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h
@@ -20,6 +20,9 @@
#include <linux/netdevice.h>
#include <linux/workqueue.h>
=20
+#include "trans.h"
+#include "core.h"
+
#define QTNF_MAX_MAC 3
=20
enum qtnf_fw_state {
--=20
2.9.5
Waiting for "completion" to be set in FW load thread can not be used
in case PCIe remove is called before FW load work was scheduled.
Just wait for work completion instead to avoid problems.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/bus.h | 1 -
drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c | 4 +---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/bus.h b/drivers/net/wir=
eless/quantenna/qtnfmac/bus.h
index 7c4f856..528ca7f 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/bus.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/bus.h
@@ -62,7 +62,6 @@ struct qtnf_bus {
struct qtnf_hw_info hw_info;
struct napi_struct mux_napi;
struct net_device mux_dev;
- struct completion firmware_init_complete;
struct workqueue_struct *workqueue;
struct work_struct fw_work;
struct work_struct event_work;
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c b/drivers/n=
et/wireless/quantenna/qtnfmac/pcie/pcie.c
index ab42d11..fd2f1a1 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
@@ -143,7 +143,6 @@ void qtnf_pcie_fw_boot_done(struct qtnf_bus *bus, bool =
boot_success,
bus->fw_state =3D QTNF_FW_STATE_DETACHED;
}
=20
- complete(&bus->firmware_init_complete);
put_device(&pdev->dev);
}
=20
@@ -317,7 +316,6 @@ int qtnf_pcie_probe(struct pci_dev *pdev, size_t priv_s=
ize,
pcie_priv->pdev =3D pdev;
pcie_priv->tx_stopped =3D 0;
=20
- init_completion(&bus->firmware_init_complete);
mutex_init(&bus->bus_lock);
spin_lock_init(&pcie_priv->tx_lock);
spin_lock_init(&pcie_priv->tx_reclaim_lock);
@@ -389,7 +387,7 @@ static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus=
_priv *priv)
=20
void qtnf_pcie_remove(struct qtnf_bus *bus, struct qtnf_pcie_bus_priv *pri=
v)
{
- wait_for_completion(&bus->firmware_init_complete);
+ cancel_work_sync(&bus->fw_work);
=20
if (bus->fw_state =3D=3D QTNF_FW_STATE_ACTIVE ||
bus->fw_state =3D=3D QTNF_FW_STATE_EP_DEAD)
--=20
2.9.5
In preparation to extract common pcie driver state into a separate
structure, rename Pearl-specific state to qtnf_pcie_pearl_state and move
it directly to pearl-specific PCIe source file.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 158 +++++++++++++++--=
----
.../quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h | 91 ------------
2 files changed, 111 insertions(+), 138 deletions(-)
delete mode 100644 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_=
bus_priv.h
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 269a6e4..ab06eca 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -28,10 +28,12 @@
#include <linux/circ_buf.h>
#include <linux/log2.h>
=20
+#include "pearl_pcie_regs.h"
+#include "pearl_pcie_ipc.h"
#include "qtn_hw_ids.h"
-#include "pearl_pcie_bus_priv.h"
#include "core.h"
#include "bus.h"
+#include "shm_ipc.h"
#include "debug.h"
=20
static bool use_msi =3D true;
@@ -52,6 +54,68 @@ MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary f=
ile on FS");
=20
#define DRV_NAME "qtnfmac_pearl_pcie"
=20
+struct qtnf_pcie_pearl_state {
+ struct pci_dev *pdev;
+
+ /* lock for irq configuration changes */
+ spinlock_t irq_lock;
+
+ /* lock for tx reclaim operations */
+ spinlock_t tx_reclaim_lock;
+ /* lock for tx0 operations */
+ spinlock_t tx0_lock;
+ u8 msi_enabled;
+ u8 tx_stopped;
+ int mps;
+
+ struct workqueue_struct *workqueue;
+ struct tasklet_struct reclaim_tq;
+
+ void __iomem *sysctl_bar;
+ void __iomem *epmem_bar;
+ void __iomem *dmareg_bar;
+
+ struct qtnf_shm_ipc shm_ipc_ep_in;
+ struct qtnf_shm_ipc shm_ipc_ep_out;
+
+ struct qtnf_pcie_bda __iomem *bda;
+ void __iomem *pcie_reg_base;
+
+ u16 tx_bd_num;
+ u16 rx_bd_num;
+
+ struct sk_buff **tx_skb;
+ struct sk_buff **rx_skb;
+
+ struct qtnf_tx_bd *tx_bd_vbase;
+ dma_addr_t tx_bd_pbase;
+
+ struct qtnf_rx_bd *rx_bd_vbase;
+ dma_addr_t rx_bd_pbase;
+
+ dma_addr_t bd_table_paddr;
+ void *bd_table_vaddr;
+ u32 bd_table_len;
+
+ u32 rx_bd_w_index;
+ u32 rx_bd_r_index;
+
+ u32 tx_bd_w_index;
+ u32 tx_bd_r_index;
+
+ u32 pcie_irq_mask;
+
+ /* diagnostics stats */
+ u32 pcie_irq_count;
+ u32 pcie_irq_rx_count;
+ u32 pcie_irq_tx_count;
+ u32 pcie_irq_uf_count;
+ u32 tx_full_count;
+ u32 tx_done_count;
+ u32 tx_reclaim_done;
+ u32 tx_reclaim_req;
+};
+
static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
{
writel(val, basereg);
@@ -60,7 +124,7 @@ static inline void qtnf_non_posted_write(u32 val, void _=
_iomem *basereg)
readl(basereg);
}
=20
-static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_pearl_state *priv)
{
unsigned long flags;
=20
@@ -69,7 +133,7 @@ static inline void qtnf_init_hdp_irqs(struct qtnf_pcie_b=
us_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie_pearl_state *priv=
)
{
unsigned long flags;
=20
@@ -78,7 +142,7 @@ static inline void qtnf_enable_hdp_irqs(struct qtnf_pcie=
_bus_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_disable_hdp_irqs(struct qtnf_pcie_pearl_state *pri=
v)
{
unsigned long flags;
=20
@@ -87,7 +151,7 @@ static inline void qtnf_disable_hdp_irqs(struct qtnf_pci=
e_bus_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_pearl_state *priv)
{
unsigned long flags;
=20
@@ -97,7 +161,7 @@ static inline void qtnf_en_rxdone_irq(struct qtnf_pcie_b=
us_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie_pearl_state *priv)
{
unsigned long flags;
=20
@@ -107,7 +171,7 @@ static inline void qtnf_dis_rxdone_irq(struct qtnf_pcie=
_bus_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_en_txdone_irq(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_en_txdone_irq(struct qtnf_pcie_pearl_state *priv)
{
unsigned long flags;
=20
@@ -117,7 +181,7 @@ static inline void qtnf_en_txdone_irq(struct qtnf_pcie_=
bus_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_bus_priv *priv)
+static inline void qtnf_dis_txdone_irq(struct qtnf_pcie_pearl_state *priv)
{
unsigned long flags;
=20
@@ -127,7 +191,7 @@ static inline void qtnf_dis_txdone_irq(struct qtnf_pcie=
_bus_priv *priv)
spin_unlock_irqrestore(&priv->irq_lock, flags);
}
=20
-static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_pcie_init_irq(struct qtnf_pcie_pearl_state *priv)
{
struct pci_dev *pdev =3D priv->pdev;
=20
@@ -150,7 +214,7 @@ static void qtnf_pcie_init_irq(struct qtnf_pcie_bus_pri=
v *priv)
}
}
=20
-static void qtnf_deassert_intx(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_deassert_intx(struct qtnf_pcie_pearl_state *priv)
{
void __iomem *reg =3D priv->sysctl_bar + PEARL_PCIE_CFG0_OFFSET;
u32 cfg;
@@ -160,7 +224,7 @@ static void qtnf_deassert_intx(struct qtnf_pcie_bus_pri=
v *priv)
qtnf_non_posted_write(cfg, reg);
}
=20
-static void qtnf_reset_card(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_reset_card(struct qtnf_pcie_pearl_state *priv)
{
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_EP_RESET);
void __iomem *reg =3D priv->sysctl_bar +
@@ -173,7 +237,7 @@ static void qtnf_reset_card(struct qtnf_pcie_bus_priv *=
priv)
=20
static void qtnf_ipc_gen_ep_int(void *arg)
{
- const struct qtnf_pcie_bus_priv *priv =3D arg;
+ const struct qtnf_pcie_pearl_state *priv =3D arg;
const u32 data =3D QTN_PEARL_IPC_IRQ_WORD(QTN_PEARL_LHOST_IPC_IRQ);
void __iomem *reg =3D priv->sysctl_bar +
QTN_PEARL_SYSCTL_LHOST_IRQ_OFFSET;
@@ -181,7 +245,7 @@ static void qtnf_ipc_gen_ep_int(void *arg)
qtnf_non_posted_write(data, reg);
}
=20
-static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_priv *priv, u8 inde=
x)
+static void __iomem *qtnf_map_bar(struct qtnf_pcie_pearl_state *priv, u8 i=
ndex)
{
void __iomem *vaddr;
dma_addr_t busaddr;
@@ -206,7 +270,7 @@ static void __iomem *qtnf_map_bar(struct qtnf_pcie_bus_=
priv *priv, u8 index)
=20
static void qtnf_pcie_control_rx_callback(void *arg, const u8 *buf, size_t=
len)
{
- struct qtnf_pcie_bus_priv *priv =3D arg;
+ struct qtnf_pcie_pearl_state *priv =3D arg;
struct qtnf_bus *bus =3D pci_get_drvdata(priv->pdev);
struct sk_buff *skb;
=20
@@ -227,7 +291,7 @@ static void qtnf_pcie_control_rx_callback(void *arg, co=
nst u8 *buf, size_t len)
qtnf_trans_handle_rx_ctl_packet(bus, skb);
}
=20
-static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_pearl_state *priv)
{
struct qtnf_shm_ipc_region __iomem *ipc_tx_reg;
struct qtnf_shm_ipc_region __iomem *ipc_rx_reg;
@@ -248,13 +312,13 @@ static int qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bu=
s_priv *priv)
return 0;
}
=20
-static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_pcie_free_shm_ipc(struct qtnf_pcie_pearl_state *priv)
{
qtnf_shm_ipc_free(&priv->shm_ipc_ep_in);
qtnf_shm_ipc_free(&priv->shm_ipc_ep_out);
}
=20
-static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_pcie_init_memory(struct qtnf_pcie_pearl_state *priv)
{
int ret =3D -ENOMEM;
=20
@@ -283,7 +347,7 @@ static int qtnf_pcie_init_memory(struct qtnf_pcie_bus_p=
riv *priv)
return 0;
}
=20
-static void qtnf_tune_pcie_mps(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_tune_pcie_mps(struct qtnf_pcie_pearl_state *priv)
{
struct pci_dev *pdev =3D priv->pdev;
struct pci_dev *parent;
@@ -355,7 +419,7 @@ static int qtnf_poll_state(__le32 __iomem *reg, u32 sta=
te, u32 delay_in_ms)
return 0;
}
=20
-static int alloc_skb_array(struct qtnf_pcie_bus_priv *priv)
+static int alloc_skb_array(struct qtnf_pcie_pearl_state *priv)
{
struct sk_buff **vaddr;
int len;
@@ -375,7 +439,7 @@ static int alloc_skb_array(struct qtnf_pcie_bus_priv *p=
riv)
return 0;
}
=20
-static int alloc_bd_table(struct qtnf_pcie_bus_priv *priv)
+static int alloc_bd_table(struct qtnf_pcie_pearl_state *priv)
{
dma_addr_t paddr;
void *vaddr;
@@ -426,7 +490,7 @@ static int alloc_bd_table(struct qtnf_pcie_bus_priv *pr=
iv)
return 0;
}
=20
-static int skb2rbd_attach(struct qtnf_pcie_bus_priv *priv, u16 index)
+static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index)
{
struct qtnf_rx_bd *rxbd;
struct sk_buff *skb;
@@ -469,7 +533,7 @@ static int skb2rbd_attach(struct qtnf_pcie_bus_priv *pr=
iv, u16 index)
return 0;
}
=20
-static int alloc_rx_buffers(struct qtnf_pcie_bus_priv *priv)
+static int alloc_rx_buffers(struct qtnf_pcie_pearl_state *priv)
{
u16 i;
int ret =3D 0;
@@ -487,7 +551,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_bus_priv *=
priv)
}
=20
/* all rx/tx activity should have ceased before calling this function */
-static void qtnf_free_xfer_buffers(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv)
{
struct qtnf_tx_bd *txbd;
struct qtnf_rx_bd *rxbd;
@@ -524,7 +588,7 @@ static void qtnf_free_xfer_buffers(struct qtnf_pcie_bus=
_priv *priv)
}
}
=20
-static int qtnf_hhbm_init(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_hhbm_init(struct qtnf_pcie_pearl_state *priv)
{
u32 val;
=20
@@ -542,7 +606,7 @@ static int qtnf_hhbm_init(struct qtnf_pcie_bus_priv *pr=
iv)
return 0;
}
=20
-static int qtnf_pcie_init_xfer(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_state *priv)
{
int ret;
u32 val;
@@ -605,7 +669,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_bus_pri=
v *priv)
return ret;
}
=20
-static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_bus_priv *priv)
+static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv)
{
struct qtnf_tx_bd *txbd;
struct sk_buff *skb;
@@ -656,7 +720,7 @@ static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_=
bus_priv *priv)
spin_unlock_irqrestore(&priv->tx_reclaim_lock, flags);
}
=20
-static int qtnf_tx_queue_ready(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_tx_queue_ready(struct qtnf_pcie_pearl_state *priv)
{
if (!CIRC_SPACE(priv->tx_bd_w_index, priv->tx_bd_r_index,
priv->tx_bd_num)) {
@@ -675,7 +739,7 @@ static int qtnf_tx_queue_ready(struct qtnf_pcie_bus_pri=
v *priv)
=20
static int qtnf_pcie_data_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
dma_addr_t txbd_paddr, skb_paddr;
struct qtnf_tx_bd *txbd;
unsigned long flags;
@@ -750,7 +814,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
=20
static int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
int ret;
=20
ret =3D qtnf_shm_ipc_send(&priv->shm_ipc_ep_in, skb->data, skb->len);
@@ -766,7 +830,7 @@ static int qtnf_pcie_control_tx(struct qtnf_bus *bus, s=
truct sk_buff *skb)
static irqreturn_t qtnf_interrupt(int irq, void *data)
{
struct qtnf_bus *bus =3D (struct qtnf_bus *)data;
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
u32 status;
=20
priv->pcie_irq_count++;
@@ -807,7 +871,7 @@ static irqreturn_t qtnf_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
=20
-static int qtnf_rx_data_ready(struct qtnf_pcie_bus_priv *priv)
+static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv)
{
u16 index =3D priv->rx_bd_r_index;
struct qtnf_rx_bd *rxbd;
@@ -825,7 +889,7 @@ static int qtnf_rx_data_ready(struct qtnf_pcie_bus_priv=
*priv)
static int qtnf_rx_poll(struct napi_struct *napi, int budget)
{
struct qtnf_bus *bus =3D container_of(napi, struct qtnf_bus, mux_napi);
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
struct net_device *ndev =3D NULL;
struct sk_buff *skb =3D NULL;
int processed =3D 0;
@@ -930,14 +994,14 @@ static int qtnf_rx_poll(struct napi_struct *napi, int=
budget)
static void
qtnf_pcie_data_tx_timeout(struct qtnf_bus *bus, struct net_device *ndev)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
=20
tasklet_hi_schedule(&priv->reclaim_tq);
}
=20
static void qtnf_pcie_data_rx_start(struct qtnf_bus *bus)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
=20
qtnf_enable_hdp_irqs(priv);
napi_enable(&bus->mux_napi);
@@ -945,7 +1009,7 @@ static void qtnf_pcie_data_rx_start(struct qtnf_bus *b=
us)
=20
static void qtnf_pcie_data_rx_stop(struct qtnf_bus *bus)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
=20
napi_disable(&bus->mux_napi);
qtnf_disable_hdp_irqs(priv);
@@ -965,7 +1029,7 @@ static const struct qtnf_bus_ops qtnf_pcie_bus_ops =3D=
{
static int qtnf_dbg_mps_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "%d\n", priv->mps);
=20
@@ -975,7 +1039,7 @@ static int qtnf_dbg_mps_show(struct seq_file *s, void =
*data)
static int qtnf_dbg_msi_show(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "%u\n", priv->msi_enabled);
=20
@@ -985,7 +1049,7 @@ static int qtnf_dbg_msi_show(struct seq_file *s, void =
*data)
static int qtnf_dbg_irq_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
u32 reg =3D readl(PCIE_HDP_INT_EN(priv->pcie_reg_base));
u32 status;
=20
@@ -1009,7 +1073,7 @@ static int qtnf_dbg_irq_stats(struct seq_file *s, voi=
d *data)
static int qtnf_dbg_hdp_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "tx_full_count(%u)\n", priv->tx_full_count);
seq_printf(s, "tx_done_count(%u)\n", priv->tx_done_count);
@@ -1040,7 +1104,7 @@ static int qtnf_dbg_hdp_stats(struct seq_file *s, voi=
d *data)
static int qtnf_dbg_shm_stats(struct seq_file *s, void *data)
{
struct qtnf_bus *bus =3D dev_get_drvdata(s->private);
- struct qtnf_pcie_bus_priv *priv =3D get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D get_bus_priv(bus);
=20
seq_printf(s, "shm_ipc_ep_in.tx_packet_count(%zu)\n",
priv->shm_ipc_ep_in.tx_packet_count);
@@ -1054,7 +1118,7 @@ static int qtnf_dbg_shm_stats(struct seq_file *s, voi=
d *data)
return 0;
}
=20
-static int qtnf_ep_fw_send(struct qtnf_pcie_bus_priv *priv, uint32_t size,
+static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_state *priv, uint32_t si=
ze,
int blk, const u8 *pblk, const u8 *fw)
{
struct pci_dev *pdev =3D priv->pdev;
@@ -1103,7 +1167,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_bus_priv =
*priv, uint32_t size,
}
=20
static int
-qtnf_ep_fw_load(struct qtnf_pcie_bus_priv *priv, const u8 *fw, u32 fw_size=
)
+qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_s=
ize)
{
int blk_size =3D QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pcie_fw_hdr);
int blk_count =3D fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0);
@@ -1172,7 +1236,7 @@ qtnf_ep_fw_load(struct qtnf_pcie_bus_priv *priv, cons=
t u8 *fw, u32 fw_size)
static void qtnf_fw_work_handler(struct work_struct *work)
{
struct qtnf_bus *bus =3D container_of(work, struct qtnf_bus, fw_work);
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
struct pci_dev *pdev =3D priv->pdev;
const struct firmware *fw;
int ret;
@@ -1256,7 +1320,7 @@ static void qtnf_fw_work_handler(struct work_struct *=
work)
=20
static void qtnf_bringup_fw_async(struct qtnf_bus *bus)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)get_bus_priv(bus);
+ struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
struct pci_dev *pdev =3D priv->pdev;
=20
get_device(&pdev->dev);
@@ -1266,7 +1330,7 @@ static void qtnf_bringup_fw_async(struct qtnf_bus *bu=
s)
=20
static void qtnf_reclaim_tasklet_fn(unsigned long data)
{
- struct qtnf_pcie_bus_priv *priv =3D (void *)data;
+ struct qtnf_pcie_pearl_state *priv =3D (void *)data;
=20
qtnf_pcie_data_tx_reclaim(priv);
qtnf_en_txdone_irq(priv);
@@ -1274,7 +1338,7 @@ static void qtnf_reclaim_tasklet_fn(unsigned long dat=
a)
=20
static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_i=
d *id)
{
- struct qtnf_pcie_bus_priv *pcie_priv;
+ struct qtnf_pcie_pearl_state *pcie_priv;
struct qtnf_bus *bus;
int ret;
=20
@@ -1407,7 +1471,7 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, cons=
t struct pci_device_id *id)
=20
static void qtnf_pcie_remove(struct pci_dev *pdev)
{
- struct qtnf_pcie_bus_priv *priv;
+ struct qtnf_pcie_pearl_state *priv;
struct qtnf_bus *bus;
=20
bus =3D pci_get_drvdata(pdev);
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_pri=
v.h b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h
deleted file mode 100644
index 986b957..0000000
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2015-2016 Quantenna Communications, Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _QTN_FMAC_PCIE_H_
-#define _QTN_FMAC_PCIE_H_
-
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-
-#include "pearl_pcie_regs.h"
-#include "pearl_pcie_ipc.h"
-#include "shm_ipc.h"
-
-struct bus;
-
-struct qtnf_pcie_bus_priv {
- struct pci_dev *pdev;
-
- /* lock for irq configuration changes */
- spinlock_t irq_lock;
-
- /* lock for tx reclaim operations */
- spinlock_t tx_reclaim_lock;
- /* lock for tx0 operations */
- spinlock_t tx0_lock;
- u8 msi_enabled;
- u8 tx_stopped;
- int mps;
-
- struct workqueue_struct *workqueue;
- struct tasklet_struct reclaim_tq;
-
- void __iomem *sysctl_bar;
- void __iomem *epmem_bar;
- void __iomem *dmareg_bar;
-
- struct qtnf_shm_ipc shm_ipc_ep_in;
- struct qtnf_shm_ipc shm_ipc_ep_out;
-
- struct qtnf_pcie_bda __iomem *bda;
- void __iomem *pcie_reg_base;
-
- u16 tx_bd_num;
- u16 rx_bd_num;
-
- struct sk_buff **tx_skb;
- struct sk_buff **rx_skb;
-
- struct qtnf_tx_bd *tx_bd_vbase;
- dma_addr_t tx_bd_pbase;
-
- struct qtnf_rx_bd *rx_bd_vbase;
- dma_addr_t rx_bd_pbase;
-
- dma_addr_t bd_table_paddr;
- void *bd_table_vaddr;
- u32 bd_table_len;
-
- u32 rx_bd_w_index;
- u32 rx_bd_r_index;
-
- u32 tx_bd_w_index;
- u32 tx_bd_r_index;
-
- u32 pcie_irq_mask;
-
- /* diagnostics stats */
- u32 pcie_irq_count;
- u32 pcie_irq_rx_count;
- u32 pcie_irq_tx_count;
- u32 pcie_irq_uf_count;
- u32 tx_full_count;
- u32 tx_done_count;
- u32 tx_reclaim_done;
- u32 tx_reclaim_req;
-};
-
-#endif /* _QTN_FMAC_PCIE_H_ */
--=20
2.9.5
Make sure that wifi device is of supported variant by checking it's CHIP ID
before completing a probe sequence.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 24 ++++++++++++++++++=
++++
.../net/wireless/quantenna/qtnfmac/qtn_hw_ids.h | 14 +++++++++++++
2 files changed, 38 insertions(+)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 424e367..d7a8d20 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -1090,6 +1090,26 @@ static void qtnf_pearl_reclaim_tasklet_fn(unsigned l=
ong data)
qtnf_en_txdone_irq(ps);
}
=20
+static int qtnf_pearl_check_chip_id(struct qtnf_pcie_pearl_state *ps)
+{
+ unsigned int chipid;
+
+ chipid =3D qtnf_chip_id_get(ps->base.sysctl_bar);
+
+ switch (chipid) {
+ case QTN_CHIP_ID_PEARL:
+ case QTN_CHIP_ID_PEARL_B:
+ case QTN_CHIP_ID_PEARL_C:
+ pr_info("chip ID is 0x%x\n", chipid);
+ break;
+ default:
+ pr_err("incorrect chip ID 0x%x\n", chipid);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static int qtnf_pcie_pearl_probe(struct pci_dev *pdev, const struct pci_de=
vice_id *id)
{
struct qtnf_shm_ipc_int ipc_int;
@@ -1129,6 +1149,10 @@ static int qtnf_pcie_pearl_probe(struct pci_dev *pde=
v, const struct pci_device_i
qtnf_pcie_init_shm_ipc(&ps->base, &ps->bda->bda_shm_reg1,
&ps->bda->bda_shm_reg2, &ipc_int);
=20
+ ret =3D qtnf_pearl_check_chip_id(ps);
+ if (ret)
+ goto error;
+
ret =3D qtnf_pcie_pearl_init_xfer(ps);
if (ret) {
pr_err("PCIE xfer init failed\n");
diff --git a/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h b/drivers/=
net/wireless/quantenna/qtnfmac/qtn_hw_ids.h
index c4ad40d..1fe798a 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/qtn_hw_ids.h
@@ -25,8 +25,22 @@
=20
#define PCIE_DEVICE_ID_QTN_PEARL (0x0008)
=20
+#define QTN_REG_SYS_CTRL_CSR 0x14
+#define QTN_CHIP_ID_MASK 0xF0
+#define QTN_CHIP_ID_TOPAZ 0x40
+#define QTN_CHIP_ID_PEARL 0x50
+#define QTN_CHIP_ID_PEARL_B 0x60
+#define QTN_CHIP_ID_PEARL_C 0x70
+
/* FW names */
=20
#define QTN_PCI_PEARL_FW_NAME "qtn/fmac_qsr10g.img"
=20
+static inline unsigned int qtnf_chip_id_get(const void __iomem *regs_base)
+{
+ u32 board_rev =3D readl(regs_base + QTN_REG_SYS_CTRL_CSR);
+
+ return board_rev & QTN_CHIP_ID_MASK;
+}
+
#endif /* _QTN_HW_IDS_H_ */
--=20
2.9.5
In preparation to extract common PCIe driver state, indicate
PEARL-specific structures by their name and move them to pearl-specific
source file.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
.../wireless/quantenna/qtnfmac/pcie/pearl_pcie.c | 89 +++++++++++++++++-=
----
.../quantenna/qtnfmac/pcie/pearl_pcie_ipc.h | 47 ------------
2 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c b/dri=
vers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index ab06eca..4e9eb46 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -54,6 +54,53 @@ MODULE_PARM_DESC(flashboot, "set to 0 to use FW binary f=
ile on FS");
=20
#define DRV_NAME "qtnfmac_pearl_pcie"
=20
+struct qtnf_pearl_bda {
+ __le16 bda_len;
+ __le16 bda_version;
+ __le32 bda_pci_endian;
+ __le32 bda_ep_state;
+ __le32 bda_rc_state;
+ __le32 bda_dma_mask;
+ __le32 bda_msi_addr;
+ __le32 bda_flashsz;
+ u8 bda_boardname[PCIE_BDA_NAMELEN];
+ __le32 bda_rc_msi_enabled;
+ u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE];
+ __le32 bda_dsbw_start_index;
+ __le32 bda_dsbw_end_index;
+ __le32 bda_dsbw_total_bytes;
+ __le32 bda_rc_tx_bd_base;
+ __le32 bda_rc_tx_bd_num;
+ u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH];
+ struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
+ struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */
+} __packed;
+
+struct qtnf_pearl_tx_bd {
+ __le32 addr;
+ __le32 addr_h;
+ __le32 info;
+ __le32 info_h;
+} __packed;
+
+struct qtnf_pearl_rx_bd {
+ __le32 addr;
+ __le32 addr_h;
+ __le32 info;
+ __le32 info_h;
+ __le32 next_ptr;
+ __le32 next_ptr_h;
+} __packed;
+
+struct qtnf_pearl_fw_hdr {
+ u8 boardflg[8];
+ __le32 fwsize;
+ __le32 seqnum;
+ __le32 type;
+ __le32 pktlen;
+ __le32 crc;
+} __packed;
+
struct qtnf_pcie_pearl_state {
struct pci_dev *pdev;
=20
@@ -78,7 +125,7 @@ struct qtnf_pcie_pearl_state {
struct qtnf_shm_ipc shm_ipc_ep_in;
struct qtnf_shm_ipc shm_ipc_ep_out;
=20
- struct qtnf_pcie_bda __iomem *bda;
+ struct qtnf_pearl_bda __iomem *bda;
void __iomem *pcie_reg_base;
=20
u16 tx_bd_num;
@@ -87,10 +134,10 @@ struct qtnf_pcie_pearl_state {
struct sk_buff **tx_skb;
struct sk_buff **rx_skb;
=20
- struct qtnf_tx_bd *tx_bd_vbase;
+ struct qtnf_pearl_tx_bd *tx_bd_vbase;
dma_addr_t tx_bd_pbase;
=20
- struct qtnf_rx_bd *rx_bd_vbase;
+ struct qtnf_pearl_rx_bd *rx_bd_vbase;
dma_addr_t rx_bd_pbase;
=20
dma_addr_t bd_table_paddr;
@@ -445,8 +492,8 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state =
*priv)
void *vaddr;
int len;
=20
- len =3D priv->tx_bd_num * sizeof(struct qtnf_tx_bd) +
- priv->rx_bd_num * sizeof(struct qtnf_rx_bd);
+ len =3D priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd) +
+ priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd);
=20
vaddr =3D dmam_alloc_coherent(&priv->pdev->dev, len, &paddr, GFP_KERNEL);
if (!vaddr)
@@ -470,8 +517,8 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state =
*priv)
=20
/* rx bd */
=20
- vaddr =3D ((struct qtnf_tx_bd *)vaddr) + priv->tx_bd_num;
- paddr +=3D priv->tx_bd_num * sizeof(struct qtnf_tx_bd);
+ vaddr =3D ((struct qtnf_pearl_tx_bd *)vaddr) + priv->tx_bd_num;
+ paddr +=3D priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd);
=20
priv->rx_bd_vbase =3D vaddr;
priv->rx_bd_pbase =3D paddr;
@@ -482,7 +529,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state =
*priv)
#endif
writel(QTN_HOST_LO32(paddr),
PCIE_HDP_TX_HOST_Q_BASE_L(priv->pcie_reg_base));
- writel(priv->rx_bd_num | (sizeof(struct qtnf_rx_bd)) << 16,
+ writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16,
PCIE_HDP_TX_HOST_Q_SZ_CTRL(priv->pcie_reg_base));
=20
pr_debug("RX descriptor table: vaddr=3D0x%p paddr=3D%pad\n", vaddr, &padd=
r);
@@ -492,7 +539,7 @@ static int alloc_bd_table(struct qtnf_pcie_pearl_state =
*priv)
=20
static int skb2rbd_attach(struct qtnf_pcie_pearl_state *priv, u16 index)
{
- struct qtnf_rx_bd *rxbd;
+ struct qtnf_pearl_rx_bd *rxbd;
struct sk_buff *skb;
dma_addr_t paddr;
=20
@@ -539,7 +586,7 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_stat=
e *priv)
int ret =3D 0;
=20
memset(priv->rx_bd_vbase, 0x0,
- priv->rx_bd_num * sizeof(struct qtnf_rx_bd));
+ priv->rx_bd_num * sizeof(struct qtnf_pearl_rx_bd));
=20
for (i =3D 0; i < priv->rx_bd_num; i++) {
ret =3D skb2rbd_attach(priv, i);
@@ -553,8 +600,8 @@ static int alloc_rx_buffers(struct qtnf_pcie_pearl_stat=
e *priv)
/* all rx/tx activity should have ceased before calling this function */
static void qtnf_free_xfer_buffers(struct qtnf_pcie_pearl_state *priv)
{
- struct qtnf_tx_bd *txbd;
- struct qtnf_rx_bd *rxbd;
+ struct qtnf_pearl_tx_bd *txbd;
+ struct qtnf_pearl_rx_bd *rxbd;
struct sk_buff *skb;
dma_addr_t paddr;
int i;
@@ -622,7 +669,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *priv)
return -EINVAL;
}
=20
- val =3D priv->tx_bd_num * sizeof(struct qtnf_tx_bd);
+ val =3D priv->tx_bd_num * sizeof(struct qtnf_pearl_tx_bd);
if (val > PCIE_HHBM_MAX_SIZE) {
pr_err("tx_bd_size_param %u is too large\n",
priv->tx_bd_num);
@@ -671,7 +718,7 @@ static int qtnf_pcie_init_xfer(struct qtnf_pcie_pearl_s=
tate *priv)
=20
static void qtnf_pcie_data_tx_reclaim(struct qtnf_pcie_pearl_state *priv)
{
- struct qtnf_tx_bd *txbd;
+ struct qtnf_pearl_tx_bd *txbd;
struct sk_buff *skb;
unsigned long flags;
dma_addr_t paddr;
@@ -741,7 +788,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
{
struct qtnf_pcie_pearl_state *priv =3D (void *)get_bus_priv(bus);
dma_addr_t txbd_paddr, skb_paddr;
- struct qtnf_tx_bd *txbd;
+ struct qtnf_pearl_tx_bd *txbd;
unsigned long flags;
int len, i;
u32 info;
@@ -782,7 +829,7 @@ static int qtnf_pcie_data_tx(struct qtnf_bus *bus, stru=
ct sk_buff *skb)
dma_wmb();
=20
/* write new TX descriptor to PCIE_RX_FIFO on EP */
- txbd_paddr =3D priv->tx_bd_pbase + i * sizeof(struct qtnf_tx_bd);
+ txbd_paddr =3D priv->tx_bd_pbase + i * sizeof(struct qtnf_pearl_tx_bd);
=20
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
writel(QTN_HOST_HI32(txbd_paddr),
@@ -874,7 +921,7 @@ static irqreturn_t qtnf_interrupt(int irq, void *data)
static int qtnf_rx_data_ready(struct qtnf_pcie_pearl_state *priv)
{
u16 index =3D priv->rx_bd_r_index;
- struct qtnf_rx_bd *rxbd;
+ struct qtnf_pearl_rx_bd *rxbd;
u32 descw;
=20
rxbd =3D &priv->rx_bd_vbase[index];
@@ -893,7 +940,7 @@ static int qtnf_rx_poll(struct napi_struct *napi, int b=
udget)
struct net_device *ndev =3D NULL;
struct sk_buff *skb =3D NULL;
int processed =3D 0;
- struct qtnf_rx_bd *rxbd;
+ struct qtnf_pearl_rx_bd *rxbd;
dma_addr_t skb_paddr;
int consume;
u32 descw;
@@ -1124,7 +1171,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_sta=
te *priv, uint32_t size,
struct pci_dev *pdev =3D priv->pdev;
struct qtnf_bus *bus =3D pci_get_drvdata(pdev);
=20
- struct qtnf_pcie_fw_hdr *hdr;
+ struct qtnf_pearl_fw_hdr *hdr;
u8 *pdata;
=20
int hds =3D sizeof(*hdr);
@@ -1139,7 +1186,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_sta=
te *priv, uint32_t size,
skb->len =3D QTN_PCIE_FW_BUFSZ;
skb->dev =3D NULL;
=20
- hdr =3D (struct qtnf_pcie_fw_hdr *)skb->data;
+ hdr =3D (struct qtnf_pearl_fw_hdr *)skb->data;
memcpy(hdr->boardflg, QTN_PCIE_BOARDFLG, strlen(QTN_PCIE_BOARDFLG));
hdr->fwsize =3D cpu_to_le32(size);
hdr->seqnum =3D cpu_to_le32(blk);
@@ -1169,7 +1216,7 @@ static int qtnf_ep_fw_send(struct qtnf_pcie_pearl_sta=
te *priv, uint32_t size,
static int
qtnf_ep_fw_load(struct qtnf_pcie_pearl_state *priv, const u8 *fw, u32 fw_s=
ize)
{
- int blk_size =3D QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pcie_fw_hdr);
+ int blk_size =3D QTN_PCIE_FW_BUFSZ - sizeof(struct qtnf_pearl_fw_hdr);
int blk_count =3D fw_size / blk_size + ((fw_size % blk_size) ? 1 : 0);
const u8 *pblk =3D fw;
int threshold =3D 0;
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h b=
/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
index 00bb21a..af528b8 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
@@ -101,44 +101,6 @@ enum qtnf_pcie_bda_ipc_flags {
QTN_PCIE_IPC_FLAG_SHM_PIO =3D BIT(1),
};
=20
-struct qtnf_pcie_bda {
- __le16 bda_len;
- __le16 bda_version;
- __le32 bda_pci_endian;
- __le32 bda_ep_state;
- __le32 bda_rc_state;
- __le32 bda_dma_mask;
- __le32 bda_msi_addr;
- __le32 bda_flashsz;
- u8 bda_boardname[PCIE_BDA_NAMELEN];
- __le32 bda_rc_msi_enabled;
- u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE];
- __le32 bda_dsbw_start_index;
- __le32 bda_dsbw_end_index;
- __le32 bda_dsbw_total_bytes;
- __le32 bda_rc_tx_bd_base;
- __le32 bda_rc_tx_bd_num;
- u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH];
- struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */
- struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */
-} __packed;
-
-struct qtnf_tx_bd {
- __le32 addr;
- __le32 addr_h;
- __le32 info;
- __le32 info_h;
-} __packed;
-
-struct qtnf_rx_bd {
- __le32 addr;
- __le32 addr_h;
- __le32 info;
- __le32 info_h;
- __le32 next_ptr;
- __le32 next_ptr_h;
-} __packed;
-
enum qtnf_fw_loadtype {
QTN_FW_DBEGIN,
QTN_FW_DSUB,
@@ -146,13 +108,4 @@ enum qtnf_fw_loadtype {
QTN_FW_CTRL
};
=20
-struct qtnf_pcie_fw_hdr {
- u8 boardflg[8];
- __le32 fwsize;
- __le32 seqnum;
- __le32 type;
- __le32 pktlen;
- __le32 crc;
-} __packed;
-
#endif /* _QTN_FMAC_PCIE_IPC_H_ */
--=20
2.9.5
Igor Mitsyanko SO <[email protected]> writes:
> Firmware name is only needed at probe stage, no point in keeping it in
> driver state structure.
>
> Signed-off-by: Igor Mitsyanko <[email protected]>
This is just cosmetics, but what's that "SO" in the From field? Do note
that if I apply these patches as is that will be stored also to git.
--
Kalle Valo
On 09/24/2018 12:34 AM, Kalle Valo wrote:
>
>
> Igor Mitsyanko SO <[email protected]> writes:
>
>> Firmware name is only needed at probe stage, no point in keeping it in
>> driver state structure.
>>
>> Signed-off-by: Igor Mitsyanko <[email protected]>
>
> This is just cosmetics, but what's that "SO" in the From field? Do note
> that if I apply these patches as is that will be stored also to git.
Looks like something new from my mail system.. Will get rid of that and
resend the series. Thanks!
In preparation to extract common qtnfmac PCIe driver sources into a
separate file, move existing Pearl-specific pcie driver sources to pcie/
directory.
Signed-off-by: Igor Mitsyanko <[email protected]>
---
drivers/net/wireless/quantenna/qtnfmac/Makefile | 2 =
+-
.../wireless/quantenna/qtnfmac/{pearl/pcie.c =3D> pcie/pearl_pcie.c} | =
2 +-
.../qtnfmac/{pearl/pcie_bus_priv.h =3D> pcie/pearl_pcie_bus_priv.h} | =
4 ++--
.../quantenna/qtnfmac/{pearl/pcie_ipc.h =3D> pcie/pearl_pcie_ipc.h} | =
0
.../qtnfmac/{pearl/pcie_regs_pearl.h =3D> pcie/pearl_pcie_regs.h} | =
0
5 files changed, 4 insertions(+), 4 deletions(-)
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie.c =3D> pcie/pear=
l_pcie.c} (99%)
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_bus_priv.h =3D> =
pcie/pearl_pcie_bus_priv.h} (97%)
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_ipc.h =3D> pcie/=
pearl_pcie_ipc.h} (100%)
rename drivers/net/wireless/quantenna/qtnfmac/{pearl/pcie_regs_pearl.h =3D=
> pcie/pearl_pcie_regs.h} (100%)
diff --git a/drivers/net/wireless/quantenna/qtnfmac/Makefile b/drivers/net/=
wireless/quantenna/qtnfmac/Makefile
index 97f760a..9eeddea 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/Makefile
+++ b/drivers/net/wireless/quantenna/qtnfmac/Makefile
@@ -23,6 +23,6 @@ obj-$(CONFIG_QTNFMAC_PEARL_PCIE) +=3D qtnfmac_pearl_pcie.=
o
=20
qtnfmac_pearl_pcie-objs +=3D \
shm_ipc.o \
- pearl/pcie.o
+ pcie/pearl_pcie.o
=20
qtnfmac_pearl_pcie-$(CONFIG_DEBUG_FS) +=3D debug.o
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c b/drivers/=
net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
similarity index 99%
rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
index 97cc7f2..269a6e4 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
@@ -29,7 +29,7 @@
#include <linux/log2.h>
=20
#include "qtn_hw_ids.h"
-#include "pcie_bus_priv.h"
+#include "pearl_pcie_bus_priv.h"
#include "core.h"
#include "bus.h"
#include "debug.h"
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h b=
/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h
similarity index 97%
rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h
rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h
index 397875a..986b957 100644
--- a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h
+++ b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_bus_priv.h
@@ -20,8 +20,8 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
=20
-#include "pcie_regs_pearl.h"
-#include "pcie_ipc.h"
+#include "pearl_pcie_regs.h"
+#include "pearl_pcie_ipc.h"
#include "shm_ipc.h"
=20
struct bus;
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_ipc.h b/driv=
ers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
similarity index 100%
rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_ipc.h
rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_ipc.h
diff --git a/drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_regs_pearl.h=
b/drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h
similarity index 100%
rename from drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_regs_pearl.h
rename to drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie_regs.h
--=20
2.9.5