This patch restores the old behavior that read
the chip_id on the QCA988x before resetting the
chip. This needs to be done in this order since
the unsupported QCA988x AR1A chips fall off the
bus when resetted. Otherwise the next MMIO Op
after the reset causes a BUS ERROR and panic.
Cc: [email protected]
Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
Signed-off-by: Christian Lamparter <[email protected]>
---
drivers/net/wireless/ath/ath10k/pci.c | 36 +++++++++++++++++++--------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index a0b4d265c6eb..347bb92e4130 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -3490,7 +3490,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
struct ath10k_pci *ar_pci;
enum ath10k_hw_rev hw_rev;
struct ath10k_bus_params bus_params = {};
- bool pci_ps;
+ bool pci_ps, is_qca988x = false;
int (*pci_soft_reset)(struct ath10k *ar);
int (*pci_hard_reset)(struct ath10k *ar);
u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
@@ -3500,6 +3500,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
case QCA988X_2_0_DEVICE_ID:
hw_rev = ATH10K_HW_QCA988X;
pci_ps = false;
+ is_qca988x = true;
pci_soft_reset = ath10k_pci_warm_reset;
pci_hard_reset = ath10k_pci_qca988x_chip_reset;
targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
@@ -3619,25 +3620,34 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
goto err_deinit_irq;
}
+ bus_params.dev_type = ATH10K_DEV_TYPE_LL;
+ bus_params.link_can_suspend = true;
+ /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that
+ * fall off the bus during chip_reset. These chips have the same pci
+ * device id as the QCA9880 BR4A or 2R4E. So that's why the check.
+ */
+ if (is_qca988x) {
+ bus_params.chip_id =
+ ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
+ if (bus_params.chip_id != 0xffffffff) {
+ if (!ath10k_pci_chip_is_supported(pdev->device,
+ bus_params.chip_id))
+ goto err_unsupported;
+ }
+ }
+
ret = ath10k_pci_chip_reset(ar);
if (ret) {
ath10k_err(ar, "failed to reset chip: %d\n", ret);
goto err_free_irq;
}
- bus_params.dev_type = ATH10K_DEV_TYPE_LL;
- bus_params.link_can_suspend = true;
bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
- if (bus_params.chip_id == 0xffffffff) {
- ath10k_err(ar, "failed to get chip id\n");
- goto err_free_irq;
- }
+ if (bus_params.chip_id == 0xffffffff)
+ goto err_unsupported;
- if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
- ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
- pdev->device, bus_params.chip_id);
+ if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id))
goto err_free_irq;
- }
ret = ath10k_core_register(ar, &bus_params);
if (ret) {
@@ -3647,6 +3657,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
return 0;
+err_unsupported:
+ ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
+ pdev->device, bus_params.chip_id);
+
err_free_irq:
ath10k_pci_free_irq(ar);
ath10k_pci_rx_retry_sync(ar);
--
2.23.0
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 1a7fecb766c8 ath10k: reset chip before reading chip_id in probe.
The bot has tested the following trees: v5.2.13, v4.19.71, v4.14.142, v4.9.191, v4.4.191.
v5.2.13: Failed to apply! Possible dependencies:
6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
v4.19.71: Failed to apply! Possible dependencies:
31324d17976e ("ath10k: support extended board data download for dual-band QCA9984")
5849ed48d226 ("ath10k: refactoring needed for extended board data download")
6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
7c2dd6154fc2 ("ath10k: add device type enum to ath10k_bus_params")
ba94c753ccb4 ("ath10k: add QMI message handshake for wcn3990 client")
c0d8d565787c ("ath10k: add struct ath10k_bus_params")
de8781d7e74d ("ath10k: disable interface pause wow config for integrated chipset")
f1908735f141 ("ath10k: allow ATH10K_SNOC with COMPILE_TEST")
v4.14.142: Failed to apply! Possible dependencies:
0fa4fbe9b8cf ("ath10k: add hif power-up/power-down methods")
17f5559e0da5 ("ath10k: platform driver for WCN3990 SNOC WLAN module")
2a1e1ad3fd37 ("ath10k: Add support for 64 bit ce descriptor")
50c51f394e68 ("ath10k: do not mix spaces and tabs in Kconfig")
5dac5f3772f6 ("ath10k: Use dma_addr_t for ce buffers to support 64bit target")
6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
7f9befbb555d ("ath10k: move pktlog_filter out of ath10k_debug")
84efe7f6ebc5 ("ath10k: map HTC services to tx/rx pipes for wcn3990")
a0aedd6e0b57 ("ath10k: build ce layer in ath10k core module")
a6a793f98786 ("ath10k: vote for hardware resources for WCN3990")
a6e149a9ff03 ("ath10k: add hif start/stop methods for wcn3990 snoc layer")
ba94c753ccb4 ("ath10k: add QMI message handshake for wcn3990 client")
c0d8d565787c ("ath10k: add struct ath10k_bus_params")
c963a683e701 ("ath10k: add resource init and deinit for WCN3990")
d390509bdf50 ("ath10k: add hif tx methods for wcn3990")
dafa42036012 ("ath10k: use 64-bit crash dump timestamps")
e2fcf60c6fe8 ("ath10k: detach coredump.c from debug.c")
f1908735f141 ("ath10k: allow ATH10K_SNOC with COMPILE_TEST")
f25b9f285a0e ("ath10k: refactor firmware crashdump code to coredump.c")
v4.9.191: Failed to apply! Possible dependencies:
0fa4fbe9b8cf ("ath10k: add hif power-up/power-down methods")
17f5559e0da5 ("ath10k: platform driver for WCN3990 SNOC WLAN module")
4db66499df91 ("ath10k: add initial USB support")
50c51f394e68 ("ath10k: do not mix spaces and tabs in Kconfig")
5524ddd4c1f1 ("ath10k: select WANT_DEV_COREDUMP")
6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
84efe7f6ebc5 ("ath10k: map HTC services to tx/rx pipes for wcn3990")
a0aedd6e0b57 ("ath10k: build ce layer in ath10k core module")
a6a793f98786 ("ath10k: vote for hardware resources for WCN3990")
a6e149a9ff03 ("ath10k: add hif start/stop methods for wcn3990 snoc layer")
ba94c753ccb4 ("ath10k: add QMI message handshake for wcn3990 client")
c0d8d565787c ("ath10k: add struct ath10k_bus_params")
c963a683e701 ("ath10k: add resource init and deinit for WCN3990")
cec17c382140 ("ath10k: add per peer htt tx stats support for 10.4")
d390509bdf50 ("ath10k: add hif tx methods for wcn3990")
d96db25d2025 ("ath10k: add initial SDIO support")
f1908735f141 ("ath10k: allow ATH10K_SNOC with COMPILE_TEST")
v4.4.191: Failed to apply! Possible dependencies:
0b523ced9a3c ("ath10k: add basic skeleton to support ahb")
0d87c9208a17 ("ath10k: expose hif ops for ahb")
133df0f849bc ("ath10k: add chip and bus halt logic in ahb")
14854bfd9daa ("ath10k: add reset ctrl related functions in ahb")
1c44fcb9234c ("ath10k: include irq related functions in ahb")
4ddb3299aa49 ("ath10k: make ath10k_pci_read32/write32() ops more generic")
6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
704dc4e36769 ("ath10k: add resource init and deinit in ahb")
7f8e79cdc253 ("ath10k: add helper functions in ahb.c for reg rd/wr")
8beff219c528 ("ath10k: add clock ctrl related functions in ahb")
f52f517189de ("ath10k: make some of ath10k_pci_* func reusable")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks,
Sasha
Hello,
On Saturday, September 7, 2019 11:43:58 PM CEST Sasha Levin wrote:
> This commit has been processed because it contains a "Fixes:" tag,
> fixing commit: 1a7fecb766c8 ath10k: reset chip before reading chip_id in probe.
>
> The bot has tested the following trees: v5.2.13, v4.19.71, v4.14.142, v4.9.191, v4.4.191.
>
> v5.2.13: Failed to apply! Possible dependencies:
> 6d084ac27ab4 ("ath10k: initialise struct ath10k_bus params to zero")
The bot is right. Either add that patch or remove the "= {};" from the patch
that was sent to linux-wireless (based on "wireless-testing.git").
Alternatively, I've also added patches (as file attachments, I did this in
the hopes of fooling patchwork and the bots at least a bit... as well as
parking the patches for later). That said, I think this will go horribly
wrong because of this response. Since It has been a long time since I needed
a multi-version patch so I'm sorry for not being up-to-date with the latest
for-stable meta.
> v4.19.71: Failed to apply! Possible dependencies:
> 31324d17976e ("ath10k: support extended board data download for dual-band QCA9984")
> [...] too much
> [...]: [...]
>
> NOTE: The patch will not be queued to stable trees until it is upstream.
>
> How should we proceed with this patch?
You could let loose your ci-bot on the attached patches and see if they would
do the trick. I'm very optimistic that this will need some more time though.
So, "let's cross that bridge whenever we get there."
Cheers,
Christian
On 06/09/2019, Christian Lamparter <[email protected]> wrote:
> This patch restores the old behavior that read
> the chip_id on the QCA988x before resetting the
> chip. This needs to be done in this order since
> the unsupported QCA988x AR1A chips fall off the
> bus when resetted. Otherwise the next MMIO Op
> after the reset causes a BUS ERROR and panic.
>
> Cc: [email protected]
> Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
> Signed-off-by: Christian Lamparter <[email protected]>
> ---
> drivers/net/wireless/ath/ath10k/pci.c | 36 +++++++++++++++++++--------
> 1 file changed, 25 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath10k/pci.c
> b/drivers/net/wireless/ath/ath10k/pci.c
> index a0b4d265c6eb..347bb92e4130 100644
> --- a/drivers/net/wireless/ath/ath10k/pci.c
> +++ b/drivers/net/wireless/ath/ath10k/pci.c
> @@ -3490,7 +3490,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
> struct ath10k_pci *ar_pci;
> enum ath10k_hw_rev hw_rev;
> struct ath10k_bus_params bus_params = {};
> - bool pci_ps;
> + bool pci_ps, is_qca988x = false;
> int (*pci_soft_reset)(struct ath10k *ar);
> int (*pci_hard_reset)(struct ath10k *ar);
> u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
> @@ -3500,6 +3500,7 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
> case QCA988X_2_0_DEVICE_ID:
> hw_rev = ATH10K_HW_QCA988X;
> pci_ps = false;
> + is_qca988x = true;
> pci_soft_reset = ath10k_pci_warm_reset;
> pci_hard_reset = ath10k_pci_qca988x_chip_reset;
> targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
> @@ -3619,25 +3620,34 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
> goto err_deinit_irq;
> }
>
> + bus_params.dev_type = ATH10K_DEV_TYPE_LL;
> + bus_params.link_can_suspend = true;
> + /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that
> + * fall off the bus during chip_reset. These chips have the same pci
> + * device id as the QCA9880 BR4A or 2R4E. So that's why the check.
> + */
> + if (is_qca988x) {
> + bus_params.chip_id =
> + ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
> + if (bus_params.chip_id != 0xffffffff) {
> + if (!ath10k_pci_chip_is_supported(pdev->device,
> + bus_params.chip_id))
> + goto err_unsupported;
> + }
> + }
> +
> ret = ath10k_pci_chip_reset(ar);
> if (ret) {
> ath10k_err(ar, "failed to reset chip: %d\n", ret);
> goto err_free_irq;
> }
>
> - bus_params.dev_type = ATH10K_DEV_TYPE_LL;
> - bus_params.link_can_suspend = true;
> bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
> - if (bus_params.chip_id == 0xffffffff) {
> - ath10k_err(ar, "failed to get chip id\n");
> - goto err_free_irq;
> - }
> + if (bus_params.chip_id == 0xffffffff)
> + goto err_unsupported;
>
> - if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
> - ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
> - pdev->device, bus_params.chip_id);
> + if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id))
> goto err_free_irq;
> - }
>
> ret = ath10k_core_register(ar, &bus_params);
> if (ret) {
> @@ -3647,6 +3657,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
>
> return 0;
>
> +err_unsupported:
> + ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
> + pdev->device, bus_params.chip_id);
> +
> err_free_irq:
> ath10k_pci_free_irq(ar);
> ath10k_pci_rx_retry_sync(ar);
> --
> 2.23.0
>
>
Looks fine. For the time being. Have you looked any further to
actually support this chip? It seems warm reset is causing bus errors,
and cold reset goes through without crash.
Firmware gets loaded but is stuck at receiving control response, most
likely because of htc packet length or response message length.
Hi Kalle
According to this very old post
http://lists.infradead.org/pipermail/ath10k/2013-July/000021.html
seems like you've been misinformed on amount of these cards that were
put out in the market.
At least digipart only have >40000 units in stocks
https://www.digipart.com/part/QCA9880-AR1A and other retailers
probably few thousands more.
With that large amount of cards I think it is justified to request
firmware support for the chip. And probably a lot easier to make few
firmware modifications than go hacking a bunch of API calls so it
works with v2 firmware.
I made some modifications to driver and it differentiates properly
between v1 and v2 card, this is the current status bootlog:
[ 0.000000] Linux version 4.19.57 (whtw46ww4@I5576) (gcc version
7.4.0 (OpenWrt GCC 7.4.0 r10563-db8e08a)) #0 Sun Jul 21 09:26:06 2019
[ 0.000000] bootconsole [early0] enabled
[ 0.000000] CPU0 revision is: 00019750 (MIPS 74Kc)
[ 0.000000] MIPS: machine is TP-Link Archer C7 v1
[ 0.000000] SoC: Qualcomm Atheros QCA9558 ver 1 rev 0
[ 0.000000] Determined physical RAM map:
[ 0.000000] memory: 08000000 @ 00000000 (usable)
[ 0.000000] debug: ignoring loglevel setting.
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases,
linesize 32 bytes
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] On node 0 totalpages: 32768
[ 0.000000] Normal zone: 288 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 32768 pages, LIFO batch:7
[ 0.000000] random: get_random_bytes called from
start_kernel+0x98/0x51c with crng_init=0
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480
[ 0.000000] Kernel command line: console=ttyS0,115200n8
rootfstype=squashfs,jffs2 ignore_loglevel
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Writing ErrCtl register=00000000
[ 0.000000] Readback ErrCtl register=00000000
[ 0.000000] Memory: 118256K/131072K available (4518K kernel code,
269K rwdata, 1104K rodata, 4980K init, 215K bss, 12816K reserved, 0K
cma-reserved)
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 51
[ 0.000000] CPU clock: 720.000 MHz
[ 0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 5309056796 ns
[ 0.000007] sched_clock: 32 bits at 360MHz, resolution 2ns, wraps
every 5965232126ns
[ 0.008691] Calibrating delay loop... 358.80 BogoMIPS (lpj=1794048)
[ 0.075695] pid_max: default: 32768 minimum: 301
[ 0.081040] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.088408] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.100532] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.111534] futex hash table entries: 256 (order: -1, 3072 bytes)
[ 0.118449] pinctrl core: initialized pinctrl subsystem
[ 0.125072] NET: Registered protocol family 16
[ 0.137497] PCI host bridge /ahb/pcie-controller@18250000 ranges:
[ 0.144293] MEM 0x0000000012000000..0x0000000013ffffff
[ 0.150153] IO 0x0000000000000001..0x0000000000000001
[ 0.173135] PCI host bridge to bus 0000:00
[ 0.177708] pci_bus 0000:00: root bus resource [mem 0x12000000-0x13ffffff]
[ 0.185419] pci_bus 0000:00: root bus resource [io 0x0001]
[ 0.191622] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
[ 0.199195] pci_bus 0000:00: No busn resource found for root bus,
will use [bus 00-ff]
[ 0.208053] pci 0000:00:00.0: [168c:003c] type 00 class 0x028000
[ 0.214800] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x001fffff 64bit]
[ 0.222408] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x0000ffff pref]
[ 0.229953] pci 0000:00:00.0: supports D1 D2
[ 0.235724] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
[ 0.243140] pci 0000:00:00.0: BAR 0: assigned [mem
0x12000000-0x121fffff 64bit]
[ 0.251297] pci 0000:00:00.0: BAR 6: assigned [mem
0x12200000-0x1220ffff pref]
[ 0.262142] clocksource: Switched to clocksource MIPS
[ 0.304897] NET: Registered protocol family 2
[ 0.310448] tcp_listen_portaddr_hash hash table entries: 512
(order: 0, 4096 bytes)
[ 0.319090] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.326880] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.333978] TCP: Hash tables configured (established 1024 bind 1024)
[ 0.341161] UDP hash table entries: 256 (order: 0, 4096 bytes)
[ 0.347721] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[ 0.355054] NET: Registered protocol family 1
[ 0.359955] PCI: CLS 0 bytes, default 32
[ 2.602152] random: fast init done
[ 5.128772] Crashlog allocated RAM at address 0x3f00000
[ 5.135884] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[ 5.148697] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 5.155250] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME)
(CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[ 5.232790] io scheduler noop registered
[ 5.237160] io scheduler deadline registered (default)
[ 5.243159] ar7200-usb-phy 18030000.usb-phy0: phy reset is missing
[ 5.250094] ar7200-usb-phy 18030010.usb-phy1: phy reset is missing
[ 5.258595] pinctrl-single 1804002c.pinmux: 544 pins, size 68
[ 5.265572] gpio-export gpio-export: 2 gpio(s) exported
[ 5.272126] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[ 5.279862] console [ttyS0] disabled
[ 5.283922] 18020000.uart: ttyS0 at MMIO 0x18020000 (irq = 9,
base_baud = 2500000) is a 16550A
[ 5.293553] console [ttyS0] enabled
[ 5.300959] bootconsole [early0] disabled
[ 5.327081] m25p80 spi0.0: s25fl064k (8192 Kbytes)
[ 5.331977] 3 fixed-partitions partitions found on MTD device spi0.0
[ 5.338440] Creating 3 MTD partitions on "spi0.0":
[ 5.343320] 0x000000000000-0x000000020000 : "u-boot"
[ 5.349085] 0x000000020000-0x0000007f0000 : "firmware"
[ 5.356806] 2 tplink-fw partitions found on MTD device firmware
[ 5.362861] Creating 2 MTD partitions on "firmware":
[ 5.367902] 0x000000000000-0x000000100000 : "kernel"
[ 5.373680] 0x000000100000-0x0000007d0000 : "rootfs"
[ 5.379320] mtd: device 3 (rootfs) set to be root filesystem
[ 5.386376] mtdsplit: no squashfs found in "rootfs"
[ 5.391368] 0x0000007f0000-0x000000800000 : "art"
[ 5.397879] libphy: Fixed MDIO Bus: probed
[ 5.753920] libphy: ag71xx_mdio: probed
[ 5.778627] switch0: Atheros AR8327 rev. 4 switch registered on mdio-bus.0
[ 6.431314] ag71xx 19000000.eth: connected to PHY at mdio-bus.0:00
[uid=004dd034, driver=Atheros AR8216/AR8236/AR8316]
[ 6.442773] eth0: Atheros AG71xx at 0xb9000000, irq 4, mode: rgmii
[ 6.801780] ag71xx 1a000000.eth: connected to PHY at fixed-0:00
[uid=00000000, driver=Generic PHY]
[ 6.811442] eth1: Atheros AG71xx at 0xba000000, irq 5, mode: sgmii
[ 6.820003] NET: Registered protocol family 10
[ 6.829252] Segment Routing with IPv6
[ 6.833117] NET: Registered protocol family 17
[ 6.837701] 8021q: 802.1Q VLAN Support v1.8
[ 6.862923] Freeing unused kernel memory: 4980K
[ 6.867527] This architecture does not have kernel memory protection.
[ 6.874085] Run /init as init process
[ 6.889985] init: Console is alive
[ 6.893771] init: - watchdog -
[ 6.915582] kmodloader: loading kernel modules from /etc/modules-boot.d/*
[ 6.931970] usbcore: registered new interface driver usbfs
[ 6.937657] usbcore: registered new interface driver hub
[ 6.943149] usbcore: registered new device driver usb
[ 6.953795] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 6.961871] ehci-platform: EHCI generic platform driver
[ 6.967460] ehci-platform 1b000000.usb: EHCI Host Controller
[ 6.973270] ehci-platform 1b000000.usb: new USB bus registered,
assigned bus number 1
[ 6.981281] ehci-platform 1b000000.usb: irq 14, io mem 0x1b000000
[ 7.012216] ehci-platform 1b000000.usb: USB 2.0 started, EHCI 1.00
[ 7.019257] hub 1-0:1.0: USB hub found
[ 7.023457] hub 1-0:1.0: 1 port detected
[ 7.027987] ehci-platform 1b400000.usb: EHCI Host Controller
[ 7.033824] ehci-platform 1b400000.usb: new USB bus registered,
assigned bus number 2
[ 7.041847] ehci-platform 1b400000.usb: irq 15, io mem 0x1b400000
[ 7.072165] ehci-platform 1b400000.usb: USB 2.0 started, EHCI 1.00
[ 7.079206] hub 2-0:1.0: USB hub found
[ 7.083403] hub 2-0:1.0: 1 port detected
[ 7.088430] kmodloader: done loading kernel modules from
/etc/modules-boot.d/*
[ 7.106193] init: - preinit -
[ 7.291223] random: jshn: uninitialized urandom read (4 bytes read)
[ 7.369076] random: jshn: uninitialized urandom read (4 bytes read)
[ 7.538353] random: jshn: uninitialized urandom read (4 bytes read)
[ 8.515044] urandom_read: 4 callbacks suppressed
[ 8.515051] random: procd: uninitialized urandom read (4 bytes read)
[ 8.531594] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 8.537651] IPv6: ADDRCONF(NETDEV_UP): eth1.1: link is not ready
[ 9.573291] eth1: link up (1000Mbps/Full duplex)
[ 9.577999] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[ 9.584709] IPv6: ADDRCONF(NETDEV_CHANGE): eth1.1: link becomes ready
[ 11.669504] eth1: link down
[ 11.688655] procd: - early -
[ 11.691672] procd: - watchdog -
[ 12.239816] procd: - watchdog -
[ 12.243288] procd: - ubus -
[ 12.252031] random: ubusd: uninitialized urandom read (4 bytes read)
[ 12.296521] random: ubusd: uninitialized urandom read (4 bytes read)
[ 12.304295] procd: - init -
[ 12.714303] kmodloader: loading kernel modules from /etc/modules.d/*
[ 12.730578] urngd: v1.0.0 started.
[ 12.756700] Loading modules backported from Linux version
v5.2-rc7-0-g6fbc7275c7a9
[ 12.764427] Backport generated by backports.git v5.2-rc7-1-0-g021a6ba1
[ 12.820407] xt_time: kernel timezone is -0000
[ 12.982093] PPP generic driver version 2.4.2
[ 12.992983] NET: Registered protocol family 24
[ 13.002433] random: crng init done
[ 13.038820] ath10k_pci 0000:00:00.0: pci probe 168c:003c 168c:3223
[ 13.045528] ath10k_pci 0000:00:00.0: enabling device (0000 -> 0002)
[ 13.051917] ath10k_pci 0000:00:00.0: boot pci_mem 0x1cb18953
[ 13.060199] ath10k_pci 0000:00:00.0: pci irq legacy oper_irq_mode 1
irq_mode 0 reset_mode 0
[ 13.068700] ath10k_pci 0000:00:00.0: boot qca99x0 chip reset
[ 13.074453] ath10k_pci 0000:00:00.0: boot cold reset
[ 13.079495] ath10k_pci 0000:00:00.0: boot target and PCIe out of reset
[ 13.086124] ath10k_pci 0000:00:00.0: boot cold reset complete
[ 13.091955] ath10k_pci 0000:00:00.0: boot waiting target to initialise
[ 13.098589] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.114327] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.130053] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.145790] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.161521] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.177252] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.192988] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.208717] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.224458] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.240183] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.255914] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.271643] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.287376] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.303112] ath10k_pci 0000:00:00.0: boot target indicator 0
[ 13.318842] ath10k_pci 0000:00:00.0: boot target indicator 2
[ 13.324613] ath10k_pci 0000:00:00.0: boot target initialised
[ 13.330355] ath10k_pci 0000:00:00.0: boot qca99x0 chip reset complete (cold)
[ 13.337552] ath10k_pci 0000:00:00.0: boot hif power up
[ 13.342788] ath10k_pci 0000:00:00.0: boot qca99x0 chip reset
[ 13.348528] ath10k_pci 0000:00:00.0: boot cold reset
[ 13.353584] ath10k_pci 0000:00:00.0: boot target and PCIe out of reset
[ 13.360205] ath10k_pci 0000:00:00.0: boot cold reset complete
[ 13.366043] ath10k_pci 0000:00:00.0: boot waiting target to initialise
[ 13.372678] ath10k_pci 0000:00:00.0: boot target indicator 2
[ 13.378428] ath10k_pci 0000:00:00.0: boot target initialised
[ 13.384181] ath10k_pci 0000:00:00.0: boot qca99x0 chip reset complete (cold)
[ 13.391374] ath10k_pci 0000:00:00.0: boot init ce src ring id 0
entries 16 base_addr 2ceb9a7e
[ 13.400070] ath10k_pci 0000:00:00.0: boot ce dest ring id 1 entries
128 base_addr 289c278c
[ 13.408497] ath10k_pci 0000:00:00.0: boot ce dest ring id 2 entries
64 base_addr c0e40e4c
[ 13.416844] ath10k_pci 0000:00:00.0: boot init ce src ring id 3
entries 32 base_addr 139e13fb
[ 13.425772] ath10k_pci 0000:00:00.0: boot init ce src ring id 4
entries 8192 base_addr 42800924
[ 13.434638] ath10k_pci 0000:00:00.0: boot ce dest ring id 5 entries
128 base_addr 230402d2
[ 13.443068] ath10k_pci 0000:00:00.0: boot init ce src ring id 7
entries 2 base_addr 11334358
[ 13.451652] ath10k_pci 0000:00:00.0: boot ce dest ring id 7 entries
2 base_addr 70d67374
[ 13.460652] ath10k_pci 0000:00:00.0: bmi get target info
[ 13.466143] ath10k_pci 0000:00:00.0: Hardware name qca988x hw1.0
version 0x4000002c
[ 13.563795] firmware ath10k!pre-cal-pci-0000:00:00.0.bin:
firmware_loading_store: map pages failed
[ 13.573090] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/pre-cal-pci-0000:00:00.0.bin': -11
[ 13.761310] firmware ath10k!cal-pci-0000:00:00.0.bin:
firmware_loading_store: map pages failed
[ 13.770242] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/cal-pci-0000:00:00.0.bin': -11
[ 13.778749] ath10k_pci 0000:00:00.0: trying fw api 6
[ 13.962772] firmware ath10k!QCA988X!hw2.0!firmware-6.bin:
firmware_loading_store: map pages failed
[ 13.972018] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/QCA988X/hw2.0/firmware-6.bin': -11
[ 13.980888] ath10k_pci 0000:00:00.0: trying fw api 5
[ 14.004273] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/QCA988X/hw2.0/firmware-5.bin': 0
[ 14.012975] ath10k_pci 0000:00:00.0: found fw version 10.2.4-1.0-00043
[ 14.019600] ath10k_pci 0000:00:00.0: found fw timestamp 1541656652
[ 14.025891] ath10k_pci 0000:00:00.0: found otp image ie (7221 B)
[ 14.031981] ath10k_pci 0000:00:00.0: found fw image ie (241515 B)
[ 14.038172] ath10k_pci 0000:00:00.0: found firmware features ie (3 B)
[ 14.044715] ath10k_pci 0000:00:00.0: Enabling feature bit: 3
[ 14.050452] ath10k_pci 0000:00:00.0: Enabling feature bit: 10
[ 14.056292] ath10k_pci 0000:00:00.0: Enabling feature bit: 12
[ 14.062121] ath10k_pci 0000:00:00.0: Enabling feature bit: 16
[ 14.067957] ath10k_pci 0000:00:00.0: features
[ 14.072396] ath10k_pci 0000:00:00.0: 00000000: 00 01 14 08
....
[ 14.081658] ath10k_pci 0000:00:00.0: found fw ie wmi op version 5
[ 14.087848] ath10k_pci 0000:00:00.0: found fw ie htt op version 2
[ 14.094046] ath10k_pci 0000:00:00.0: using fw api 5
[ 14.099004] ath10k_pci 0000:00:00.0: qca988x hw1.0 target
0x4000002c chip_id 0x043200ff sub 168c:3223
[ 14.108373] ath10k_pci 0000:00:00.0: kconfig debug 1 debugfs 1
tracing 1 dfs 1 testmode 1
[ 14.121519] ath10k_pci 0000:00:00.0: firmware ver 10.2.4-1.0-00043
api 5 features no-p2p,raw-mode,mfp,allows-mesh-bcast crc32 ed0aafd8
[ 14.133799] ath10k_pci 0000:00:00.0: boot did not find a pre
calibration file, try DT next: -11
[ 14.142638] ath10k_pci 0000:00:00.0: unable to load pre cal data from DT: -2
[ 14.149787] ath10k_pci 0000:00:00.0: could not load pre cal data: -2
[ 14.156243] ath10k_pci 0000:00:00.0: boot upload otp to 0x1234 len
7221 for board id
[ 14.164111] ath10k_pci 0000:00:00.0: bmi fast download address
0x1234 buffer 0x3ca910fe length 7221
[ 14.173297] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x1234
[ 14.253843] ath10k_pci 0000:00:00.0: bmi lz data buffer 0x3ca910fe
length 7220
[ 14.285961] ath10k_pci 0000:00:00.0: bmi lz data buffer 0x9fc59964 length 4
[ 14.293057] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x0
[ 14.299517] ath10k_pci 0000:00:00.0: bmi execute address 0x1234 param 0x10
[ 14.306655] ath10k_pci 0000:00:00.0: bmi execute result 0x10
[ 14.312413] ath10k_pci 0000:00:00.0: boot get otp board id result
0x00000010 board_id 0 chip_id 0 ext_bid_support 0
[ 14.323010] ath10k_pci 0000:00:00.0: board id does not exist in
otp, ignore it
[ 14.330335] ath10k_pci 0000:00:00.0: SMBIOS bdf variant name not set.
[ 14.336877] ath10k_pci 0000:00:00.0: DT bdf variant name not set.
[ 14.343077] ath10k_pci 0000:00:00.0: boot using board name
'bus=pci,vendor=168c,device=003c,subsystem-vendor=168c,subsystem-device=3223'
[ 14.355522] ath10k_pci 0000:00:00.0: boot using board name
'bus=pci,vendor=168c,device=003c,subsystem-vendor=168c,subsystem-device=3223'
[ 14.458077] firmware ath10k!QCA988X!hw2.0!board-2.bin:
firmware_loading_store: map pages failed
[ 14.467099] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/QCA988X/hw2.0/board-2.bin': -11
[ 14.482333] ath10k_pci 0000:00:00.0: boot fw request
'ath10k/QCA988X/hw2.0/board.bin': 0
[ 14.490551] ath10k_pci 0000:00:00.0: using board api 1
[ 14.495851] ath10k_pci 0000:00:00.0: board_file api 1 bmi_id N/A
crc32 bebc7c08
[ 14.503280] ath10k_pci 0000:00:00.0: bmi start
[ 14.507790] ath10k_pci 0000:00:00.0: bmi write address 0x400800 length 4
[ 14.546287] ath10k_pci 0000:00:00.0: bmi read address 0x400810 length 4
[ 14.557471] ath10k_pci 0000:00:00.0: bmi write address 0x400810 length 4
[ 14.572212] ath10k_pci 0000:00:00.0: bmi write address 0x400844 length 4
[ 14.592214] ath10k_pci 0000:00:00.0: bmi write address 0x400904 length 4
[ 14.602208] ath10k_pci 0000:00:00.0: bmi write address 0x4008bc length 4
[ 14.622213] ath10k_pci 0000:00:00.0: boot did not find a pre
calibration file, try DT next: -11
[ 14.631043] ath10k_pci 0000:00:00.0: unable to load pre cal data from DT: -2
[ 14.638205] ath10k_pci 0000:00:00.0: failed to load pre cal data: -2
[ 14.644657] ath10k_pci 0000:00:00.0: pre cal download procedure
failed, try cal file: -2
[ 14.652880] ath10k_pci 0000:00:00.0: boot did not find a
calibration file, try DT next: -11
[ 14.661349] ath10k_pci 0000:00:00.0: boot did not find DT entry,
try target EEPROM next: -2
[ 14.669830] ath10k_pci 0000:00:00.0: boot did not find target
EEPROM entry, try OTP next: -122
[ 14.678578] ath10k_pci 0000:00:00.0: bmi read address 0x4008ac length 4
[ 14.695286] ath10k_pci 0000:00:00.0: boot push board extended data addr 0x0
[ 14.702401] ath10k_pci 0000:00:00.0: bmi read address 0x400854 length 4
[ 14.709186] ath10k_pci 0000:00:00.0: bmi write address 0x401cb0 length 2116
[ 14.719947] ath10k_pci 0000:00:00.0: bmi write address 0x400858 length 4
[ 14.726782] ath10k_pci 0000:00:00.0: boot upload otp to 0x1234 len 7221
[ 14.733509] ath10k_pci 0000:00:00.0: bmi fast download address
0x1234 buffer 0x3ca910fe length 7221
[ 14.742691] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x1234
[ 14.749419] ath10k_pci 0000:00:00.0: bmi lz data buffer 0x3ca910fe
length 7220
[ 14.781532] ath10k_pci 0000:00:00.0: bmi lz data buffer 0x51c0dfb6 length 4
[ 14.788635] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x0
[ 14.795111] ath10k_pci 0000:00:00.0: bmi execute address 0x1234 param 0x0
[ 14.802126] ath10k_pci 0000:00:00.0: bmi execute result 0x0
[ 14.807791] ath10k_pci 0000:00:00.0: boot otp execute result 0
[ 14.813716] ath10k_pci 0000:00:00.0: boot using calibration mode otp
[ 14.820166] ath10k_pci 0000:00:00.0: boot uploading firmware image
c21dc34c len 241515
[ 14.828219] ath10k_pci 0000:00:00.0: bmi fast download address
0x1234 buffer 0xc21dc34c length 241515
[ 14.837583] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x1234
[ 14.844343] ath10k_pci 0000:00:00.0: bmi lz data buffer 0xc21dc34c
length 241512
[ 15.865780] ath10k_pci 0000:00:00.0: bmi lz data buffer 0x9fc59964 length 4
[ 15.872878] ath10k_pci 0000:00:00.0: bmi lz stream start address 0x0
[ 15.879337] ath10k_pci 0000:00:00.0: bmi write address 0x400814 length 4
[ 15.886185] ath10k_pci 0000:00:00.0: pci hif map service
[ 15.891585] ath10k_pci 0000:00:00.0: boot htc service 'Control' ul
pipe 0 dl pipe 1 eid 0 ready
[ 15.900428] ath10k_pci 0000:00:00.0: boot htc service 'Control' eid
0 TX flow control disabled
[ 15.909175] ath10k_pci 0000:00:00.0: bmi done
[ 15.913627] ath10k_pci 0000:00:00.0: htt tx max num pending tx 1424
[ 15.920206] ath10k_pci 0000:00:00.0: htt rx ring size 512 fill_level 255
[ 15.927035] ath10k_pci 0000:00:00.0: boot hif start
[ 17.012155] ath10k_pci 0000:00:00.0: failed to receive control
response completion, polling..
[ 17.020805] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.026909] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.032936] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.039476] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.046029] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.052581] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.059117] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.065671] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.072224] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.078760] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.085320] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.091414] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.097440] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.103994] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.110538] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.117087] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.123640] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.130178] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.136730] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.143284] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.149842] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.155950] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.161967] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.168516] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.175068] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.181606] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.188157] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.194711] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.201246] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.207802] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.214355] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.220448] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.226478] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.233029] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.239570] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.246128] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.252675] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.259212] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.265764] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.272319] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.278861] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.284967] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.290980] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.297533] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.304084] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.310620] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.317176] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.323729] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.330274] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.336824] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.343380] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.349474] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.355501] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.362044] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.368594] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.375144] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.381682] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.388235] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 0 0
[ 17.394790] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.401331] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.407900] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.414006] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.420018] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.426570] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.433119] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.439659] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.446207] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.452753] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 127 0
[ 17.459288] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.465844] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 17.472393] ath10k_pci 0000:00:00.0: pci hif send complete check
[ 17.478482] ath10k_pci 0000:00:00.0: Copy Engine register dump:
[ 17.484509] ath10k_pci 0000:00:00.0: [00]: 0x00057400 10 10 11 10
[ 17.491052] ath10k_pci 0000:00:00.0: [01]: 0x00057800 6 6 5 6
[ 17.497600] ath10k_pci 0000:00:00.0: [02]: 0x00057c00 0 0 63 0
[ 17.504152] ath10k_pci 0000:00:00.0: [03]: 0x00058000 0 0 0 0
[ 17.510689] ath10k_pci 0000:00:00.0: [04]: 0x00058400 0 0 0 0
[ 17.517242] ath10k_pci 0000:00:00.0: [05]: 0x00058800 0 0 127 0
[ 17.523797] ath10k_pci 0000:00:00.0: [06]: 0x00058c00 0 0 0 0
[ 17.530341] ath10k_pci 0000:00:00.0: [07]: 0x00059000 1 1 1 1
[ 18.612158] ath10k_pci 0000:00:00.0: ctl_resp never came in (-145)
[ 18.618427] ath10k_pci 0000:00:00.0: failed to connect to HTC: -145
[ 18.624797] ath10k_pci 0000:00:00.0: boot hif stop
[ 18.630758] ath10k_pci 0000:00:00.0: could not init core (-145)
[ 18.636893] ath10k_pci 0000:00:00.0: boot hif power down
[ 18.642304] ath10k_pci 0000:00:00.0: could not probe fw (-145)
[ 18.694782] ath: EEPROM regdomain: 0x0
[ 18.698591] ath: EEPROM indicates default country code should be used
[ 18.705152] ath: doing EEPROM country->regdmn map search
[ 18.710550] ath: country maps to regdmn code: 0x3a
[ 18.715420] ath: Country alpha2 being used: US
[ 18.719921] ath: Regpair used: 0x3a
[ 18.741147] ieee80211 phy1: Selected rate control algorithm 'minstrel_ht'
[ 18.749490] ieee80211 phy1: Atheros AR9550 Rev:0 mem=0xb8100000, irq=12
[ 18.812526] kmodloader: done loading kernel modules from /etc/modules.d/*
[ 47.429359] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 47.436481] eth1: link up (1000Mbps/Full duplex)
[ 47.441181] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[ 47.475602] br-lan: port 1(eth1.1) entered blocking state
[ 47.481087] br-lan: port 1(eth1.1) entered disabled state
[ 47.486905] device eth1.1 entered promiscuous mode
[ 47.491769] device eth1 entered promiscuous mode
[ 47.546852] br-lan: port 1(eth1.1) entered blocking state
[ 47.552373] br-lan: port 1(eth1.1) entered forwarding state
[ 47.558177] IPv6: ADDRCONF(NETDEV_UP): br-lan: link is not ready
[ 47.646842] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 47.674813] IPv6: ADDRCONF(NETDEV_UP): eth0.2: link is not ready
[ 48.452468] IPv6: ADDRCONF(NETDEV_CHANGE): br-lan: link becomes ready
[ 48.693435] eth0: link up (1000Mbps/Full duplex)
[ 48.698191] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 48.722234] IPv6: ADDRCONF(NETDEV_CHANGE): eth0.2: link becomes ready
Regards, Tom
(dropping stable list)
Tom Psyborg <[email protected]> writes:
> According to this very old post
> http://lists.infradead.org/pipermail/ath10k/2013-July/000021.html
> seems like you've been misinformed on amount of these cards that were
> put out in the market.
>
> At least digipart only have >40000 units in stocks
> https://www.digipart.com/part/QCA9880-AR1A and other retailers
> probably few thousands more.
>
> With that large amount of cards I think it is justified to request
> firmware support for the chip. And probably a lot easier to make few
> firmware modifications than go hacking a bunch of API calls so it
> works with v2 firmware.
I'm very surprised that QCA9880 hw1.0 boards are still available, after
six years. Did you confirm that it really is hw1.0 and not just some
mixup with hardware ids or something like that? For example, you could
try the old ath10k and old hw1.0 firmware to see if it works.
But if it's really is hw1.0 I doubt there will be any support for that.
I recommend to avoid hw1.0 altogether.
--
Kalle Valo
On 10/09/2019, Kalle Valo <[email protected]> wrote:
> (dropping stable list)
>
> Tom Psyborg <[email protected]> writes:
>
>> According to this very old post
>> http://lists.infradead.org/pipermail/ath10k/2013-July/000021.html
>> seems like you've been misinformed on amount of these cards that were
>> put out in the market.
>>
>> At least digipart only have >40000 units in stocks
>> https://www.digipart.com/part/QCA9880-AR1A and other retailers
>> probably few thousands more.
>>
>> With that large amount of cards I think it is justified to request
>> firmware support for the chip. And probably a lot easier to make few
>> firmware modifications than go hacking a bunch of API calls so it
>> works with v2 firmware.
>
> I'm very surprised that QCA9880 hw1.0 boards are still available, after
> six years. Did you confirm that it really is hw1.0 and not just some
> mixup with hardware ids or something like that?
Print on the chip clearly says QCA9880-AR1A. ID same as for v2 - 003C.
> old hw1.0 firmware to see if it works.
I don't know which fw blob version that is. I could not find it
online. All files are v2 related.
>
> But if it's really is hw1.0 I doubt there will be any support for that.
> I recommend to avoid hw1.0 altogether.
>
> --
> Kalle Valo
>
That would be too bad, even worse when you find out that
qca-wifi-10.2.4.58.1 driver fails to load firmware too. The only one
that works is qca-wifi that comes with tp-link firmware, some very
early version 10.0.108 or somtehing like that that has no available
sources..
Christian Lamparter <[email protected]> wrote:
> This patch restores the old behavior that read
> the chip_id on the QCA988x before resetting the
> chip. This needs to be done in this order since
> the unsupported QCA988x AR1A chips fall off the
> bus when resetted. Otherwise the next MMIO Op
> after the reset causes a BUS ERROR and panic.
>
> Cc: [email protected]
> Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
> Signed-off-by: Christian Lamparter <[email protected]>
I'll drop this as there's no plan to support QCA988X hw1.0.
--
https://patchwork.kernel.org/patch/11136089/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
On 17/09/2019, Kalle Valo <[email protected]> wrote:
> Christian Lamparter <[email protected]> wrote:
>
>> This patch restores the old behavior that read
>> the chip_id on the QCA988x before resetting the
>> chip. This needs to be done in this order since
>> the unsupported QCA988x AR1A chips fall off the
>> bus when resetted. Otherwise the next MMIO Op
>> after the reset causes a BUS ERROR and panic.
>>
>> Cc: [email protected]
>> Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in
>> probe")
>> Signed-off-by: Christian Lamparter <[email protected]>
>
> I'll drop this as there's no plan to support QCA988X hw1.0.
>
> --
> https://patchwork.kernel.org/patch/11136089/
>
> https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
>
>
Maybe the whole subject on QCA988X cards should be re-evaluated? Since
at this point it's not for certain whether the card is difficult to
support or whether it is damaged.
There was at least one report of QCA988X hw2.0 failing in an identical
way as QCA988X hw1.0. In case it turns out to be hw damage, a fallback
driver mechanism could provide extended lifetime for these cards. A
link to the hw2.0 failure:
https://forum.openwrt.org/t/is-it-possible-to-brick-the-wireless-card-qca988x-irreversibly/32615
On Tuesday, September 17, 2019 8:44:12 AM CEST Kalle Valo wrote:
> Christian Lamparter <[email protected]> wrote:
>
> > This patch restores the old behavior that read
> > the chip_id on the QCA988x before resetting the
> > chip. This needs to be done in this order since
> > the unsupported QCA988x AR1A chips fall off the
> > bus when resetted. Otherwise the next MMIO Op
> > after the reset causes a BUS ERROR and panic.
> >
> > Cc: [email protected]
> > Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
> > Signed-off-by: Christian Lamparter <[email protected]>
>
> I'll drop this as there's no plan to support QCA988X hw1.0.
Kalle,
I'm surprised about this. And your justification
"no plan to support QCA988X hw1.0" seems very odd in this context,
because this patch does not add any support for the QCA988X hw1.0.
But, I could see how the mails/replies from Tom Psyborg derailed the
topic here. Though, I'm not sure if this is the case or not.
So let set the record straight and show you the result of having that
patch applied and load ath10k_pci with a QCA9880 v1 AR1A:
[ 1491.622282] ath10k_pci 0000:00:00.0: device 003c with chip_id 043200ff isn't supported
(System is all good!)
And without the patch:
[ 900.320000] Data bus error, epc == 86a9a1b0, ra == 86a9a4b0
[ 900.320000] Oops[#1]:
[ 900.320000] CPU: 0 PID: 8127 Comm: insmod Not tainted 5.2.16 #1
[ 900.320000] task: 8790dd50 ti: 86a2c000 task.ti: 86a2c000
[ 900.320000] $ 0 : 00000000 80350000 deadc0de 1000fc03
[ 900.320000] $ 4 : b2080000 8790dd50 1000fc00 ffff00fe
[ 900.320000] $ 8 : 86a2dfe0 0000fc00 00000000 00000000
[ 900.320000] $12 : 00000005 00000000 00000000 00420000
[ 900.320000] $16 : 00000009 8788d400 869f9000 87821800
[ 900.320000] $20 : 00000009 b2080008 b2080000 00000001
[ 900.320000] $24 : 00000000 8006b784
[ 900.320000] $28 : 86a2c000 86a2dba8 b2080004 86a7a5b0
[ 900.320000] Hi : 000000d1
[ 900.320000] Lo : 9ea86180
[ 900.320000] epc : 86a7a5b0 ath10k_pci_cold_reset+0xf88/0x1bb0 [ath10k_pci]
[ 900.320000] Not tainted
[ 900.320000] ra : 86a7a5b0 ath10k_pci_cold_reset+0xf88/0x1bb0 [ath10k_pci]
[ 900.320000] Status: 1000fc03 KERNEL EXL IE
[ 900.320000] Cause : 4080801c
[ 900.320000] PrId : 00019750 (MIPS 74Kc)
[ 900.320000] Modules linked in: ath10k_pci(+) ath10k_core [...]
[ 900.320000] Process insmod (pid: 1127, threadinfo=86a2c000, task=8790dd50, tls=775b1440)
[ 900.320000] Stack : 80301d90 8790dd50 8790dd50 80301d90 8790c430 80067e78 00000000 87821800
00080000 00000000 80373900 86a2dc0c 80373900 0000ea80 00000009 b2080008
b2080000 00000001 80373900 80066964 86a2dc0c 80081e80 8790dd50 86a63924
00000001 00000000 00200200 0000ea80 80373900 80081e80 8790dd50 ffffffff
8788d400 00000009 8788d400 86a2dc58 87821800 80082398 86a2dc5c 86a7d140
...
[ 900.320000] Call Trace:
[ 900.320000] [<86a7a5b0>] ath10k_pci_cold_reset+0xf88/0x1bb0 [ath10k_pci]
[ 900.320000]
[ 900.320000]
Code: 2410000a 0c0621d3 02c02021 <30420400> 10400006 00002021 24040001 0c0208de 2610ffff
[ 900.570000] ---[ end trace 1e4e2b7fd4ac9eb8 ]---
Segmentation fault
Notice the DATA BUS Error! The router is unusable at that point and no longer "working".
As for why this patch was coded this way. It's because this patch follows Michał Kazior
recommendation of how to handle this card in his reply to a previous thread
"ath10k: reset chip after supported check" regarding the same issue. He did check for a
QCA988X Hardware and only then perform the SOC_CHIP_ID_ADDRESS read.
<https://patchwork.kernel.org/patch/10866417/#22549011>
|That makes sense, but I don't see how blacklisting pci slots would
|help someone putting v2 nic into C7v1 mobo? Won't the slot be the same
|regardless what nic is put?
|
|The best thing I can come up with is something like this:
|
|--- a/drivers/net/wireless/ath/ath10k/pci.c
|+++ b/drivers/net/wireless/ath/ath10k/pci.c
|@@ -3629,6 +3629,19 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
| goto err_deinit_irq;
| }
|
|+ if (hw_rev == ATH10K_HW_QCA988X) {
|+ /* v1 can crash the system on chip_reset()
|+ * so all we can do is keep our fingers
|+ * crossed v2 never reports 0 without a
|+ * chip_reset()
|+ */
|+ if (ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS) == 0) {
|+ ath10k_err(ar, "qca9880 v1 is chip not supported");
|+ ret = -ENOTSUP;
|+ goto err_free_irq;
|+ }
|+ }
|+
| ret = ath10k_pci_chip_reset(ar);
| if (ret) {
| ath10k_err(ar, "failed to reset chip: %d\n", ret);
|
|I didn't test it. Someone needs to compile and test and make sure v2
|doesn't regress when fw hangs and cold & warm host cpu resets are
|mixed in.
I do hope this helped "to clear things up" since I did not add support
for the QCA9880 v1 AR1A here and don't plan to do so.
Regards,
Christian
Christian Lamparter <[email protected]> writes:
> On Tuesday, September 17, 2019 8:44:12 AM CEST Kalle Valo wrote:
>> Christian Lamparter <[email protected]> wrote:
>>
>> > This patch restores the old behavior that read
>> > the chip_id on the QCA988x before resetting the
>> > chip. This needs to be done in this order since
>> > the unsupported QCA988x AR1A chips fall off the
>> > bus when resetted. Otherwise the next MMIO Op
>> > after the reset causes a BUS ERROR and panic.
>> >
>> > Cc: [email protected]
>> > Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
>> > Signed-off-by: Christian Lamparter <[email protected]>
>>
>> I'll drop this as there's no plan to support QCA988X hw1.0.
>
> Kalle,
>
> I'm surprised about this. And your justification "no plan to support
> QCA988X hw1.0" seems very odd in this context, because this patch does
> not add any support for the QCA988X hw1.0.
No wonder my comment was odd, it seems I had completely misunderstood :)
I assumed this is for preparation in adding QCA988X hw1.0 support, which
is clearly wrong.
> But, I could see how the mails/replies from Tom Psyborg derailed the
> topic here. Though, I'm not sure if this is the case or not.
>
> So let set the record straight and show you the result of having that
> patch applied and load ath10k_pci with a QCA9880 v1 AR1A:
>
> [ 1491.622282] ath10k_pci 0000:00:00.0: device 003c with chip_id
> 043200ff isn't supported
>
> (System is all good!)
>
> And without the patch:
>
> [ 900.320000] Data bus error, epc == 86a9a1b0, ra == 86a9a4b0
[...]
> Notice the DATA BUS Error! The router is unusable at that point and no
> longer "working".
Thanks, this clear for me now. I added this back to my queue and clarify
the commit log a bit.
--
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
Hey Lamperter, I'm sorry if you feel like I hijacked this thread but
it was in an obvious attempt to prove more can be done than just
returning unsupported message.
However, as the company itself is unwilling to provide firmware and
everybody mention this chip variant in such a negative context there
are obviously some internal reasons to keep it unsupported with
silicon bug or two being used as an excuse. Most chips have some hw
bugs and workarounds for the same are available, but this didn't
result in dropping support for their drivers. So, you can go with this
change, but it won't be that useful or required as few others who
switch to different card in their router won't need it. For the rest
of us 700Mbps with factory TP-Link firmware will suffice.
Christian Lamparter <[email protected]> wrote:
> This patch restores the old behavior that read
> the chip_id on the QCA988x before resetting the
> chip. This needs to be done in this order since
> the unsupported QCA988x AR1A chips fall off the
> bus when resetted. Otherwise the next MMIO Op
> after the reset causes a BUS ERROR and panic.
>
> Cc: [email protected]
> Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe")
> Signed-off-by: Christian Lamparter <[email protected]>
> Signed-off-by: Kalle Valo <[email protected]>
Patch applied to ath-next branch of ath.git, thanks.
f8914a14623a ath10k: restore QCA9880-AR1A (v1) detection
--
https://patchwork.kernel.org/patch/11136089/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches