2014-11-06 05:21:00

by Sujith Manoharan

Subject: [PATCH v2] ath9k: Fix RTC_DERIVED_CLK usage

From: Miaoqing Pan <[email protected]>

Based on the reference clock, which could be 25MHz or 40MHz,
AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
But, when a chip reset is done, processing the initvals
sets the register back to the default value.

Fix this by moving the code in ath9k_hw_init_pll() to
ar9003_hw_override_ini(). Also, do this override for AR9531.

Cc: [email protected]
Signed-off-by: Miaoqing Pan <[email protected]>
Signed-off-by: Sujith Manoharan <[email protected]>
---
v2 - Fix author address.

drivers/net/wireless/ath/ath9k/ar9003_phy.c | 13 +++++++++++++
drivers/net/wireless/ath/ath9k/hw.c | 13 -------------
2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 9bdaa0a..2df6d2e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struct ath_hw *ah)
ah->enabled_cals |= TX_CL_CAL;
else
ah->enabled_cals &= ~TX_CL_CAL;
+
+ if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
+ if (ah->is_clk_25mhz) {
+ REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
+ REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
+ REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
+ } else {
+ REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
+ REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
+ REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
+ }
+ udelay(100);
+ }
}

static void ar9003_hw_prog_ini(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index ee9fb52..04ae1f8 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
udelay(RTC_PLL_SETTLE_DELAY);

REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
-
- if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
- if (ah->is_clk_25mhz) {
- REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
- REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
- REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
- } else {
- REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
- REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
- REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
- }
- udelay(100);
- }
}

static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
--
2.1.3

2014-11-06 20:45:13

by John W. Linville

Subject: Re: [PATCH v2] ath9k: Fix RTC_DERIVED_CLK usage

On Thu, Nov 06, 2014 at 10:52:23AM +0530, Sujith Manoharan wrote:
> From: Miaoqing Pan <[email protected]>
>
> Based on the reference clock, which could be 25MHz or 40MHz,
> AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
> But, when a chip reset is done, processing the initvals
> sets the register back to the default value.
>
> Fix this by moving the code in ath9k_hw_init_pll() to
> ar9003_hw_override_ini(). Also, do this override for AR9531.

What is the effect of having the clock programmed incorrectly?


> Cc: [email protected]
> Signed-off-by: Miaoqing Pan <[email protected]>
> Signed-off-by: Sujith Manoharan <[email protected]>
> ---
> v2 - Fix author address.
>
> drivers/net/wireless/ath/ath9k/ar9003_phy.c | 13 +++++++++++++
> drivers/net/wireless/ath/ath9k/hw.c | 13 -------------
> 2 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> index 9bdaa0a..2df6d2e 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> @@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struct ath_hw *ah)
> ah->enabled_cals |= TX_CL_CAL;
> else
> ah->enabled_cals &= ~TX_CL_CAL;
> +
> + if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
> + if (ah->is_clk_25mhz) {
> + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
> + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
> + REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
> + } else {
> + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
> + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
> + REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
> + }
> + udelay(100);
> + }
> }
>
> static void ar9003_hw_prog_ini(struct ath_hw *ah,
> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
> index ee9fb52..04ae1f8 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
> udelay(RTC_PLL_SETTLE_DELAY);
>
> REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
> -
> - if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
> - if (ah->is_clk_25mhz) {
> - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
> - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
> - REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
> - } else {
> - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
> - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
> - REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
> - }
> - udelay(100);
> - }
> }
>
> static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
> --
> 2.1.3
>
>

--
John W. Linville Someday the world will need a hero, and you
[email protected] might be all we have. Be ready.

2014-11-07 01:27:19

by Pan, Miaoqing

Subject: RE: [PATCH v2] ath9k: Fix RTC_DERIVED_CLK usage

It will cause TSF not accurate, the result is beacon interval not equal to the real time.

Thanks,
Miaoqing

-----Original Message-----
From: John W. Linville [mailto:[email protected]]
Sent: Friday, November 07, 2014 4:42 AM
To: [email protected]
Cc: [email protected]; ath9k-devel; [email protected]
Subject: Re: [PATCH v2] ath9k: Fix RTC_DERIVED_CLK usage

On Thu, Nov 06, 2014 at 10:52:23AM +0530, Sujith Manoharan wrote:
> From: Miaoqing Pan <[email protected]>
>
> Based on the reference clock, which could be 25MHz or 40MHz,
> AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550.
> But, when a chip reset is done, processing the initvals sets the
> register back to the default value.
>
> Fix this by moving the code in ath9k_hw_init_pll() to
> ar9003_hw_override_ini(). Also, do this override for AR9531.

What is the effect of having the clock programmed incorrectly?


> Cc: [email protected]
> Signed-off-by: Miaoqing Pan <[email protected]>
> Signed-off-by: Sujith Manoharan <[email protected]>
> ---
> v2 - Fix author address.
>
> drivers/net/wireless/ath/ath9k/ar9003_phy.c | 13 +++++++++++++
> drivers/net/wireless/ath/ath9k/hw.c | 13 -------------
> 2 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> index 9bdaa0a..2df6d2e 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> @@ -664,6 +664,19 @@ static void ar9003_hw_override_ini(struct ath_hw *ah)
> ah->enabled_cals |= TX_CL_CAL;
> else
> ah->enabled_cals &= ~TX_CL_CAL;
> +
> + if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
> + if (ah->is_clk_25mhz) {
> + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
> + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
> + REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
> + } else {
> + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
> + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
> + REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
> + }
> + udelay(100);
> + }
> }
>
> static void ar9003_hw_prog_ini(struct ath_hw *ah, diff --git
> a/drivers/net/wireless/ath/ath9k/hw.c
> b/drivers/net/wireless/ath/ath9k/hw.c
> index ee9fb52..04ae1f8 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -870,19 +870,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
> udelay(RTC_PLL_SETTLE_DELAY);
>
> REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
> -
> - if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
> - if (ah->is_clk_25mhz) {
> - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
> - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
> - REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
> - } else {
> - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
> - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
> - REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
> - }
> - udelay(100);
> - }
> }
>
> static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
> --
> 2.1.3
>
>

--
John W. Linville Someday the world will need a hero, and you
[email protected] might be all we have. Be ready.