* Set BB_tpc_1.enable_pd_calibrate to 0
* Set BB_cl_cal_ctrl.enable_parallel_cal to 1
* Enable "enable_dac_async_fifo" and "enable_adc_async_fifo"
to fix some dac/adc timing issue,
e.g. EVM won't degrade when setting core voltage to 1.15V.
Set BB_gen_controls.enable_dac_async_fifo=1
Set BB_gen_controls.enable_adc_async_fifo=1
* Improve LNA2 Sensitivity ~1dB
Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 = 1
* Correct alternate chain RSSI when doing diversity
Set BB_bbb_sig_detect.ant_switch_time to 63
* Refer to RACK RX gain report and modify RF gain table for LNA2
* Invert the phase of the root of both clocks
(setting flip_pllclk320 = 1) and set inv_clk320_adc back = 0.
Set ch0_PLLCLKMODA2WLAN.flip_pllclk320 to 1
Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 to 0
* Remove MAC PCU registers MAC_PCU_TSF_L32/MAC_PCU_TSF_U32.
Signed-off-by: Sujith Manoharan <[email protected]>
---
tools/initvals/ar9565_1p0_initvals.h | 100 +++++++++++++++++------------------
1 file changed, 49 insertions(+), 51 deletions(-)
diff --git a/tools/initvals/ar9565_1p0_initvals.h b/tools/initvals/ar9565_1p0_initvals.h
index fa9e093..843e79f 100644
--- a/tools/initvals/ar9565_1p0_initvals.h
+++ b/tools/initvals/ar9565_1p0_initvals.h
@@ -58,8 +58,6 @@ static const u32 ar9565_1p0_mac_core[][2] = {
{0x00008040, 0x00000000},
{0x00008044, 0x00000000},
{0x00008048, 0x00000000},
- {0x0000804c, 0xffffffff},
- {0x00008050, 0xffffffff},
{0x00008054, 0x00000000},
{0x00008058, 0x00000000},
{0x0000805c, 0x000fc78f},
@@ -246,7 +244,7 @@ static const u32 ar9565_1p0_baseband_core[][2] = {
{0x00009e50, 0x00ff03f1},
{0x00009e54, 0xe4c355c7},
{0x00009e5c, 0xe9198724},
- {0x00009fc0, 0x823e4788},
+ {0x00009fc0, 0x823e4fc8},
{0x00009fc4, 0x0001efb5},
{0x00009fcc, 0x40000014},
{0x0000a20c, 0x00000000},
@@ -291,7 +289,7 @@ static const u32 ar9565_1p0_baseband_core[][2] = {
{0x0000a3ec, 0x20202020},
{0x0000a3f0, 0x00000000},
{0x0000a3f4, 0x00000006},
- {0x0000a3f8, 0x0cdbd380},
+ {0x0000a3f8, 0x0c9bd380},
{0x0000a3fc, 0x000f0f01},
{0x0000a400, 0x8fa91f01},
{0x0000a404, 0x00000000},
@@ -355,11 +353,11 @@ static const u32 ar9565_1p0_baseband_postamble[][5] = {
{0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
{0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
{0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
- {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
+ {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
{0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
{0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
{0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
- {0x0000a204, 0x033187c0, 0x033187c4, 0x033187c4, 0x033187c0},
+ {0x0000a204, 0x07318fc0, 0x07318fc4, 0x07318fc4, 0x07318fc0},
{0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
{0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f},
{0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
@@ -375,9 +373,9 @@ static const u32 ar9565_1p0_baseband_postamble[][5] = {
{0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
{0x0000a288, 0x00100510, 0x00100510, 0x00100510, 0x00100510},
{0x0000a28c, 0x00021551, 0x00021551, 0x00021551, 0x00021551},
- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+ {0x0000a2c4, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18},
{0x0000a2d0, 0x00071982, 0x00071982, 0x00071982, 0x00071982},
- {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
{0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
{0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -417,7 +415,7 @@ static const u32 ar9565_1p0_radio_core[][2] = {
{0x00016144, 0x02084080},
{0x00016148, 0x000080c0},
{0x00016280, 0x050a0001},
- {0x00016284, 0x3d841400},
+ {0x00016284, 0x3d841440},
{0x00016288, 0x00000000},
{0x0001628c, 0xe3000000},
{0x00016290, 0xa1004080},
@@ -840,27 +838,27 @@ static const u32 ar9565_1p0_common_wo_xlna_rx_gain_table[][2] = {
{0x0000a0b4, 0x00000000},
{0x0000a0b8, 0x00000000},
{0x0000a0bc, 0x00000000},
- {0x0000a0c0, 0x301f3000},
- {0x0000a0c4, 0x41004101},
- {0x0000a0c8, 0x411e411f},
- {0x0000a0cc, 0x411c411d},
- {0x0000a0d0, 0x42434244},
- {0x0000a0d4, 0x42414242},
- {0x0000a0d8, 0x425f4240},
- {0x0000a0dc, 0x5342425e},
- {0x0000a0e0, 0x53405341},
- {0x0000a0e4, 0x535e535f},
- {0x0000a0e8, 0x7402535d},
- {0x0000a0ec, 0x74007401},
- {0x0000a0f0, 0x741e741f},
- {0x0000a0f4, 0x7522741d},
- {0x0000a0f8, 0x75207521},
- {0x0000a0fc, 0x753e753f},
- {0x0000a100, 0x76617662},
- {0x0000a104, 0x767f7660},
- {0x0000a108, 0x767d767e},
- {0x0000a10c, 0x77e277e3},
- {0x0000a110, 0x77e077e1},
+ {0x0000a0c0, 0x00bf00a0},
+ {0x0000a0c4, 0x11a011a1},
+ {0x0000a0c8, 0x11be11bf},
+ {0x0000a0cc, 0x11bc11bd},
+ {0x0000a0d0, 0x22632264},
+ {0x0000a0d4, 0x22612262},
+ {0x0000a0d8, 0x227f2260},
+ {0x0000a0dc, 0x4322227e},
+ {0x0000a0e0, 0x43204321},
+ {0x0000a0e4, 0x433e433f},
+ {0x0000a0e8, 0x4462433d},
+ {0x0000a0ec, 0x44604461},
+ {0x0000a0f0, 0x447e447f},
+ {0x0000a0f4, 0x5582447d},
+ {0x0000a0f8, 0x55805581},
+ {0x0000a0fc, 0x559e559f},
+ {0x0000a100, 0x66816682},
+ {0x0000a104, 0x669f6680},
+ {0x0000a108, 0x669d669e},
+ {0x0000a10c, 0x77627763},
+ {0x0000a110, 0x77607761},
{0x0000a114, 0x00000000},
{0x0000a118, 0x00000000},
{0x0000a11c, 0x00000000},
@@ -872,27 +870,27 @@ static const u32 ar9565_1p0_common_wo_xlna_rx_gain_table[][2] = {
{0x0000a134, 0x00000000},
{0x0000a138, 0x00000000},
{0x0000a13c, 0x00000000},
- {0x0000a140, 0x301f3000},
- {0x0000a144, 0x41004101},
- {0x0000a148, 0x411e411f},
- {0x0000a14c, 0x411c411d},
- {0x0000a150, 0x42434244},
- {0x0000a154, 0x42414242},
- {0x0000a158, 0x425f4240},
- {0x0000a15c, 0x5342425e},
- {0x0000a160, 0x53405341},
- {0x0000a164, 0x535e535f},
- {0x0000a168, 0x7402535d},
- {0x0000a16c, 0x74007401},
- {0x0000a170, 0x741e741f},
- {0x0000a174, 0x7522741d},
- {0x0000a178, 0x75207521},
- {0x0000a17c, 0x753e753f},
- {0x0000a180, 0x76617662},
- {0x0000a184, 0x767f7660},
- {0x0000a188, 0x767d767e},
- {0x0000a18c, 0x77e277e3},
- {0x0000a190, 0x77e077e1},
+ {0x0000a140, 0x00bf00a0},
+ {0x0000a144, 0x11a011a1},
+ {0x0000a148, 0x11be11bf},
+ {0x0000a14c, 0x11bc11bd},
+ {0x0000a150, 0x22632264},
+ {0x0000a154, 0x22612262},
+ {0x0000a158, 0x227f2260},
+ {0x0000a15c, 0x4322227e},
+ {0x0000a160, 0x43204321},
+ {0x0000a164, 0x433e433f},
+ {0x0000a168, 0x4462433d},
+ {0x0000a16c, 0x44604461},
+ {0x0000a170, 0x447e447f},
+ {0x0000a174, 0x5582447d},
+ {0x0000a178, 0x55805581},
+ {0x0000a17c, 0x559e559f},
+ {0x0000a180, 0x66816682},
+ {0x0000a184, 0x669f6680},
+ {0x0000a188, 0x669d669e},
+ {0x0000a18c, 0x77627763},
+ {0x0000a190, 0x77607761},
{0x0000a194, 0x00000000},
{0x0000a198, 0x00000000},
{0x0000a19c, 0x00000000},
--
1.7.12
On Tue, Sep 11, 2012 at 11:28 PM, Sujith Manoharan
<[email protected]> wrote:
> * Set BB_tpc_1.enable_pd_calibrate to 0
>
> * Set BB_cl_cal_ctrl.enable_parallel_cal to 1
>
> * Enable "enable_dac_async_fifo" and "enable_adc_async_fifo"
> to fix some dac/adc timing issue,
> e.g. EVM won't degrade when setting core voltage to 1.15V.
>
> Set BB_gen_controls.enable_dac_async_fifo=1
> Set BB_gen_controls.enable_adc_async_fifo=1
>
> * Improve LNA2 Sensitivity ~1dB
> Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 = 1
>
> * Correct alternate chain RSSI when doing diversity
> Set BB_bbb_sig_detect.ant_switch_time to 63
>
> * Refer to RACK RX gain report and modify RF gain table for LNA2
>
> * Invert the phase of the root of both clocks
> (setting flip_pllclk320 = 1) and set inv_clk320_adc back = 0.
>
> Set ch0_PLLCLKMODA2WLAN.flip_pllclk320 to 1
> Set ch0_PLLCLKMODA2WLAN.inv_clk320_adc_ch0 to 0
>
> * Remove MAC PCU registers MAC_PCU_TSF_L32/MAC_PCU_TSF_U32.
>
> Signed-off-by: Sujith Manoharan <[email protected]>
thanks, applied and pushed both patches, sorry for the delay in
applying the other patch.
Luis