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Kishon Vijay Abraham I (
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Number of posts: 4392 (2.23 per day)
First post: 2012-05-30 10:56:58
Last post: 2017-10-24 06:19:00
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2021-03-08 08:44:20
linux-kernel
[PATCH v4 0/4] AM64: Add PCIe bindings and driver support
2021-03-08 08:44:18
linux-kernel
[PATCH v5 10/13] phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback
2021-03-08 08:44:15
linux-kernel
[PATCH v5 06/13] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function
2021-03-08 08:42:45
linux-kernel
[PATCH v5 13/13] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
2021-03-08 08:42:30
linux-kernel
[PATCH v5 11/13] dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider
2021-03-08 08:42:26
linux-kernel
[PATCH v5 09/13] phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy"
2021-03-08 08:42:25
linux-kernel
[PATCH v5 08/13] phy: cadence-torrent: Use a common header file for Cadence SERDES
2021-03-08 08:42:24
linux-kernel
[PATCH v5 01/13] phy: cadence: Sierra: Fix PHY power_on sequence
2021-03-08 08:42:20
linux-kernel
[PATCH v5 07/13] phy: cadence: cadence-sierra: Explicitly request exclusive reset control
2021-03-08 08:42:17
linux-kernel
[PATCH v5 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function
2021-03-08 08:42:16
linux-kernel
[PATCH v5 04/13] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode
2021-03-08 08:42:16
linux-kernel
[PATCH v5 03/13] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes
2021-03-08 08:42:16
linux-kernel
[PATCH v5 02/13] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()
2021-03-08 08:42:13
linux-kernel
[PATCH v5 00/13] PHY: Add support in Sierra to use external clock
2021-03-08 08:41:47
linux-kernel
Re: [PATCH v4 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
2021-03-05 05:08:35
linux-kernel
[PATCH v3 6/7] misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device
2021-03-05 05:07:18
linux-kernel
[PATCH v3 5/7] PCI: cadence: Add support to configure virtual functions
2021-03-05 05:07:02
linux-kernel
[PATCH v3 3/7] PCI: endpoint: Add support to link a physical function to a virtual function
2021-03-05 05:06:52
linux-kernel
[PATCH v3 7/7] Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV
2021-03-05 05:06:07
linux-kernel
[PATCH v3 4/7] PCI: endpoint: Add virtual function number in pci_epc ops
2021-03-05 05:05:57
linux-kernel
[PATCH v3 0/7] Add SR-IOV support in PCIe Endpoint Core
2021-03-05 05:05:55
linux-kernel
[PATCH v3 2/7] PCI: endpoint: Add support to add virtual function in endpoint core
2021-03-05 05:05:52
linux-kernel
[PATCH v3 1/7] dt-bindings: PCI: pci-ep: Add binding to specify virtual function
2021-03-05 03:00:56
linux-kernel
[PATCH] PCI: designware-ep: Fix NULL pointer dereference error
2021-03-05 00:02:57
linux-kernel
[PATCH v4 08/13] phy: cadence-torrent: Use a common header file for Cadence SERDES
2021-03-05 00:02:54
linux-kernel
[PATCH v4 03/13] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes
2021-03-05 00:02:29
linux-kernel
Re: [PATCH v2 1/9] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper
2021-03-05 00:02:21
linux-kernel
[PATCH v4 01/13] phy: cadence: Sierra: Fix PHY power_on sequence
2021-03-05 00:02:02
linux-kernel
[PATCH v4 07/13] phy: cadence: cadence-sierra: Explicitly request exclusive reset control
2021-03-05 00:02:02
linux-kernel
[PATCH v4 09/13] phy: cadence: cadence-sierra: Add array of input clocks in "struct cdns_sierra_phy"
2021-03-04 14:51:26
linux-kernel
[PATCH v4 11/13] dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock provider
2021-03-04 14:51:23
linux-kernel
[PATCH v4 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
2021-03-04 14:48:36
linux-kernel
[PATCH v4 04/13] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode
2021-03-04 14:48:32
linux-kernel
[PATCH v4 02/13] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()
2021-03-04 14:48:25
linux-kernel
[PATCH v4 13/13] phy: cadence: phy-cadence-sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
2021-03-04 14:48:09
linux-kernel
[PATCH v4 06/13] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function
2021-03-04 14:48:08
linux-kernel
[PATCH v4 00/13] PHY: Add support in Sierra to use external clock
2021-03-04 14:47:45
linux-kernel
[PATCH v4 10/13] phy: cadence: cadence-sierra: Add missing clk_disable_unprepare() in .remove callback
2021-03-04 14:47:09
linux-kernel
[PATCH v4 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function
2021-03-01 06:09:38
linux-kernel
Re: [PATCH] arm64: dts: ti: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems
2021-02-23 12:25:20
linux-kernel
Re: [PATCH v15 2/4] phy: Add media type and speed serdes configuration interfaces
2021-02-22 11:45:48
linux-kernel
[PATCH v3 0/4] AM64: Add PCIe bindings and driver support
2021-02-22 11:45:42
linux-kernel
[PATCH v3 4/4] PCI: j721e: Add support to provide refclk to PCIe connector
2021-02-22 11:45:25
linux-kernel
[PATCH v3 3/4] dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
2021-02-22 11:42:46
linux-kernel
[PATCH v3 2/4] dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC
2021-02-22 11:42:32
linux-kernel
[PATCH v3 1/4] dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector
2021-02-22 11:31:04
linux-kernel
[PATCH v2 7/9] phy: ti: j721e-wiz: Model the internal clocks without device tree input
2021-02-22 11:29:16
linux-kernel
[PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out
2021-02-22 11:29:03
linux-kernel
[PATCH v2 5/9] phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup
2021-02-22 11:29:00
linux-kernel
[PATCH v2 8/9] phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>
2021-02-22 11:28:52
linux-kernel
[PATCH v2 6/9] phy: ti: j721e-wiz: Configure full rate divider for AM64