AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't
have a clock generator (unlike J7200 base board). Here the clock from
the SERDES has to be routed to the PCIE connector. This series adds
support to drive reference clock output from SERDES and also adds
SERDES (torrent) and SERDES wrapper (WIZ) bindings.
v1 of the patch series can be found @ [1]
Changes from v1:
*) Model the internal clocks without device tree input (Add #clock-cells
to SERDES DT nodes for getting a reference to the clock using index
to phandle). This is in accordance with comment given by Rob [2].
However the existing method to model clocks from device tree is not
removed to support upstreamed device tree.
*) Included a patch to fix modifying static data by instance specific
initializations.
*) Added a fix to delete "clk_div_sel" clk provider during cleanup
[1] -> https://lore.kernel.org/r/[email protected]
[2] -> http://lore.kernel.org/r/[email protected]
Kishon Vijay Abraham I (9):
dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES
Wrapper
dt-bindings: phy: cadence-torrent: Add binding for refclk driver
dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel
phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup
phy: ti: j721e-wiz: Configure full rate divider for AM64
phy: ti: j721e-wiz: Model the internal clocks without device tree
input
phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>
phy: cadence-torrent: Add support to drive refclk out
.../bindings/phy/phy-cadence-torrent.yaml | 20 +-
.../bindings/phy/ti,phy-j721e-wiz.yaml | 10 +-
drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++-
drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++---
include/dt-bindings/mux/ti-serdes.h | 5 +
include/dt-bindings/phy/phy-cadence-torrent.h | 2 +
include/dt-bindings/phy/phy-ti.h | 21 ++
7 files changed, 553 insertions(+), 56 deletions(-)
create mode 100644 include/dt-bindings/phy/phy-ti.h
--
2.17.1
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 39 +++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 1a4e09a394a8..2706e7be0c28 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -101,6 +101,13 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 24, 25),
};
+static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 22, 23),
+ REG_FIELD(WIZ_LANECTL(1), 22, 23),
+ REG_FIELD(WIZ_LANECTL(2), 22, 23),
+ REG_FIELD(WIZ_LANECTL(3), 22, 23),
+};
+
static const struct reg_field typec_ln10_swap =
REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
@@ -191,6 +198,7 @@ static const struct wiz_clk_div_sel clk_div_sel[] = {
enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
+ AM64_WIZ_10G,
};
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
@@ -208,6 +216,7 @@ struct wiz {
struct regmap_field *p_align[WIZ_MAX_LANES];
struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
+ struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
@@ -373,7 +382,7 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
}
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->mux_sel_field[REFCLK_DIG] =
devm_regmap_field_alloc(dev, regmap,
refclk_dig_sel_10g);
@@ -417,6 +426,12 @@ static int wiz_regfield_init(struct wiz *wiz)
i);
return PTR_ERR(wiz->p_standard_mode[i]);
}
+
+ wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
+ if (IS_ERR(wiz->p0_fullrt_div[i])) {
+ dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_fullrt_div[i]);
+ }
}
wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
@@ -718,6 +733,17 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
return ret;
}
+static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
+{
+ if (wiz->type != AM64_WIZ_10G)
+ return 0;
+
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+
+ return 0;
+}
+
static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
@@ -741,6 +767,10 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
return ret;
}
+ ret = wiz_phy_fullrt_div(wiz, id - 1);
+ if (ret)
+ return ret;
+
if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
@@ -768,6 +798,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
},
+ {
+ .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
+ },
{}
};
MODULE_DEVICE_TABLE(of, wiz_id_table);
@@ -899,14 +932,14 @@ static int wiz_probe(struct platform_device *pdev)
wiz->dev = dev;
wiz->regmap = regmap;
wiz->num_lanes = num_lanes;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_mux_sel = clk_mux_sel_10g;
else
wiz->clk_mux_sel = clk_mux_sel_16g;
wiz->clk_div_sel = clk_div_sel;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
else
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
--
2.17.1
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. In order to drive the refclk out from the SERDES
(Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ.
Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can
enable it.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 89 ++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index f9299dcdbdb7..03896240a5d5 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -66,6 +66,7 @@ enum wiz_clock_input {
static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
+static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
static const struct reg_field pll1_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 29, 29);
static const struct reg_field pll0_refclk_mux_sel =
@@ -86,6 +87,7 @@ static const char * const output_clk_names[] = {
[TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
[TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
[TI_WIZ_REFCLK_DIG] = "refclk-dig",
+ [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
};
static const struct reg_field p_enable[WIZ_MAX_LANES] = {
@@ -158,6 +160,14 @@ struct wiz_clk_div_sel {
const char *node_name;
};
+struct wiz_phy_en_refclk {
+ struct clk_hw hw;
+ struct regmap_field *phy_en_refclk;
+ struct clk_init_data clk_data;
+};
+
+#define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
+
static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
{
/*
@@ -237,6 +247,7 @@ struct wiz {
unsigned int clk_div_sel_num;
struct regmap_field *por_en;
struct regmap_field *phy_reset_n;
+ struct regmap_field *phy_en_refclk;
struct regmap_field *p_enable[WIZ_MAX_LANES];
struct regmap_field *p_align[WIZ_MAX_LANES];
struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
@@ -469,6 +480,76 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->typec_ln10_swap);
}
+ wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
+ if (IS_ERR(wiz->phy_en_refclk)) {
+ dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
+ return PTR_ERR(wiz->phy_en_refclk);
+ }
+
+ return 0;
+}
+
+static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+
+ regmap_field_write(phy_en_refclk, 1);
+
+ return 0;
+}
+
+static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+
+ regmap_field_write(phy_en_refclk, 0);
+}
+
+static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+ int val;
+
+ regmap_field_read(phy_en_refclk, &val);
+
+ return !!val;
+}
+
+static const struct clk_ops wiz_phy_en_refclk_ops = {
+ .enable = wiz_phy_en_refclk_enable,
+ .disable = wiz_phy_en_refclk_disable,
+ .is_enabled = wiz_phy_en_refclk_is_enabled,
+};
+
+static int wiz_phy_en_refclk_register(struct wiz *wiz)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk;
+ struct device *dev = wiz->dev;
+ struct clk_init_data *init;
+ struct clk *clk;
+
+ wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
+ if (!wiz_phy_en_refclk)
+ return -ENOMEM;
+
+ init = &wiz_phy_en_refclk->clk_data;
+
+ init->ops = &wiz_phy_en_refclk_ops;
+ init->flags = 0;
+ init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK];
+
+ wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
+ wiz_phy_en_refclk->hw.init = init;
+
+ clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
+
return 0;
}
@@ -724,6 +805,8 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
of_clk_del_provider(clk_node);
of_node_put(clk_node);
}
+
+ of_clk_del_provider(wiz->dev->of_node);
}
static int wiz_clock_register(struct wiz *wiz)
@@ -747,6 +830,12 @@ static int wiz_clock_register(struct wiz *wiz)
}
}
+ ret = wiz_phy_en_refclk_register(wiz);
+ if (ret) {
+ dev_err(dev, "Failed to add phy-en-refclk\n");
+ return ret;
+ }
+
wiz->clk_data.clks = wiz->output_clks;
wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
--
2.17.1
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module
present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in
wiz. However during cleanup, it removed only the MUX clock provider.
Remove the DIVIDER clock provider here.
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 956a93d96d9b..1a4e09a394a8 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -608,6 +608,12 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
of_clk_del_provider(clk_node);
of_node_put(clk_node);
}
+
+ for (i = 0; i < wiz->clk_div_sel_num; i++) {
+ clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
+ of_clk_del_provider(clk_node);
+ of_node_put(clk_node);
+ }
}
static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
--
2.17.1
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_<p/m> can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++++++++++++++-
1 file changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index f310e15d94cb..07eebdd90d4b 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -7,7 +7,9 @@
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence-torrent.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
@@ -76,6 +78,8 @@
* register offsets from SD0801 PHY register block base (i.e MHDP
* register base + 0x500000)
*/
+#define CMN_CDIAG_REFCLK_OVRD 0x004CU
+#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
#define CMN_SSM_BANDGAP_TMR 0x0021U
#define CMN_SSM_BIAS_TMR 0x0022U
#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
@@ -206,6 +210,8 @@
#define RX_DIAG_ACYA 0x01FFU
/* PHY PCS common registers */
+#define PHY_PIPE_CMN_CTRL1 0x0000U
+#define PHY_ISO_CMN_CTRL 0x0008U
#define PHY_PLL_CFG 0x000EU
#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
@@ -216,6 +222,10 @@
#define PHY_PMA_CMN_CTRL2 0x0001U
#define PHY_PMA_PLL_RAW_CTRL 0x0003U
+static const char * const clk_names[] = {
+ [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
+};
+
static const struct reg_field phy_pll_cfg =
REG_FIELD(PHY_PLL_CFG, 0, 1);
@@ -231,6 +241,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
static const struct reg_field phy_reset_ctrl =
REG_FIELD(PHY_RESET, 8, 8);
+#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
+
+enum cdns_torrent_refclk_out_pcs {
+ PHY_ISO_CMN_CTRL_8,
+ PHY_PIPE_CMN_CTRL1_0,
+};
+
+#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
+
+enum cdns_torrent_refclk_out_cmn {
+ CMN_CDIAG_REFCLK_OVRD_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_1,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_5,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_6,
+};
+
+static const struct reg_field refclk_out_pcs_cfg[] = {
+ [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8, 8),
+ [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0),
+};
+
+static const struct reg_field refclk_out_cmn_cfg[] = {
+ [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
+};
+
enum cdns_torrent_phy_type {
TYPE_NONE,
TYPE_DP,
@@ -279,6 +319,8 @@ struct cdns_torrent_phy {
struct regmap_field *phy_pma_cmn_ctrl_2;
struct regmap_field *phy_pma_pll_raw_ctrl;
struct regmap_field *phy_reset_ctrl;
+ struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
+ struct clk_onecell_data clk_data;
};
enum phy_powerstate {
@@ -288,6 +330,16 @@ enum phy_powerstate {
POWERSTATE_A3 = 3,
};
+struct cdns_torrent_derived_refclk {
+ struct clk_hw hw;
+ struct regmap_field *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
+ struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
+ struct clk_init_data clk_data;
+};
+
+#define to_cdns_torrent_derived_refclk(_hw) \
+ container_of(_hw, struct cdns_torrent_derived_refclk, hw)
+
static int cdns_torrent_phy_init(struct phy *phy);
static int cdns_torrent_dp_init(struct phy *phy);
static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
@@ -1604,6 +1656,111 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
return ret;
}
+static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
+
+ return 0;
+}
+
+static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
+}
+
+static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
+ int val;
+
+ regmap_field_read(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], &val);
+
+ return !!val;
+}
+
+static const struct clk_ops cdns_torrent_derived_refclk_ops = {
+ .enable = cdns_torrent_derived_refclk_enable,
+ .disable = cdns_torrent_derived_refclk_disable,
+ .is_enabled = cdns_torrent_derived_refclk_is_enabled,
+};
+
+static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk;
+ struct device *dev = cdns_phy->dev;
+ struct regmap_field *field;
+ struct clk_init_data *init;
+ const char *parent_name;
+ struct regmap *regmap;
+ char clk_name[100];
+ struct clk *clk;
+ int i;
+
+ derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
+ if (!derived_refclk)
+ return -ENOMEM;
+
+ snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
+ clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
+
+ clk = devm_clk_get_optional(dev, "phy_en_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "No parent clock for derived_refclk\n");
+ return PTR_ERR(clk);
+ }
+
+ init = &derived_refclk->clk_data;
+
+ if (clk) {
+ parent_name = __clk_get_name(clk);
+ init->parent_names = &parent_name;
+ init->num_parents = 1;
+ }
+ init->ops = &cdns_torrent_derived_refclk_ops;
+ init->flags = 0;
+ init->name = clk_name;
+
+ regmap = cdns_phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG; i++) {
+ field = devm_regmap_field_alloc(dev, regmap, refclk_out_pcs_cfg[i]);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PCS reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ derived_refclk->pcs_fields[i] = field;
+ }
+
+ regmap = cdns_phy->regmap_common_cdb;
+ for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG; i++) {
+ field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
+ if (IS_ERR(field)) {
+ dev_err(dev, "CMN reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ derived_refclk->cmn_fields[i] = field;
+ }
+
+ derived_refclk->hw.init = init;
+
+ clk = devm_clk_register(dev, &derived_refclk->hw);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] = clk;
+
+ return 0;
+}
+
static int cdns_torrent_phy_on(struct phy *phy)
{
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
@@ -2071,6 +2228,37 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
return 0;
}
+static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
+{
+ struct device *dev = cdns_phy->dev;
+
+ of_clk_del_provider(dev->of_node);
+}
+
+static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
+{
+ struct device *dev = cdns_phy->dev;
+ struct device_node *node = dev->of_node;
+ int ret;
+
+ ret = cdns_torrent_derived_refclk_register(cdns_phy);
+ if (ret) {
+ dev_err(dev, "failed to register derived refclk\n");
+ return ret;
+ }
+
+ cdns_phy->clk_data.clks = cdns_phy->clks;
+ cdns_phy->clk_data.clk_num = CDNS_TORRENT_REFCLK_DRIVER + 1;
+
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy->clk_data);
+ if (ret) {
+ dev_err(dev, "Failed to add clock provider: %s\n", node->name);
+ return ret;
+ }
+
+ return 0;
+}
+
static int cdns_torrent_phy_probe(struct platform_device *pdev)
{
struct cdns_torrent_phy *cdns_phy;
@@ -2134,17 +2322,21 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = cdns_torrent_clk_register(cdns_phy);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(cdns_phy->clk);
if (ret) {
dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
- return ret;
+ goto clk_cleanup;
}
cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
if (!(cdns_phy->ref_clk_rate)) {
dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
- clk_disable_unprepare(cdns_phy->clk);
- return -EINVAL;
+ ret = -EINVAL;
+ goto clk_disable;
}
/* Enable APB */
@@ -2322,7 +2514,10 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
reset_control_put(cdns_phy->phys[i].lnk_rst);
of_node_put(child);
reset_control_assert(cdns_phy->apb_rst);
+clk_disable:
clk_disable_unprepare(cdns_phy->clk);
+clk_cleanup:
+ cdns_torrent_clk_cleanup(cdns_phy);
return ret;
}
@@ -2339,6 +2534,7 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
}
clk_disable_unprepare(cdns_phy->clk);
+ cdns_torrent_clk_cleanup(cdns_phy);
return 0;
}
--
2.17.1
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module
present in TI J721E SoC") modeled the internal clocks depending on the
subnodes that are populated in device tree. However recent discussions
in the mailing list [1] suggested to just add #clock cells in the parent
DT node and model the clocks within the driver.
Model the mux clocks without device tree input for AM64x SoC. Don't
remove the earlier design since DT nodes for J7200 and J721e are already
upstreamed.
[1] -> http://lore.kernel.org/r/[email protected]
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 144 +++++++++++++++++++++++++++++++--
1 file changed, 139 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2706e7be0c28..f9299dcdbdb7 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/gpio.h>
@@ -27,6 +28,10 @@
#define WIZ_SERDES_TYPEC 0x410
#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
+#define WIZ_MAX_INPUT_CLOCKS 4
+/* To include mux clocks, divider clocks and gate clocks */
+#define WIZ_MAX_OUTPUT_CLOCKS 32
+
#define WIZ_MAX_LANES 4
#define WIZ_MUX_NUM_CLOCKS 3
#define WIZ_DIV_NUM_CLOCKS_16G 2
@@ -52,6 +57,13 @@ enum wiz_refclk_div_sel {
CMN_REFCLK1_DIG_DIV,
};
+enum wiz_clock_input {
+ WIZ_CORE_REFCLK,
+ WIZ_EXT_REFCLK,
+ WIZ_CORE_REFCLK1,
+ WIZ_EXT_REFCLK1,
+};
+
static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
@@ -70,6 +82,11 @@ static const struct reg_field pma_cmn_refclk_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
static const struct reg_field pma_cmn_refclk1_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
+static const char * const output_clk_names[] = {
+ [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
+ [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
+ [TI_WIZ_REFCLK_DIG] = "refclk-dig",
+};
static const struct reg_field p_enable[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(0), 30, 31),
@@ -130,8 +147,10 @@ struct wiz_clk_divider {
#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
struct wiz_clk_mux_sel {
- u32 table[4];
+ u32 table[WIZ_MAX_INPUT_CLOCKS];
const char *node_name;
+ u32 num_parents;
+ u32 parents[WIZ_MAX_INPUT_CLOCKS];
};
struct wiz_clk_div_sel {
@@ -164,14 +183,20 @@ static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
* Mux value to be configured for each of the input clocks
* in the order populated in device tree
*/
+ .num_parents = 2,
+ .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
.table = { 1, 0 },
.node_name = "pll0-refclk",
},
{
+ .num_parents = 2,
+ .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
.table = { 1, 0 },
.node_name = "pll1-refclk",
},
{
+ .num_parents = 2,
+ .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
.table = { 1, 0 },
.node_name = "refclk-dig",
},
@@ -232,6 +257,9 @@ struct wiz {
struct gpio_desc *gpio_typec_dir;
int typec_dir_delay;
u32 lane_phy_type[WIZ_MAX_LANES];
+ struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
+ struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
+ struct clk_onecell_data clk_data;
};
static int wiz_reset(struct wiz *wiz)
@@ -469,8 +497,69 @@ static const struct clk_ops wiz_clk_mux_ops = {
.get_parent = wiz_clk_mux_get_parent,
};
-static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
- struct regmap_field *field, const u32 *table)
+static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
+ const struct wiz_clk_mux_sel *mux_sel, int clk_index)
+{
+ struct device *dev = wiz->dev;
+ struct clk_init_data *init;
+ const char **parent_names;
+ unsigned int num_parents;
+ struct wiz_clk_mux *mux;
+ char clk_name[100];
+ struct clk *clk;
+ int ret = 0, i;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ num_parents = mux_sel->num_parents;
+
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+ if (!parent_names)
+ return -ENOMEM;
+
+ for (i = 0; i < num_parents; i++) {
+ clk = wiz->input_clks[mux_sel->parents[i]];
+ if (IS_ERR_OR_NULL(clk)) {
+ dev_err(dev, "Failed to get parent clk for %s\n",
+ output_clk_names[clk_index]);
+ ret = -EINVAL;
+ goto err;
+ }
+ parent_names[i] = __clk_get_name(clk);
+ }
+
+ snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
+
+ init = &mux->clk_data;
+
+ init->ops = &wiz_clk_mux_ops;
+ init->flags = CLK_SET_RATE_NO_REPARENT;
+ init->parent_names = parent_names;
+ init->num_parents = num_parents;
+ init->name = clk_name;
+
+ mux->field = field;
+ mux->table = mux_sel->table;
+ mux->hw.init = init;
+
+ clk = devm_clk_register(dev, &mux->hw);
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ goto err;
+ }
+
+ wiz->output_clks[clk_index] = clk;
+
+err:
+ kfree(parent_names);
+
+ return ret;
+}
+
+static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
+ struct regmap_field *field, const u32 *table)
{
struct device *dev = wiz->dev;
struct clk_init_data *init;
@@ -615,9 +704,15 @@ static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
{
const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
+ struct device *dev = wiz->dev;
struct device_node *clk_node;
int i;
+ if (wiz->type == AM64_WIZ_10G) {
+ of_clk_del_provider(dev->of_node);
+ return;
+ }
+
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
of_clk_del_provider(clk_node);
@@ -631,6 +726,36 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
}
}
+static int wiz_clock_register(struct wiz *wiz)
+{
+ const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
+ struct device *dev = wiz->dev;
+ struct device_node *node = dev->of_node;
+ int clk_index;
+ int ret;
+ int i;
+
+ if (wiz->type != AM64_WIZ_10G)
+ return 0;
+
+ clk_index = TI_WIZ_PLL0_REFCLK;
+ for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
+ ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
+ if (ret) {
+ dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
+ return ret;
+ }
+ }
+
+ wiz->clk_data.clks = wiz->output_clks;
+ wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
+ ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
+ if (ret)
+ dev_err(dev, "Failed to add clock provider: %s\n", node->name);
+
+ return ret;
+}
+
static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
{
const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
@@ -648,6 +773,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
ret = PTR_ERR(clk);
return ret;
}
+ wiz->input_clks[WIZ_CORE_REFCLK] = clk;
rate = clk_get_rate(clk);
if (rate >= 100000000)
@@ -661,6 +787,7 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
ret = PTR_ERR(clk);
return ret;
}
+ wiz->input_clks[WIZ_EXT_REFCLK] = clk;
rate = clk_get_rate(clk);
if (rate >= 100000000)
@@ -668,6 +795,13 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
+ if (wiz->type == AM64_WIZ_10G) {
+ ret = wiz_clock_register(wiz);
+ if (ret)
+ dev_err(dev, "Failed to register wiz clocks\n");
+ return ret;
+ }
+
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
node_name = clk_mux_sel[i].node_name;
clk_node = of_get_child_by_name(node, node_name);
@@ -677,8 +811,8 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
goto err;
}
- ret = wiz_mux_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
- clk_mux_sel[i].table);
+ ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
+ clk_mux_sel[i].table);
if (ret) {
dev_err(dev, "Failed to register %s clock\n",
node_name);
--
2.17.1
Hi Kishon,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.11 next-20210222]
[cannot apply to phy/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Kishon-Vijay-Abraham-I/AM64-Add-SERDES-bindings-and-driver-support/20210222-192920
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8e5a26dabfd678ff5e8d7e1c28eaa2fcb5d76e8d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Kishon-Vijay-Abraham-I/AM64-Add-SERDES-bindings-and-driver-support/20210222-192920
git checkout 8e5a26dabfd678ff5e8d7e1c28eaa2fcb5d76e8d
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>, old ones prefixed by <<):
ERROR: modpost: "__delay" [drivers/net/mdio/mdio-cavium.ko] undefined!
>> ERROR: modpost: "of_clk_src_onecell_get" [drivers/phy/cadence/phy-cadence-torrent.ko] undefined!
ERROR: modpost: "devm_clk_register" [drivers/phy/cadence/phy-cadence-torrent.ko] undefined!
>> ERROR: modpost: "of_clk_add_provider" [drivers/phy/cadence/phy-cadence-torrent.ko] undefined!
>> ERROR: modpost: "__clk_get_name" [drivers/phy/cadence/phy-cadence-torrent.ko] undefined!
>> ERROR: modpost: "of_clk_del_provider" [drivers/phy/cadence/phy-cadence-torrent.ko] undefined!
ERROR: modpost: "__udivdi3" [fs/btrfs/btrfs.ko] undefined!
ERROR: modpost: "__umoddi3" [fs/btrfs/btrfs.ko] undefined!
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for SND_ATMEL_SOC_PDC
Depends on SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && HAS_DMA
Selected by
- SND_ATMEL_SOC_SSC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC
- SND_ATMEL_SOC_SSC_PDC && SOUND && !UML && SND && SND_SOC && SND_ATMEL_SOC && ATMEL_SSC
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Kishon,
> -----Original Message-----
> From: Kishon Vijay Abraham I <[email protected]>
> Sent: Monday, February 22, 2021 4:53 PM
> To: Kishon Vijay Abraham I <[email protected]>; Vinod Koul
> <[email protected]>; Rob Herring <[email protected]>; Peter Rosin
> <[email protected]>; Swapnil Kashinath Jakhade <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]
> Subject: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out
>
> EXTERNAL MAIL
>
>
> cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
> reference clock. cmn_refclk_<p/m> can also be configured to output the
> reference clock. Model this derived reference clock as a "clock" so that
> platforms like AM642 EVM can enable it.
>
> This is used by PCIe to use the same refclk both in local SERDES
> and remote device. Add support here to drive refclk out.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> ---
> drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++++++++++++++-
> 1 file changed, 199 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
> b/drivers/phy/cadence/phy-cadence-torrent.c
> index f310e15d94cb..07eebdd90d4b 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -7,7 +7,9 @@
> */
>
> #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-cadence-torrent.h>
> #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/io.h>
> @@ -76,6 +78,8 @@
> * register offsets from SD0801 PHY register block base (i.e MHDP
> * register base + 0x500000)
> */
> +#define CMN_CDIAG_REFCLK_OVRD 0x004CU
> +#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
Nitpick, this can be added sequentially.
> #define CMN_SSM_BANDGAP_TMR 0x0021U
> #define CMN_SSM_BIAS_TMR 0x0022U
> #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
> @@ -206,6 +210,8 @@
> #define RX_DIAG_ACYA 0x01FFU
>
> /* PHY PCS common registers */
> +#define PHY_PIPE_CMN_CTRL1 0x0000U
> +#define PHY_ISO_CMN_CTRL 0x0008U
> #define PHY_PLL_CFG 0x000EU
> #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
> #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
> @@ -216,6 +222,10 @@
> #define PHY_PMA_CMN_CTRL2 0x0001U
> #define PHY_PMA_PLL_RAW_CTRL 0x0003U
>
> +static const char * const clk_names[] = {
> + [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
> +};
> +
> static const struct reg_field phy_pll_cfg =
> REG_FIELD(PHY_PLL_CFG, 0, 1);
>
> @@ -231,6 +241,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
> static const struct reg_field phy_reset_ctrl =
> REG_FIELD(PHY_RESET, 8, 8);
>
> +#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
This could be reduced just to REFCLK_OUT_NUM_PCS_CONFIG, but up to you.
Same below.
> +
> +enum cdns_torrent_refclk_out_pcs {
> + PHY_ISO_CMN_CTRL_8,
> + PHY_PIPE_CMN_CTRL1_0,
> +};
> +
> +#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
> +
> +enum cdns_torrent_refclk_out_cmn {
> + CMN_CDIAG_REFCLK_OVRD_4,
> + CMN_CDIAG_REFCLK_DRV0_CTRL_1,
> + CMN_CDIAG_REFCLK_DRV0_CTRL_4,
> + CMN_CDIAG_REFCLK_DRV0_CTRL_5,
> + CMN_CDIAG_REFCLK_DRV0_CTRL_6,
> +};
> +
> +static const struct reg_field refclk_out_pcs_cfg[] = {
> + [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8,
> 8),
> + [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1,
> 0, 0),
> +};
> +
> +static const struct reg_field refclk_out_cmn_cfg[] = {
> + [CMN_CDIAG_REFCLK_OVRD_4] =
> REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
> + [CMN_CDIAG_REFCLK_DRV0_CTRL_1] =
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
> + [CMN_CDIAG_REFCLK_DRV0_CTRL_4] =
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
> + [CMN_CDIAG_REFCLK_DRV0_CTRL_5] =
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
> + [CMN_CDIAG_REFCLK_DRV0_CTRL_6] =
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
> +};
> +
> enum cdns_torrent_phy_type {
> TYPE_NONE,
> TYPE_DP,
> @@ -279,6 +319,8 @@ struct cdns_torrent_phy {
> struct regmap_field *phy_pma_cmn_ctrl_2;
> struct regmap_field *phy_pma_pll_raw_ctrl;
> struct regmap_field *phy_reset_ctrl;
> + struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
> + struct clk_onecell_data clk_data;
> };
>
> enum phy_powerstate {
> @@ -288,6 +330,16 @@ enum phy_powerstate {
> POWERSTATE_A3 = 3,
> };
>
> +struct cdns_torrent_derived_refclk {
> + struct clk_hw hw;
> + struct regmap_field
> *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
> + struct regmap_field
> *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
> + struct clk_init_data clk_data;
> +};
> +
> +#define to_cdns_torrent_derived_refclk(_hw) \
> + container_of(_hw, struct
> cdns_torrent_derived_refclk, hw)
> +
> static int cdns_torrent_phy_init(struct phy *phy);
> static int cdns_torrent_dp_init(struct phy *phy);
> static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
> @@ -1604,6 +1656,111 @@ static int cdns_torrent_dp_run(struct
> cdns_torrent_phy *cdns_phy, u32 num_lanes)
> return ret;
> }
>
> +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
> +{
> + struct cdns_torrent_derived_refclk *derived_refclk =
> to_cdns_torrent_derived_refclk(hw);
> +
> + regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
> + regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
> + regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
> + regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
> + regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
> + regmap_field_write(derived_refclk-
> >pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
> + regmap_field_write(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
> +
> + return 0;
> +}
> +
> +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
> +{
> + struct cdns_torrent_derived_refclk *derived_refclk =
> to_cdns_torrent_derived_refclk(hw);
> +
> + regmap_field_write(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
> +}
> +
PHY_ISO_CMN_CTRL is a PHY isolation register. Not sure, but is this correct
to control phy_en_refclk to enable/disable refclk output from here?
> +static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
> +{
> + struct cdns_torrent_derived_refclk *derived_refclk =
> to_cdns_torrent_derived_refclk(hw);
> + int val;
> +
> + regmap_field_read(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], &val);
> +
> + return !!val;
> +}
> +
> +static const struct clk_ops cdns_torrent_derived_refclk_ops = {
> + .enable = cdns_torrent_derived_refclk_enable,
> + .disable = cdns_torrent_derived_refclk_disable,
> + .is_enabled = cdns_torrent_derived_refclk_is_enabled,
> +};
> +
> +static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy
> *cdns_phy)
> +{
> + struct cdns_torrent_derived_refclk *derived_refclk;
> + struct device *dev = cdns_phy->dev;
> + struct regmap_field *field;
> + struct clk_init_data *init;
> + const char *parent_name;
> + struct regmap *regmap;
> + char clk_name[100];
> + struct clk *clk;
> + int i;
> +
> + derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk),
> GFP_KERNEL);
> + if (!derived_refclk)
> + return -ENOMEM;
> +
> + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
> + clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
> +
> + clk = devm_clk_get_optional(dev, "phy_en_refclk");
> + if (IS_ERR(clk)) {
> + dev_err(dev, "No parent clock for derived_refclk\n");
> + return PTR_ERR(clk);
> + }
> +
> + init = &derived_refclk->clk_data;
> +
> + if (clk) {
> + parent_name = __clk_get_name(clk);
> + init->parent_names = &parent_name;
> + init->num_parents = 1;
> + }
> + init->ops = &cdns_torrent_derived_refclk_ops;
> + init->flags = 0;
> + init->name = clk_name;
> +
> + regmap = cdns_phy->regmap_phy_pcs_common_cdb;
> + for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG;
> i++) {
> + field = devm_regmap_field_alloc(dev, regmap,
> refclk_out_pcs_cfg[i]);
> + if (IS_ERR(field)) {
> + dev_err(dev, "PCS reg field init failed\n");
> + return PTR_ERR(field);
> + }
> + derived_refclk->pcs_fields[i] = field;
> + }
> +
> + regmap = cdns_phy->regmap_common_cdb;
> + for (i = 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG;
> i++) {
> + field = devm_regmap_field_alloc(dev, regmap,
> refclk_out_cmn_cfg[i]);
> + if (IS_ERR(field)) {
> + dev_err(dev, "CMN reg field init failed\n");
> + return PTR_ERR(field);
> + }
> + derived_refclk->cmn_fields[i] = field;
> + }
> +
> + derived_refclk->hw.init = init;
> +
> + clk = devm_clk_register(dev, &derived_refclk->hw);
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] = clk;
> +
> + return 0;
> +}
> +
> static int cdns_torrent_phy_on(struct phy *phy)
> {
> struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
> @@ -2071,6 +2228,37 @@ int cdns_torrent_phy_configure_multilink(struct
> cdns_torrent_phy *cdns_phy)
> return 0;
> }
>
> +static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
> +{
> + struct device *dev = cdns_phy->dev;
> +
> + of_clk_del_provider(dev->of_node);
> +}
> +
> +static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
> +{
> + struct device *dev = cdns_phy->dev;
> + struct device_node *node = dev->of_node;
> + int ret;
> +
> + ret = cdns_torrent_derived_refclk_register(cdns_phy);
> + if (ret) {
> + dev_err(dev, "failed to register derived refclk\n");
> + return ret;
> + }
> +
> + cdns_phy->clk_data.clks = cdns_phy->clks;
> + cdns_phy->clk_data.clk_num = CDNS_TORRENT_REFCLK_DRIVER + 1;
> +
> + ret = of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy-
> >clk_data);
> + if (ret) {
> + dev_err(dev, "Failed to add clock provider: %s\n", node-
> >name);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int cdns_torrent_phy_probe(struct platform_device *pdev)
> {
> struct cdns_torrent_phy *cdns_phy;
> @@ -2134,17 +2322,21 @@ static int cdns_torrent_phy_probe(struct
> platform_device *pdev)
> if (ret)
> return ret;
>
> + ret = cdns_torrent_clk_register(cdns_phy);
> + if (ret)
> + return ret;
> +
> ret = clk_prepare_enable(cdns_phy->clk);
> if (ret) {
> dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> - return ret;
> + goto clk_cleanup;
> }
>
> cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
> if (!(cdns_phy->ref_clk_rate)) {
> dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> - clk_disable_unprepare(cdns_phy->clk);
> - return -EINVAL;
> + ret = -EINVAL;
> + goto clk_disable;
> }
>
> /* Enable APB */
> @@ -2322,7 +2514,10 @@ static int cdns_torrent_phy_probe(struct
> platform_device *pdev)
> reset_control_put(cdns_phy->phys[i].lnk_rst);
> of_node_put(child);
> reset_control_assert(cdns_phy->apb_rst);
> +clk_disable:
> clk_disable_unprepare(cdns_phy->clk);
> +clk_cleanup:
> + cdns_torrent_clk_cleanup(cdns_phy);
> return ret;
> }
>
> @@ -2339,6 +2534,7 @@ static int cdns_torrent_phy_remove(struct
> platform_device *pdev)
> }
>
> clk_disable_unprepare(cdns_phy->clk);
> + cdns_torrent_clk_cleanup(cdns_phy);
>
> return 0;
> }
> --
> 2.17.1
Thanks & regards,
Swapnil
Hi Swapnil,
On 09/03/21 7:51 pm, Swapnil Kashinath Jakhade wrote:
> Hi Kishon,
>
>> -----Original Message-----
>> From: Kishon Vijay Abraham I <[email protected]>
>> Sent: Monday, February 22, 2021 4:53 PM
>> To: Kishon Vijay Abraham I <[email protected]>; Vinod Koul
>> <[email protected]>; Rob Herring <[email protected]>; Peter Rosin
>> <[email protected]>; Swapnil Kashinath Jakhade <[email protected]>
>> Cc: [email protected]; [email protected]; linux-
>> [email protected]
>> Subject: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out
>>
>> EXTERNAL MAIL
>>
>>
>> cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
>> reference clock. cmn_refclk_<p/m> can also be configured to output the
>> reference clock. Model this derived reference clock as a "clock" so that
>> platforms like AM642 EVM can enable it.
>>
>> This is used by PCIe to use the same refclk both in local SERDES
>> and remote device. Add support here to drive refclk out.
>>
>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>> ---
>> drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++++++++++++++-
>> 1 file changed, 199 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
>> b/drivers/phy/cadence/phy-cadence-torrent.c
>> index f310e15d94cb..07eebdd90d4b 100644
>> --- a/drivers/phy/cadence/phy-cadence-torrent.c
>> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
>> @@ -7,7 +7,9 @@
>> */
>>
>> #include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-cadence-torrent.h>
>> #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> #include <linux/delay.h>
>> #include <linux/err.h>
>> #include <linux/io.h>
>> @@ -76,6 +78,8 @@
>> * register offsets from SD0801 PHY register block base (i.e MHDP
>> * register base + 0x500000)
>> */
>> +#define CMN_CDIAG_REFCLK_OVRD 0x004CU
>> +#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
>
> Nitpick, this can be added sequentially.
>
>> #define CMN_SSM_BANDGAP_TMR 0x0021U
>> #define CMN_SSM_BIAS_TMR 0x0022U
>> #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
>> @@ -206,6 +210,8 @@
>> #define RX_DIAG_ACYA 0x01FFU
>>
>> /* PHY PCS common registers */
>> +#define PHY_PIPE_CMN_CTRL1 0x0000U
>> +#define PHY_ISO_CMN_CTRL 0x0008U
>> #define PHY_PLL_CFG 0x000EU
>> #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
>> #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
>> @@ -216,6 +222,10 @@
>> #define PHY_PMA_CMN_CTRL2 0x0001U
>> #define PHY_PMA_PLL_RAW_CTRL 0x0003U
>>
>> +static const char * const clk_names[] = {
>> + [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
>> +};
>> +
>> static const struct reg_field phy_pll_cfg =
>> REG_FIELD(PHY_PLL_CFG, 0, 1);
>>
>> @@ -231,6 +241,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
>> static const struct reg_field phy_reset_ctrl =
>> REG_FIELD(PHY_RESET, 8, 8);
>>
>> +#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
>
> This could be reduced just to REFCLK_OUT_NUM_PCS_CONFIG, but up to you.
> Same below.
>
>> +
>> +enum cdns_torrent_refclk_out_pcs {
>> + PHY_ISO_CMN_CTRL_8,
>> + PHY_PIPE_CMN_CTRL1_0,
>> +};
>> +
>> +#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
>> +
>> +enum cdns_torrent_refclk_out_cmn {
>> + CMN_CDIAG_REFCLK_OVRD_4,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_1,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_4,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_5,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_6,
>> +};
>> +
>> +static const struct reg_field refclk_out_pcs_cfg[] = {
>> + [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8,
>> 8),
>> + [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1,
>> 0, 0),
>> +};
>> +
>> +static const struct reg_field refclk_out_cmn_cfg[] = {
>> + [CMN_CDIAG_REFCLK_OVRD_4] =
>> REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_1] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_4] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_5] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_6] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
>> +};
>> +
>> enum cdns_torrent_phy_type {
>> TYPE_NONE,
>> TYPE_DP,
>> @@ -279,6 +319,8 @@ struct cdns_torrent_phy {
>> struct regmap_field *phy_pma_cmn_ctrl_2;
>> struct regmap_field *phy_pma_pll_raw_ctrl;
>> struct regmap_field *phy_reset_ctrl;
>> + struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
>> + struct clk_onecell_data clk_data;
>> };
>>
>> enum phy_powerstate {
>> @@ -288,6 +330,16 @@ enum phy_powerstate {
>> POWERSTATE_A3 = 3,
>> };
>>
>> +struct cdns_torrent_derived_refclk {
>> + struct clk_hw hw;
>> + struct regmap_field
>> *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
>> + struct regmap_field
>> *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
>> + struct clk_init_data clk_data;
>> +};
>> +
>> +#define to_cdns_torrent_derived_refclk(_hw) \
>> + container_of(_hw, struct
>> cdns_torrent_derived_refclk, hw)
>> +
>> static int cdns_torrent_phy_init(struct phy *phy);
>> static int cdns_torrent_dp_init(struct phy *phy);
>> static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
>> @@ -1604,6 +1656,111 @@ static int cdns_torrent_dp_run(struct
>> cdns_torrent_phy *cdns_phy, u32 num_lanes)
>> return ret;
>> }
>>
>> +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>> +{
>> + struct cdns_torrent_derived_refclk *derived_refclk =
>> to_cdns_torrent_derived_refclk(hw);
>> +
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
>> +{
>> + struct cdns_torrent_derived_refclk *derived_refclk =
>> to_cdns_torrent_derived_refclk(hw);
>> +
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
>> +}
>> +
>
> PHY_ISO_CMN_CTRL is a PHY isolation register. Not sure, but is this correct
> to control phy_en_refclk to enable/disable refclk output from here?
hmm.. I see this is used to drive phy_en_refclk when in ISOLATION mode.
Given that we are not selecting to operate in isolation mode, this
shouldn't be required.
This was present in the sequence given by HW team but maybe it's enabled
for some debugging.
I've also verified PCIe works without this configuration. I'll repost
without this configuration and also check with HW team on why it was added.
Thanks
Kishon