Terry Bowman ([email protected])

Number of posts: 311 (0.26 per day)
First post: 2021-01-22 18:06:53
Last post: 2024-04-22 14:46:03

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Date List Subject
2023-06-22 21:18:15 linux-kernel [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port
2023-06-22 21:17:40 linux-kernel [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
2023-06-22 21:17:05 linux-kernel [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport
2023-06-22 21:17:05 linux-kernel [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-06-22 21:16:45 linux-kernel [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
2023-06-22 21:16:45 linux-kernel [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address
2023-06-22 21:14:56 linux-kernel [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-06-22 21:14:56 linux-kernel [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev'
2023-06-22 21:07:31 linux-kernel [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-06-22 20:59:40 linux-kernel [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
2023-06-22 20:59:40 linux-kernel [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
2023-06-22 20:59:38 linux-kernel [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse
2023-06-22 20:59:33 linux-kernel [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
2023-06-22 20:59:33 linux-kernel [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
2023-06-22 20:59:33 linux-kernel [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
2023-06-22 20:59:33 linux-kernel [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH
2023-06-22 20:59:29 linux-kernel [PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-22 16:54:17 linux-kernel Re: [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode
2023-06-22 14:59:34 linux-kernel Re: [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
2023-06-22 14:14:18 linux-kernel Re: [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
2023-06-22 05:01:01 linux-kernel [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
2023-06-22 04:57:04 linux-kernel [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port
2023-06-22 04:51:05 linux-kernel [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery
2023-06-22 04:49:45 linux-kernel [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address
2023-06-22 04:48:40 linux-kernel [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-06-22 04:27:14 linux-kernel [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport
2023-06-22 04:25:23 linux-kernel [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
2023-06-22 04:25:11 linux-kernel [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
2023-06-22 04:24:34 linux-kernel [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-06-22 04:24:28 linux-kernel [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev'
2023-06-22 04:24:07 linux-kernel [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
2023-06-22 04:24:03 linux-kernel [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-06-22 04:23:32 linux-kernel [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
2023-06-22 04:23:25 linux-kernel [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode
2023-06-22 04:23:18 linux-kernel [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map
2023-06-22 04:23:12 linux-kernel [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup
2023-06-22 04:22:21 linux-kernel [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging
2023-06-22 04:22:03 linux-kernel [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
2023-06-22 04:22:00 linux-kernel [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB
2023-06-22 04:21:21 linux-kernel [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup
2023-06-22 04:20:44 linux-kernel [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse
2023-06-22 04:09:22 linux-kernel [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
2023-06-22 04:05:38 linux-kernel [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
2023-06-22 04:01:31 linux-kernel [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
2023-06-22 03:59:51 linux-kernel [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port()
2023-06-22 03:58:47 linux-kernel [PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-22 03:58:46 linux-kernel [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
2023-06-22 03:58:37 linux-kernel [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
2023-06-16 16:35:18 linux-kernel Re: [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
2023-06-16 16:33:12 linux-kernel Re: [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
2023-06-13 15:38:21 linux-kernel Re: [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode