Terry Bowman ([email protected])

Number of posts: 311 (0.26 per day)
First post: 2021-01-22 18:06:53
Last post: 2024-04-22 14:46:03

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Date List Subject
2023-06-12 18:27:32 linux-kernel Re: [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors
2023-06-12 15:03:18 linux-kernel Re: [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery
2023-06-08 22:33:54 linux-kernel Re: [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around
2023-06-08 22:31:57 linux-kernel Re: [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map
2023-06-08 19:32:59 linux-kernel Re: [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev
2023-06-08 14:46:02 linux-kernel Re: [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev
2023-06-07 22:56:12 linux-kernel [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
2023-06-07 22:56:00 linux-kernel [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors
2023-06-07 22:55:23 linux-kernel [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode
2023-06-07 22:42:15 linux-kernel [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
2023-06-07 22:41:25 linux-kernel [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around
2023-06-07 22:38:54 linux-kernel [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation
2023-06-07 22:38:48 linux-kernel [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-06-07 22:38:42 linux-kernel [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery
2023-06-07 22:38:21 linux-kernel [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map
2023-06-07 22:37:47 linux-kernel [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-06-07 22:37:38 linux-kernel [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
2023-06-07 22:34:45 linux-kernel [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport
2023-06-07 22:34:23 linux-kernel [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
2023-06-07 22:34:06 linux-kernel [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-06-07 22:33:40 linux-kernel [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup
2023-06-07 22:33:21 linux-kernel [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address
2023-06-07 22:30:57 linux-kernel [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state
2023-06-07 22:30:23 linux-kernel [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port
2023-06-07 22:29:30 linux-kernel [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB
2023-06-07 22:27:25 linux-kernel [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup
2023-06-07 22:27:25 linux-kernel [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse
2023-06-07 22:26:13 linux-kernel [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev
2023-06-07 22:24:31 linux-kernel [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port
2023-06-07 22:24:28 linux-kernel [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
2023-06-07 22:22:45 linux-kernel [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
2023-06-07 22:22:24 linux-kernel [PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling
2023-06-07 22:22:23 linux-kernel [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
2023-06-01 14:17:11 linux-kernel Re: [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors
2023-05-25 21:51:52 linux-kernel Re: [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-05-24 02:12:42 linux-kernel Re: [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling
2023-05-24 00:20:39 linux-kernel [PATCH v4 21/23] cxl/pci: Add RCH downstream port error logging
2023-05-24 00:09:25 linux-kernel [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery
2023-05-24 00:02:27 linux-kernel [PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-05-24 00:02:16 linux-kernel [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address
2023-05-24 00:02:03 linux-kernel [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port
2023-05-24 00:01:28 linux-kernel [PATCH v4 12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
2023-05-23 23:58:59 linux-kernel [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-05-23 23:56:34 linux-kernel [PATCH v4 22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
2023-05-23 23:55:16 linux-kernel [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state
2023-05-23 23:51:25 linux-kernel [PATCH v4 15/23] cxl/port: Remove Component Register base address from struct cxl_dport
2023-05-23 23:47:46 linux-kernel Re: [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling - CHANGELOG
2023-05-23 23:31:19 linux-kernel [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
2023-05-23 23:31:03 linux-kernel [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors
2023-05-23 23:30:27 linux-kernel [PATCH v4 02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
2023-05-23 23:29:14 linux-kernel [PATCH v4 09/23] cxl/pci: Early setup RCH dport component registers from RCRB