This patch series adds MFC v12 support. MFC v12 is used in
Tesla FSD SoC.
This adds support for following:
* Add support for VP9 encoder
* Add support for YV12 and I420 format (3-plane)
* Add support for Rate Control, UHD and DMABUF for encoder
* Add support for DPB buffers allocation based on MFC requirement
* Update Documentation for control id definitions
Changes since v2:
- Addressed review comments by Rob Herring.
- Addressed review comments by Krzysztof Kozlowski.
- Addressed review comments by Andi Shyti.
Smitha T Murthy (15):
dt-bindings: media: s5p-mfc: Add new DT schema for MFC
dt-bindings: media: s5p-mfc: Add mfcv12 variant
media: s5p-mfc: Rename IS_MFCV10 macro
media: s5p-mfc: Add initial support for MFCv12
Documention: v4l: Documentation for VP9 CIDs.
media: v4l2: Add v4l2 control IDs for VP9 encoder.
media: s5p-mfc: Add support for VP9 encoder.
media: s5p-mfc: Add YV12 and I420 multiplanar format support
media: s5p-mfc: Add support for rate controls in MFCv12
media: s5p-mfc: Add support for UHD encoding.
media: s5p-mfc: Add support for DMABUF for encoder
media: s5p-mfc: Set context for valid case before calling try_run
media: s5p-mfc: Load firmware for each run in MFCv12.
media: s5p-mfc: DPB Count Independent of VIDIOC_REQBUF
arm64: dts: fsd: Add MFC related DT enteries
.../devicetree/bindings/media/s5p-mfc.txt | 75 ---------
.../bindings/media/samsung,s5p-mfc.yaml | 164 ++++++++++++++++++
.../media/v4l/ext-ctrls-codec.rst | 167 +++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 21 +
.../platform/samsung/s5p-mfc/regs-mfc-v12.h | 60 +++
.../platform/samsung/s5p-mfc/regs-mfc-v7.h | 1 +
.../platform/samsung/s5p-mfc/regs-mfc-v8.h | 3 +
.../media/platform/samsung/s5p-mfc/s5p_mfc.c | 36 +-
.../platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c | 3 +
.../platform/samsung/s5p-mfc/s5p_mfc_common.h | 56 ++-
.../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 9 +-
.../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 51 ++-
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 410 +++++++++++++++--
.../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 16 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c | 12 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 435 ++++++++++++++++--
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 7 +-
drivers/media/v4l2-core/v4l2-ctrls-defs.c | 44 ++
include/uapi/linux/v4l2-controls.h | 33 ++
19 files changed, 1349 insertions(+), 203 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
create mode 100644 drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
--
2.17.1
From: Smitha T Murthy <[email protected]>
Convert DT schema for s5p-mfc in yaml format
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../devicetree/bindings/media/s5p-mfc.txt | 75 --------
.../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
2 files changed, 163 insertions(+), 75 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index aa54c8159d9f..8b137891791f 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -1,76 +1 @@
-* Samsung Multi Format Codec (MFC)
-Multi Format Codec (MFC) is the IP present in Samsung SoCs which
-supports high resolution decoding and encoding functionalities.
-The MFC device driver is a v4l2 driver which can encode/decode
-video raw/elementary streams and has support for all popular
-video codecs.
-
-Required properties:
- - compatible : value should be either one among the following
- (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
- (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
- (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
- (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
- (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
- (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
-
- - reg : Physical base address of the IP registers and length of memory
- mapped region.
-
- - interrupts : MFC interrupt number to the CPU.
- - clocks : from common clock binding: handle to mfc clock.
- - clock-names : from common clock binding: must contain "mfc",
- corresponding to entry in the clocks property.
-
-Optional properties:
- - power-domains : power-domain property defined with a phandle
- to respective power domain.
- - memory-region : from reserved memory binding: phandles to two reserved
- memory regions, first is for "left" mfc memory bus interfaces,
- second if for the "right" mfc memory bus, used when no SYSMMU
- support is available; used only by MFC v5 present in Exynos4 SoCs
-
-Obsolete properties:
- - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
- property instead
-
-
-Example:
-SoC specific DT entry:
-
-mfc: codec@13400000 {
- compatible = "samsung,mfc-v5";
- reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
- power-domains = <&pd_mfc>;
- clocks = <&clock 273>;
- clock-names = "mfc";
-};
-
-Reserved memory specific DT entry for given board (see reserved memory binding
-for more information):
-
-reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mfc_left: region@51000000 {
- compatible = "shared-dma-pool";
- no-map;
- reg = <0x51000000 0x800000>;
- };
-
- mfc_right: region@43000000 {
- compatible = "shared-dma-pool";
- no-map;
- reg = <0x43000000 0x800000>;
- };
-};
-
-Board specific DT entry:
-
-codec@13400000 {
- memory-region = <&mfc_left>, <&mfc_right>;
-};
diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
new file mode 100644
index 000000000000..ad61b509846f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Multi Format Codec (MFC)
+
+maintainers:
+ - Marek Szyprowski <[email protected]>
+ - Smitha T Murthy <[email protected]>
+ - Aakarsh Jain <[email protected]>
+
+description:
+ Multi Format Codec (MFC) is the IP present in Samsung SoCs which
+ supports high resolution decoding and encoding functionalities.
+
+properties:
+ compatible:
+ enum:
+ - samsung,mfc-v5 # Exynos4
+ - samsung,mfc-v6 # Exynos5
+ - samsung,mfc-v7 # Exynos5420
+ - samsung,mfc-v8 # Exynos5800
+ - samsung,exynos5433-mfc # Exynos5433
+ - samsung,mfc-v10 # Exynos7880
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 2
+
+ iommu-names:
+ maxItems: 2
+
+ power-domains:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,mfc-v6
+ - samsung,mfc-v7
+ - samsung,mfc-v8
+ - tesla,fsd-mfc
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: mfc
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,mfc-v5
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: mfc
+ - const: sclk_mfc
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5433-mfc
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pclk
+ - const: aclk
+ - const: aclk_xiu
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,mfc-v5
+ - samsung,mfc-v6
+ - samsung,mfc-v7
+ - samsung,mfc-v8
+ - samsung,exynos5433-mfc
+
+ then:
+ properties:
+ iommus:
+ minItems: 2
+ maxItems: 2
+ iommu-names:
+ items:
+ - const: left
+ - const: right
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tesla,fsd-mfc
+ then:
+ properties:
+ memory-region:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos4.h>
+ #include <dt-bindings/clock/exynos-audss-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ codec@13400000 {
+ compatible = "samsung,mfc-v5";
+ reg = <0x13400000 0x10000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_mfc>;
+ clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
+ clock-names = "mfc", "sclk_mfc";
+ iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+ iommu-names = "left", "right";
+
+ };
--
2.17.1
From: Smitha T Murthy <[email protected]>
Renames macro IS_MFCV10 to IS_MFCV10_PLUS so that the MFCv10 code can
be resued for MFCv12 support. Since some part of MFCv10 specific code
holds good for MFCv12 also.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/s5p_mfc_common.h | 10 +++----
.../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 2 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 28 +++++++++----------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
index 5304f42c8c72..e6ec4a43b290 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
@@ -771,11 +771,11 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
(dev->variant->port_num ? 1 : 0) : 0) : 0)
#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
-#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
-#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
-#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0)
-#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0)
-#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
+#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60)
+#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70)
+#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80)
+#define IS_MFCV10_PLUS(dev) (dev->variant->version >= 0xA0)
+#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev))
#define MFC_V5_BIT BIT(0)
#define MFC_V6_BIT BIT(1)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
index 72d70984e99a..ffe9f7e79eca 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
@@ -236,7 +236,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
else
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
mfc_debug(2, "Will now wait for completion of firmware transfer\n");
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 8227004f6746..728d255e65fc 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -72,9 +72,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->luma_size, ctx->chroma_size, ctx->mv_size);
mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
} else if (ctx->type == MFCINST_ENCODER) {
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev))
ctx->tmv_buffer_size = 0;
- } else if (IS_MFCV8_PLUS(dev))
+ else if (IS_MFCV8_PLUS(dev))
ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
S5P_FIMV_TMV_BUFFER_ALIGN_V6);
@@ -82,7 +82,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
S5P_FIMV_TMV_BUFFER_ALIGN_V6);
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
@@ -133,7 +133,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
switch (ctx->codec_mode) {
case S5P_MFC_CODEC_H264_DEC:
case S5P_MFC_CODEC_H264_MVC_DEC:
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_debug(2, "Use min scratch buffer size\n");
else if (IS_MFCV8_PLUS(dev))
ctx->scratch_buf_size =
@@ -152,7 +152,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
(ctx->mv_count * ctx->mv_size);
break;
case S5P_MFC_CODEC_MPEG4_DEC:
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_debug(2, "Use min scratch buffer size\n");
else if (IS_MFCV7_PLUS(dev)) {
ctx->scratch_buf_size =
@@ -172,7 +172,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
break;
case S5P_MFC_CODEC_VC1RCV_DEC:
case S5P_MFC_CODEC_VC1_DEC:
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_debug(2, "Use min scratch buffer size\n");
else
ctx->scratch_buf_size =
@@ -189,7 +189,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->bank2.size = 0;
break;
case S5P_MFC_CODEC_H263_DEC:
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_debug(2, "Use min scratch buffer size\n");
else
ctx->scratch_buf_size =
@@ -201,7 +201,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->bank1.size = ctx->scratch_buf_size;
break;
case S5P_MFC_CODEC_VP8_DEC:
- if (IS_MFCV10(dev))
+ if (IS_MFCV10_PLUS(dev))
mfc_debug(2, "Use min scratch buffer size\n");
else if (IS_MFCV8_PLUS(dev))
ctx->scratch_buf_size =
@@ -230,7 +230,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
DEC_VP9_STATIC_BUFFER_SIZE;
break;
case S5P_MFC_CODEC_H264_ENC:
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
@@ -254,7 +254,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
break;
case S5P_MFC_CODEC_MPEG4_ENC:
case S5P_MFC_CODEC_H263_ENC:
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
@@ -273,7 +273,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->bank2.size = 0;
break;
case S5P_MFC_CODEC_VP8_ENC:
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
@@ -452,7 +452,7 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
ctx->img_height);
} else {
@@ -668,7 +668,7 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
- if (IS_MFCV10(dev)) {
+ if (IS_MFCV10_PLUS(dev)) {
/* start address of per buffer is aligned */
for (i = 0; i < ctx->pb_count; i++) {
writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
@@ -2455,7 +2455,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
- if (!IS_MFCV10(dev))
+ if (!IS_MFCV10_PLUS(dev))
goto done;
/* Initialize registers used in MFC v10 only.
--
2.17.1
From: Smitha T Murthy <[email protected]>
Adds V4l2 controls for VP9 encoder documention.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
1 file changed, 167 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
index 2a165ae063fb..2277d83a7cf0 100644
--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
@@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
* - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
- Profile 3
+VP9 Control Reference
+---------------------
+
+The VP9 controls include controls for encoding parameters of VP9 video
+codec.
+
+.. _vp9-control-id:
+
+VP9 Control IDs
+
.. _v4l2-mpeg-video-vp9-profile:
``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
@@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
* - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
- Level 6.2
+``V4L2_CID_CODEC_VP9_I_FRAME_QP``
+ Quantization parameter for an I frame for VP9. Valid range: from 1 to 255.
+
+``V4L2_CID_CODEC_VP9_P_FRAME_QP``
+ Quantization parameter for an P frame for VP9. Valid range: from 1 to 255.
+
+``V4L2_CID_CODEC_VP9_MAX_QP``
+ Maximum quantization parameter for VP9. Valid range: from 1 to 255.
+ Recommended range for MFC is from 230 to 255.
+
+``V4L2_CID_CODEC_VP9_MIN_QP``
+ Minimum quantization parameter for VP9. Valid range: from 1 to 255.
+ Recommended range for MFC is from 1 to 24.
+
+``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
+ Indicates the number of evenly spaced subintervals, called ticks, within
+ one second. This is a 16 bit unsigned integer and has a maximum value up to
+ 0xffff and a minimum value of 1.
+
+``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
+ Indicates the refresh period of the golden frame for VP9 encoder.
+
+.. _v4l2-vp9-golden-frame-sel:
+
+``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
+ (enum)
+
+enum v4l2_mpeg_vp9_golden_framesel -
+ Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
+ Possible values are:
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
+ - Use the (n-2)th frame as a golden frame, current frame index being
+ 'n'.
+ * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
+ - Use the previous specific frame indicated by
+ ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
+ golden frame.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
+ Allows host to specify the quantization parameter values for each
+ temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
+ if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
+ value to 1 enables setting of the QP values for the layers.
+
+.. _v4l2-vp9-ref-number-of-pframes:
+
+``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
+ (enum)
+
+enum v4l2_mpeg_vp9_ref_num_for_pframes -
+ Number of reference pictures for encoding P frames.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
+ - Indicates one reference frame, last encoded frame will be searched.
+ * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
+ - Indicates 2 reference frames, last encoded frame and golden frame
+ will be searched.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
+ Indicates the number of hierarchial coding layer.
+ In normal encoding (non-hierarchial coding), it should be zero.
+ VP9 has upto 3 layer of encoder.
+
+``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
+ Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
+ Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
+ Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
+ Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
+ Indicates quantization parameter for hierarchical coding layer 0.
+ Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
+ V4L2_CID_CODEC_VP9_MAX_QP].
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
+ Indicates quantization parameter for hierarchical coding layer 1.
+ Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
+ V4L2_CID_CODEC_VP9_MAX_QP].
+
+``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
+ Indicates quantization parameter for hierarchical coding layer 2.
+ Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
+ V4L2_CID_CODEC_VP9_MAX_QP].
+
+.. _v4l2-vp9-max-partition-depth:
+
+``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
+ (enum)
+
+enum v4l2_mpeg_vp9_num_partitions -
+ Indicate maximum coding unit depth.
+
+.. raw:: latex
+
+ \footnotesize
+
+.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
+
+.. flat-table::
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
+ - No coding unit partition depth.
+ * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
+ - Allows one coding unit partition depth.
+
+.. raw:: latex
+
+ \normalsize
+
+
+``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
+ Zero indicates enable intra NxN PU split.
+ One indicates disable intra NxN PU split.
+
+``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
+ Indicates IVF header generation. Zero indicates enable IVF format.
+ One indicates disable IVF format.
+
High Efficiency Video Coding (HEVC/H.265) Control Reference
===========================================================
--
2.17.1
From: Smitha T Murthy <[email protected]>
MFC driver had restriction on max resolution of 1080p, updated it for
UHD. Added corresponding support to set recommended profile and level
for H264 in UHD scenario.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c | 9 ++++++---
.../media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 12 ++++++++++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index b761b9a31383..f953a3ed7f20 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -1628,9 +1628,12 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
mfc_err("Unsupported format by this MFC version.\n");
return -EINVAL;
}
-
- v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1,
- &pix_fmt_mp->height, 4, 1080, 1, 0);
+ if (IS_MFCV12(dev))
+ v4l_bound_align_image(&pix_fmt_mp->width, 8, 3840, 1,
+ &pix_fmt_mp->height, 4, 2160, 1, 0);
+ else
+ v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1,
+ &pix_fmt_mp->height, 4, 1080, 1, 0);
} else {
mfc_err("invalid buf type\n");
return -EINVAL;
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 2194df7b6fbf..c4953419be0e 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -1116,6 +1116,18 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
reg |= ((p->num_b_frame & 0x3) << 16);
writel(reg, mfc_regs->e_gop_config);
+ /* UHD encoding case */
+ if ((ctx->img_width == 3840) && ctx->img_height == 2160) {
+ if (p_h264->level < 51) {
+ mfc_debug(2, "Set Level 5.1 for UHD\n");
+ p_h264->level = 51;
+ }
+ if (p_h264->profile != 0x2) {
+ mfc_debug(2, "Set High profile for UHD\n");
+ p_h264->profile = 0x2;
+ }
+ }
+
/* profile & level */
reg = 0;
/** level */
--
2.17.1
From: Smitha T Murthy <[email protected]>
Add V4l2 controls for VP9 encoder
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
drivers/media/v4l2-core/v4l2-ctrls-defs.c | 44 +++++++++++++++++++++++
include/uapi/linux/v4l2-controls.h | 33 +++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index e22921e7ea61..2d92e93158bd 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
@@ -577,6 +577,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
"Cyclic",
NULL,
};
+ static const char * const vp9_golden_framesel[] = {
+ "Use previous",
+ "Use refresh period",
+ NULL,
+ };
+ static const char * const vp9_ref_num_for_pframes[] = {
+ "1",
+ "2",
+ NULL,
+ };
+ static const char * const vp9_max_partition_depth[] = {
+ "No CU partition depth",
+ "Allow 1 CU partition depth",
+ NULL,
+ };
switch (id) {
case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ:
@@ -708,6 +723,12 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
return hevc_decode_mode;
case V4L2_CID_STATELESS_HEVC_START_CODE:
return hevc_start_code;
+ case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL:
+ return vp9_golden_framesel;
+ case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES:
+ return vp9_ref_num_for_pframes;
+ case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH:
+ return vp9_max_partition_depth;
case V4L2_CID_CAMERA_ORIENTATION:
return camera_orientation;
case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE:
@@ -950,6 +971,26 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_MPEG_VIDEO_VP8_PROFILE: return "VP8 Profile";
case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile";
case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level";
+ case V4L2_CID_CODEC_VP9_I_FRAME_QP: return "VP9 I Frame QP Value";
+ case V4L2_CID_CODEC_VP9_P_FRAME_QP: return "VP9 P Frame QP Value";
+ case V4L2_CID_CODEC_VP9_MAX_QP: return "VP9 Frame QP MAX Value";
+ case V4L2_CID_CODEC_VP9_MIN_QP: return "VP9 Frame QP MIN Value";
+ case V4L2_CID_CODEC_VP9_RC_FRAME_RATE: return "VP9 Frame Rate";
+ case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: return "VP9 Indication of Golden Frame";
+ case V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD: return "VP9 Golden Frame Refresh Period";
+ case V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE: return "VP9 Hierarchical QP Enable";
+ case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: return "VP9 Number of Reference Pictures";
+ case V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER:return "VP9 Num of Hierarchical Layers";
+ case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: return "VP9 Maximum Coding Unit Depth";
+ case V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT: return "VP9 Disable Intra PU Split";
+ case V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE: return "VP9 Hierarchical BitRate Enable";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR: return "VP9 Hierarchical Layer 0 BitRate";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR: return "VP9 Hierarchical Layer 1 BitRate";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR: return "VP9 Hierarchical Layer 2 BitRate";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP: return "VP9 Layer0 QP Value";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP: return "VP9 Layer1 QP Value";
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP: return "VP9 Layer2 QP Value";
+ case V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER: return "VP9 IVF header generation";
/* HEVC controls */
case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value";
@@ -1366,6 +1407,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE:
case V4L2_CID_STATELESS_HEVC_DECODE_MODE:
case V4L2_CID_STATELESS_HEVC_START_CODE:
+ case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL:
+ case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES:
+ case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH:
case V4L2_CID_STATELESS_H264_DECODE_MODE:
case V4L2_CID_STATELESS_H264_START_CODE:
case V4L2_CID_CAMERA_ORIENTATION:
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index b5e7d082b8ad..a60b60bc4ad4 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -722,6 +722,38 @@ enum v4l2_mpeg_video_vp9_level {
V4L2_MPEG_VIDEO_VP9_LEVEL_6_1 = 12,
V4L2_MPEG_VIDEO_VP9_LEVEL_6_2 = 13,
};
+#define V4L2_CID_CODEC_VP9_RC_FRAME_RATE (V4L2_CID_CODEC_BASE+514)
+#define V4L2_CID_CODEC_VP9_MIN_QP (V4L2_CID_CODEC_BASE+515)
+#define V4L2_CID_CODEC_VP9_MAX_QP (V4L2_CID_CODEC_BASE+516)
+#define V4L2_CID_CODEC_VP9_I_FRAME_QP (V4L2_CID_CODEC_BASE+517)
+#define V4L2_CID_CODEC_VP9_P_FRAME_QP (V4L2_CID_CODEC_BASE+518)
+#define V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL (V4L2_CID_CODEC_BASE+519)
+enum v4l2_mpeg_vp9_golden_framesel {
+ V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV = 0,
+ V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD = 1,
+};
+#define V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD (V4L2_CID_CODEC_BASE+520)
+#define V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE (V4L2_CID_CODEC_BASE+521)
+#define V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES (V4L2_CID_CODEC_BASE+522)
+enum v4l2_mpeg_vp9_ref_num_for_pframes {
+ V4L2_CID_CODEC_VP9_1_REF_PFRAME = 0,
+ V4L2_CID_CODEC_VP9_2_REF_PFRAME = 1,
+};
+#define V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER (V4L2_CID_CODEC_BASE+523)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR (V4L2_CID_CODEC_BASE+524)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR (V4L2_CID_CODEC_BASE+525)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR (V4L2_CID_CODEC_BASE+526)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP (V4L2_CID_CODEC_BASE+527)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP (V4L2_CID_CODEC_BASE+528)
+#define V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP (V4L2_CID_CODEC_BASE+529)
+#define V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH (V4L2_CID_CODEC_BASE+530)
+enum v4l2_mpeg_vp9_num_partitions {
+ V4L2_CID_CODEC_VP9_0_PARTITION = 0,
+ V4L2_CID_CODEC_VP9_1_PARTITION = 1,
+};
+#define V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT (V4L2_CID_CODEC_BASE+531)
+#define V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER (V4L2_CID_CODEC_BASE+532)
+#define V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE (V4L2_CID_CODEC_BASE+533)
/* CIDs for HEVC encoding. */
@@ -832,6 +864,7 @@ enum v4l2_mpeg_video_frame_skip_mode {
#define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY (V4L2_CID_CODEC_BASE + 653)
#define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE (V4L2_CID_CODEC_BASE + 654)
+
/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
#define V4L2_CID_CODEC_CX2341X_BASE (V4L2_CTRL_CLASS_CODEC | 0x1000)
#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_CODEC_CX2341X_BASE+0)
--
2.17.1
From: Smitha T Murthy <[email protected]>
Add Tesla FSD MFC(MFC v12) compatible.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
index ad61b509846f..9fb4cae1b68f 100644
--- a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
+++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
@@ -24,6 +24,7 @@ properties:
- samsung,mfc-v8 # Exynos5800
- samsung,exynos5433-mfc # Exynos5433
- samsung,mfc-v10 # Exynos7880
+ - tesla,fsd-mfc # Tesla FSD
reg:
maxItems: 1
--
2.17.1
From: Smitha T Murthy <[email protected]>
Add VP9 encoder support and necessary registers, V4L2 CIDs, vp9
encoder parameters.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/regs-mfc-v12.h | 8 +
.../platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c | 3 +
.../platform/samsung/s5p-mfc/s5p_mfc_common.h | 27 +-
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 273 ++++++++++++++++++
.../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 2 +
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 121 ++++++++
6 files changed, 433 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
index 6c68a45082d0..7cb74a9cb769 100644
--- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
+++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
@@ -12,6 +12,10 @@
#include <linux/sizes.h>
#include "regs-mfc-v10.h"
+/* MFCv12 register definitions*/
+#define S5P_FIMV_E_VP9_OPTION_V12 0xFD90
+#define S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12 0xFD98
+
/* MFCv12 Context buffer sizes */
#define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K)
#define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M)
@@ -47,4 +51,8 @@
ALIGN((((x + 3) * (y + 3) * 32) \
+ (((y * 128) + 2304) * (x + 3) / 4)), 256)
+#define ENC_V120_VP9_ME_SIZE(x, y) \
+ ((((x * 2) + 3) * ((y * 2) + 3) * 128) \
+ + (((y * 256) + 2304) * (x + 1) / 2))
+
#endif /*_REGS_MFC_V12_H*/
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c
index f8588e52dfc8..d524815cd38a 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c
@@ -121,6 +121,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
case S5P_MFC_CODEC_HEVC_ENC:
codec_type = S5P_FIMV_CODEC_HEVC_ENC;
break;
+ case S5P_MFC_CODEC_VP9_ENC:
+ codec_type = S5P_FIMV_CODEC_VP9_ENC;
+ break;
default:
codec_type = S5P_FIMV_CODEC_NONE_V6;
}
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
index dd2e9f7704ab..10abaa50d7db 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
@@ -57,7 +57,7 @@
#define MFC_ENC_CAP_PLANE_COUNT 1
#define MFC_ENC_OUT_PLANE_COUNT 2
#define STUFF_BYTE 4
-#define MFC_MAX_CTRLS 128
+#define MFC_MAX_CTRLS 147
#define S5P_MFC_CODEC_NONE -1
#define S5P_MFC_CODEC_H264_DEC 0
@@ -77,6 +77,7 @@
#define S5P_MFC_CODEC_H263_ENC 23
#define S5P_MFC_CODEC_VP8_ENC 24
#define S5P_MFC_CODEC_HEVC_ENC 26
+#define S5P_MFC_CODEC_VP9_ENC 27
#define S5P_MFC_R2H_CMD_EMPTY 0
#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
@@ -483,6 +484,29 @@ struct s5p_mfc_hevc_enc_params {
u8 prepend_sps_pps_to_idr;
};
+/**
+ * struct s5p_mfc_vp9_enc_params - encoding parameters for vp9
+ */
+struct s5p_mfc_vp9_enc_params {
+ u32 rc_framerate;
+ u8 vp9_profile;
+ u8 rc_min_qp;
+ u8 rc_max_qp;
+ u8 rc_frame_qp;
+ u8 rc_p_frame_qp;
+ u8 vp9_goldenframesel;
+ u8 vp9_gfrefreshperiod;
+ u8 hier_qp_enable;
+ u8 hier_qp_layer[3];
+ u8 hier_rc_enable;
+ u32 hier_bit_layer[3];
+ u8 num_refs_for_p;
+ u8 num_hier_layer;
+ u8 max_partition_depth;
+ u8 intra_pu_split_disable;
+ u8 ivf_header;
+};
+
/*
* struct s5p_mfc_enc_params - general encoding parameters
*/
@@ -521,6 +545,7 @@ struct s5p_mfc_enc_params {
struct s5p_mfc_mpeg4_enc_params mpeg4;
struct s5p_mfc_vp8_enc_params vp8;
struct s5p_mfc_hevc_enc_params hevc;
+ struct s5p_mfc_vp9_enc_params vp9;
} codec;
};
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index 143d95fe2f89..197667ab1fbc 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -94,6 +94,14 @@ static struct s5p_mfc_fmt formats[] = {
.num_planes = 1,
.versions = MFC_V10PLUS_BITS,
},
+ {
+ .fourcc = V4L2_PIX_FMT_VP9,
+ .codec_mode = S5P_FIMV_CODEC_VP9_ENC,
+ .type = MFC_FMT_ENC,
+ .num_planes = 1,
+ .versions = MFC_V12_BIT,
+ },
+
};
#define NUM_FORMATS ARRAY_SIZE(formats)
@@ -1055,6 +1063,174 @@ static struct mfc_control controls[] = {
.step = 1,
.default_value = 0,
},
+ {
+ .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,
+ .type = V4L2_CTRL_TYPE_MENU,
+ .minimum = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+ .maximum = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ .step = 1,
+ .default_value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_I_FRAME_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 1,
+ .maximum = 255,
+ .step = 1,
+ .default_value = 1,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_P_FRAME_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 1,
+ .maximum = 255,
+ .step = 1,
+ .default_value = 1,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_MAX_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 230,
+ .maximum = 255,
+ .step = 1,
+ .default_value = 255,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_MIN_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 1,
+ .maximum = 24,
+ .step = 1,
+ .default_value = 1,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_RC_FRAME_RATE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 1,
+ .maximum = (1 << 16) - 1,
+ .step = 1,
+ .default_value = 1,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL,
+ .type = V4L2_CTRL_TYPE_MENU,
+ .minimum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV,
+ .maximum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD,
+ .step = 1,
+ .default_value = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 0,
+ .maximum = ((1 << 16) - 1),
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES,
+ .type = V4L2_CTRL_TYPE_MENU,
+ .minimum = V4L2_CID_CODEC_VP9_1_REF_PFRAME,
+ .maximum = V4L2_CID_CODEC_VP9_2_REF_PFRAME,
+ .step = 1,
+ .default_value = V4L2_CID_CODEC_VP9_1_REF_PFRAME,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = 0,
+ .maximum = 2,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH,
+ .type = V4L2_CTRL_TYPE_MENU,
+ .minimum = V4L2_CID_CODEC_VP9_0_PARTITION,
+ .maximum = V4L2_CID_CODEC_VP9_1_PARTITION,
+ .step = 1,
+ .default_value = V4L2_CID_CODEC_VP9_0_PARTITION,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .minimum = INT_MIN,
+ .maximum = INT_MAX,
+ .step = 1,
+ .default_value = 0,
+ },
+ {
+ .id = V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER,
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .minimum = 0,
+ .maximum = 1,
+ .step = 1,
+ .default_value = 0,
+ },
{
.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
.type = V4L2_CTRL_TYPE_INTEGER,
@@ -1791,6 +1967,36 @@ static void __enc_update_hevc_qp_ctrls_range(struct s5p_mfc_ctx *ctx,
}
}
+/*
+ * Update range of all VP9 quantization parameter controls that depend on the
+ * V4L2_CID_CODEC_VP9_MIN_QP, V4L2_CID_CODEC_VP9_MAX_QP controls.
+ */
+static void __enc_update_vp9_qp_ctrls_range(struct s5p_mfc_ctx *ctx,
+ int min, int max)
+{
+ static const int __vp9_qp_ctrls[] = {
+ V4L2_CID_CODEC_VP9_I_FRAME_QP,
+ V4L2_CID_CODEC_VP9_P_FRAME_QP,
+ V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP,
+ V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP,
+ V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP,
+ };
+ struct v4l2_ctrl *ctrl = NULL;
+ int i, j;
+
+ for (i = 0; i < ARRAY_SIZE(__vp9_qp_ctrls); i++) {
+ for (j = 0; j < ARRAY_SIZE(ctx->ctrls); j++) {
+ if (ctx->ctrls[j]->id == __vp9_qp_ctrls[i]) {
+ ctrl = ctx->ctrls[j];
+ break;
+ }
+ }
+ if (WARN_ON(!ctrl))
+ break;
+ __v4l2_ctrl_modify_range(ctrl, min, max, ctrl->step, min);
+ }
+}
+
static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
@@ -2194,6 +2400,73 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR:
p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
break;
+ case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:
+ p->codec.vp9.vp9_profile = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_RC_FRAME_RATE:
+ p->codec.vp9.rc_framerate = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_MIN_QP:
+ p->codec.vp9.rc_min_qp = ctrl->val;
+ __enc_update_vp9_qp_ctrls_range(ctx, ctrl->val,
+ p->codec.vp9.rc_max_qp);
+ break;
+ case V4L2_CID_CODEC_VP9_MAX_QP:
+ p->codec.vp9.rc_max_qp = ctrl->val;
+ __enc_update_vp9_qp_ctrls_range(ctx,
+ p->codec.vp9.rc_min_qp, ctrl->val);
+ break;
+ case V4L2_CID_CODEC_VP9_I_FRAME_QP:
+ p->codec.vp9.rc_frame_qp = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_P_FRAME_QP:
+ p->codec.vp9.rc_p_frame_qp = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL:
+ p->codec.vp9.vp9_goldenframesel = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD:
+ p->codec.vp9.vp9_gfrefreshperiod = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE:
+ p->codec.vp9.hier_qp_enable = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE:
+ p->codec.vp9.hier_rc_enable = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP:
+ p->codec.vp9.hier_qp_layer[0] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP:
+ p->codec.vp9.hier_qp_layer[1] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP:
+ p->codec.vp9.hier_qp_layer[2] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR:
+ p->codec.vp9.hier_bit_layer[0] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR:
+ p->codec.vp9.hier_bit_layer[1] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR:
+ p->codec.vp9.hier_bit_layer[2] = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES:
+ p->codec.vp9.num_refs_for_p = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER:
+ p->codec.vp9.num_hier_layer = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH:
+ p->codec.vp9.max_partition_depth = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT:
+ p->codec.vp9.intra_pu_split_disable = ctrl->val;
+ break;
+ case V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER:
+ p->codec.vp9.ivf_header = ctrl->val;
+ break;
default:
v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
ctrl->id, ctrl->val);
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
index 87ac56756a16..a005623e2daa 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
@@ -277,6 +277,8 @@ struct s5p_mfc_regs {
void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
void __iomem *e_hevc_nal_control; /* v10 */
+ void __iomem *e_vp9_options; /* v12 */
+ void __iomem *e_vp9_golden_frame_option; /* v12 */
};
struct s5p_mfc_hw_ops {
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 5d14ccf8b4fe..87bd10b34620 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -363,6 +363,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->chroma_dpb_size + ctx->me_buffer_size));
ctx->bank2.size = 0;
break;
+ case S5P_FIMV_CODEC_VP9_ENC:
+ mfc_debug(2, "Use min scratch buffer size\n");
+ ctx->me_buffer_size =
+ ALIGN(ENC_V120_VP9_ME_SIZE(lcu_width, lcu_height), 16);
+ ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+ ctx->bank1.size =
+ ctx->scratch_buf_size + ctx->tmv_buffer_size +
+ (ctx->pb_count * (ctx->luma_dpb_size +
+ ctx->chroma_dpb_size + ctx->me_buffer_size));
+ ctx->bank2.size = 0;
+ break;
default:
break;
}
@@ -418,6 +429,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
case S5P_MFC_CODEC_MPEG4_ENC:
case S5P_MFC_CODEC_H263_ENC:
case S5P_MFC_CODEC_VP8_ENC:
+ case S5P_FIMV_CODEC_VP9_ENC:
ctx->ctx.size = buf_size->other_enc_ctx;
break;
default:
@@ -1652,6 +1664,102 @@ static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
return 0;
}
+int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
+{
+ struct s5p_mfc_dev *dev = ctx->dev;
+ const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
+ struct s5p_mfc_enc_params *p = &ctx->enc_params;
+ struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9;
+ unsigned int reg = 0;
+ int i;
+
+ mfc_debug_enter();
+
+ s5p_mfc_set_enc_params(ctx);
+
+ /* profile*/
+ reg = 0;
+ reg |= (p_vp9->vp9_profile);
+ writel(reg, mfc_regs->e_picture_profile);
+
+ reg = 0;
+ reg |= ((p_vp9->ivf_header & 0x1) << 12);
+ reg |= ((p_vp9->hier_qp_enable & 0x1) << 11);
+ reg |= (p_vp9->max_partition_depth & 0x1) << 3;
+ reg |= (p_vp9->intra_pu_split_disable & 0x1) << 1;
+ reg |= (p_vp9->num_refs_for_p - 1) & 0x1;
+ writel(reg, mfc_regs->e_vp9_options);
+
+ reg = 0;
+ reg |= (p_vp9->vp9_goldenframesel & 0x1);
+ reg |= (p_vp9->vp9_gfrefreshperiod & 0xffff) << 1;
+ writel(reg, mfc_regs->e_vp9_golden_frame_option);
+
+ reg = 0;
+ if (p_vp9->num_hier_layer) {
+ reg |= p_vp9->num_hier_layer & 0x3;
+ writel(reg, mfc_regs->e_num_t_layer);
+ /* QP value for each layer */
+ if (p_vp9->hier_qp_enable) {
+ for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
+ writel(p_vp9->hier_qp_layer[i],
+ mfc_regs->e_hier_qp_layer0
+ + i * 4);
+ }
+ if (p_vp9->hier_rc_enable) {
+ for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
+ writel(p_vp9->hier_bit_layer[i],
+ mfc_regs->e_hier_bit_rate_layer0
+ + i * 4);
+ }
+ }
+ /* number of coding layer should be zero when hierarchical is disable */
+ reg |= p_vp9->num_hier_layer;
+ writel(reg, mfc_regs->e_num_t_layer);
+
+ /* qp */
+ writel(0x0, mfc_regs->e_fixed_picture_qp);
+ if (!p->rc_frame && !p->rc_mb) {
+ reg = 0;
+ reg &= ~(0xff << 8);
+ reg |= (p_vp9->rc_p_frame_qp << 8);
+ reg &= ~(0xff);
+ reg |= p_vp9->rc_frame_qp;
+ writel(reg, mfc_regs->e_fixed_picture_qp);
+ }
+
+ /* frame rate */
+ if (p->rc_frame) {
+ reg = 0;
+ reg &= ~(0xffff << 16);
+ reg |= ((p_vp9->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
+ reg &= ~(0xffff);
+ reg |= FRAME_DELTA_DEFAULT;
+ writel(reg, mfc_regs->e_rc_frame_rate);
+ }
+
+ /* rate control config. */
+ reg = readl(mfc_regs->e_rc_config);
+ /** macroblock level rate control */
+ reg &= ~(0x1 << 8);
+ reg |= ((p->rc_mb & 0x1) << 8);
+ writel(reg, mfc_regs->e_rc_config);
+
+ /* max & min value of QP */
+ reg = 0;
+ /** max QP */
+ reg &= ~(0xFF << 8);
+ reg |= (p_vp9->rc_max_qp << 8);
+ /** min QP */
+ reg &= ~(0xFF);
+ reg |= p_vp9->rc_min_qp;
+ writel(reg, mfc_regs->e_rc_qp_bound);
+
+ mfc_debug_leave();
+
+ return 0;
+}
+
/* Initialize decoding */
static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
{
@@ -1773,6 +1881,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
s5p_mfc_set_enc_params_vp8(ctx);
else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
s5p_mfc_set_enc_params_hevc(ctx);
+ else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC)
+ s5p_mfc_set_enc_params_vp9(ctx);
else {
mfc_err("Unknown codec for encoding (%x).\n",
ctx->codec_mode);
@@ -2536,6 +2646,17 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
+ if (!IS_MFCV12(dev))
+ goto done;
+
+ /* Initialize registers used in MFC v10 only.
+ * Also, over-write the registers which have
+ * a different offset for MFC v10.
+ */
+
+ R(e_vp9_options, S5P_FIMV_E_VP9_OPTION_V12);
+ R(e_vp9_golden_frame_option, S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12);
+
done:
return &mfc_regs;
#undef S5P_MFC_REG_ADDR
--
2.17.1
From: Smitha T Murthy <[email protected]>
Context bit is set for hardware execution if there is a buffer in
source and destination queue before calling try_run in the
init_buffers function. Now there will be a new context created and
hardware will be invoked for the buffer queued instead of waiting for
another buffer to be queued from userspace to set this context bit for
hw execution.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
index ad04ec68921b..7e6fd130f7d4 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
@@ -589,6 +589,8 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
s5p_mfc_clock_off();
wake_up(&ctx->queue);
+ if (ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
+ set_work_bit_irqsave(ctx);
s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
} else {
WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
--
2.17.1
From: Smitha T Murthy <[email protected]>
YV12 and I420 format (3-plane) support is added. Stride information is
added to all formats and planes since it is necessary for YV12/I420
which are different from width.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/regs-mfc-v12.h | 2 +
.../platform/samsung/s5p-mfc/regs-mfc-v7.h | 1 +
.../platform/samsung/s5p-mfc/regs-mfc-v8.h | 3 +
.../platform/samsung/s5p-mfc/s5p_mfc_common.h | 4 +
.../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 45 ++++-
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 86 +++++++--
.../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 6 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c | 12 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 168 +++++++++++++++---
9 files changed, 281 insertions(+), 46 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
index 7cb74a9cb769..07cb218c0179 100644
--- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
+++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
@@ -30,6 +30,8 @@
#define MFC_VERSION_V12 0xC0
#define MFC_NUM_PORTS_V12 1
#define S5P_FIMV_CODEC_VP9_ENC 27
+#define MFC_CHROMA_PAD_BYTES_V12 256
+#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V12 256
/* Encoder buffer size for MFCv12 */
#define ENC_V120_BASE_SIZE(x, y) \
diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h
index 4a7adfdaa359..50f9bf0603c1 100644
--- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h
+++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h
@@ -24,6 +24,7 @@
#define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7 0xfa70
#define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7 0xfa74
+#define S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7 0xfa78
#define S5P_FIMV_E_VP8_OPTIONS_V7 0xfdb0
#define S5P_FIMV_E_VP8_FILTER_OPTIONS_V7 0xfdb4
diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h
index 162e3c7e920f..0ef9eb2dff22 100644
--- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h
+++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h
@@ -17,13 +17,16 @@
#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108
#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144
#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148
+#define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8 0xf14C
#define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150
#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138
#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c
+#define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8 0xf140
#define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160
#define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260
+#define S5P_FIMV_D_THIRD_PLANE_DPB_V8 0xf360
#define S5P_FIMV_D_MV_BUFFER_V8 0xf460
#define S5P_FIMV_D_NUM_MV_V8 0xf134
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
index 10abaa50d7db..f6ed3eeda6ba 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
@@ -56,6 +56,7 @@
#define MFC_NO_INSTANCE_SET -1
#define MFC_ENC_CAP_PLANE_COUNT 1
#define MFC_ENC_OUT_PLANE_COUNT 2
+#define VB2_MAX_PLANE_COUNT 3
#define STUFF_BYTE 4
#define MFC_MAX_CTRLS 147
@@ -182,6 +183,7 @@ struct s5p_mfc_buf {
struct {
size_t luma;
size_t chroma;
+ size_t chroma_1;
} raw;
size_t stream;
} cookie;
@@ -682,6 +684,7 @@ struct s5p_mfc_ctx {
int luma_size;
int chroma_size;
+ int chroma_size_1;
int mv_size;
unsigned long consumed_stream;
@@ -747,6 +750,7 @@ struct s5p_mfc_ctx {
size_t scratch_buf_size;
int is_10bit;
int is_422;
+ int stride[VB2_MAX_PLANE_COUNT];
};
/*
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
index e219cbcd86d5..317f796fffa1 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
@@ -56,6 +56,20 @@ static struct s5p_mfc_fmt formats[] = {
.num_planes = 2,
.versions = MFC_V6PLUS_BITS,
},
+ {
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .codec_mode = S5P_MFC_CODEC_NONE,
+ .type = MFC_FMT_RAW,
+ .num_planes = 3,
+ .versions = MFC_V12_BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YVU420M,
+ .codec_mode = S5P_MFC_CODEC_NONE,
+ .type = MFC_FMT_RAW,
+ .num_planes = 3,
+ .versions = MFC_V12_BIT
+ },
{
.fourcc = V4L2_PIX_FMT_H264,
.codec_mode = S5P_MFC_CODEC_H264_DEC,
@@ -359,10 +373,15 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
/* Set pixelformat to the format in which MFC
outputs the decoded frame */
pix_mp->pixelformat = ctx->dst_fmt->fourcc;
- pix_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+ pix_mp->plane_fmt[0].bytesperline = ctx->stride[0];
pix_mp->plane_fmt[0].sizeimage = ctx->luma_size;
- pix_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+ pix_mp->plane_fmt[1].bytesperline = ctx->stride[1];
pix_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ pix_mp->plane_fmt[2].bytesperline = ctx->stride[2];
+ pix_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1;
+ }
} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
/* This is run on OUTPUT
The buffer contains compressed image
@@ -937,6 +956,9 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,
vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
/* Output plane count is 2 - one for Y and one for CbCr */
*plane_count = 2;
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ *plane_count = 3;
/* Setup buffer count */
if (*buf_count < ctx->pb_count)
*buf_count = ctx->pb_count;
@@ -955,12 +977,17 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,
vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
psize[0] = ctx->luma_size;
psize[1] = ctx->chroma_size;
-
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ psize[2] = ctx->chroma_size_1;
if (IS_MFCV6_PLUS(dev))
alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];
else
alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX];
alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX];
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ alloc_devs[2] = ctx->dev->mem_dev[BANK_L_CTX];
} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
ctx->state == MFCINST_INIT) {
psize[0] = ctx->dec_src_buf_size;
@@ -994,12 +1021,24 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb)
mfc_err("Plane buffer (CAPTURE) is too small\n");
return -EINVAL;
}
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ if (vb2_plane_size(vb, 2) < ctx->chroma_size_1) {
+ mfc_err("Plane buffer (CAPTURE) is too small\n");
+ return -EINVAL;
+ }
+ }
i = vb->index;
ctx->dst_bufs[i].b = vbuf;
ctx->dst_bufs[i].cookie.raw.luma =
vb2_dma_contig_plane_dma_addr(vb, 0);
ctx->dst_bufs[i].cookie.raw.chroma =
vb2_dma_contig_plane_dma_addr(vb, 1);
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ ctx->dst_bufs[i].cookie.raw.chroma_1 =
+ vb2_dma_contig_plane_dma_addr(vb, 2);
+ }
ctx->dst_bufs_cnt++;
} else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
if (IS_ERR_OR_NULL(ERR_PTR(
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index 197667ab1fbc..b761b9a31383 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -59,6 +59,20 @@ static struct s5p_mfc_fmt formats[] = {
.num_planes = 2,
.versions = MFC_V6PLUS_BITS,
},
+ {
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .codec_mode = S5P_MFC_CODEC_NONE,
+ .type = MFC_FMT_RAW,
+ .num_planes = 3,
+ .versions = MFC_V12_BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YVU420M,
+ .codec_mode = S5P_MFC_CODEC_NONE,
+ .type = MFC_FMT_RAW,
+ .num_planes = 3,
+ .versions = MFC_V12_BIT,
+ },
{
.fourcc = V4L2_PIX_FMT_H264,
.codec_mode = S5P_MFC_CODEC_H264_ENC,
@@ -1369,14 +1383,20 @@ static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
struct s5p_mfc_dev *dev = ctx->dev;
struct s5p_mfc_buf *dst_mb;
struct s5p_mfc_buf *src_mb;
- unsigned long src_y_addr, src_c_addr, dst_addr;
+ unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;
unsigned int dst_size;
src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ src_c_1_addr =
+ vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 2);
+ else
+ src_c_1_addr = 0;
s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx,
- src_y_addr, src_c_addr);
+ src_y_addr, src_c_addr, src_c_1_addr);
dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
@@ -1391,8 +1411,8 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
{
struct s5p_mfc_dev *dev = ctx->dev;
struct s5p_mfc_buf *mb_entry;
- unsigned long enc_y_addr = 0, enc_c_addr = 0;
- unsigned long mb_y_addr, mb_c_addr;
+ unsigned long enc_y_addr = 0, enc_c_addr = 0, enc_c_1_addr = 0;
+ unsigned long mb_y_addr, mb_c_addr, mb_c_1_addr;
int slice_type;
unsigned int strm_size;
@@ -1404,14 +1424,21 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));
if (slice_type >= 0) {
s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx,
- &enc_y_addr, &enc_c_addr);
+ &enc_y_addr, &enc_c_addr, &enc_c_1_addr);
list_for_each_entry(mb_entry, &ctx->src_queue, list) {
mb_y_addr = vb2_dma_contig_plane_dma_addr(
&mb_entry->b->vb2_buf, 0);
mb_c_addr = vb2_dma_contig_plane_dma_addr(
&mb_entry->b->vb2_buf, 1);
- if ((enc_y_addr == mb_y_addr) &&
- (enc_c_addr == mb_c_addr)) {
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ mb_c_1_addr = vb2_dma_contig_plane_dma_addr
+ (&mb_entry->b->vb2_buf, 2);
+ else
+ mb_c_1_addr = 0;
+ if ((enc_y_addr == mb_y_addr)
+ && (enc_c_addr == mb_c_addr)
+ && (enc_c_1_addr == mb_c_1_addr)) {
list_del(&mb_entry->list);
ctx->src_queue_cnt--;
vb2_buffer_done(&mb_entry->b->vb2_buf,
@@ -1424,8 +1451,15 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
&mb_entry->b->vb2_buf, 0);
mb_c_addr = vb2_dma_contig_plane_dma_addr(
&mb_entry->b->vb2_buf, 1);
- if ((enc_y_addr == mb_y_addr) &&
- (enc_c_addr == mb_c_addr)) {
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ mb_c_1_addr = vb2_dma_contig_plane_dma_addr(
+ &mb_entry->b->vb2_buf, 2);
+ else
+ mb_c_1_addr = 0;
+ if ((enc_y_addr == mb_y_addr)
+ && (enc_c_addr == mb_c_addr)
+ && (enc_c_1_addr == mb_c_1_addr)) {
list_del(&mb_entry->list);
ctx->ref_queue_cnt--;
vb2_buffer_done(&mb_entry->b->vb2_buf,
@@ -1549,10 +1583,15 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc;
pix_fmt_mp->num_planes = ctx->src_fmt->num_planes;
- pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+ pix_fmt_mp->plane_fmt[0].bytesperline = ctx->stride[0];
pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
- pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+ pix_fmt_mp->plane_fmt[1].bytesperline = ctx->stride[1];
pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ pix_fmt_mp->plane_fmt[2].bytesperline = ctx->stride[2];
+ pix_fmt_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1;
+ }
} else {
mfc_err("invalid buf type\n");
return -EINVAL;
@@ -1636,9 +1675,14 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx);
pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
- pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
+ pix_fmt_mp->plane_fmt[0].bytesperline = ctx->stride[0];
pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
- pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width;
+ pix_fmt_mp->plane_fmt[1].bytesperline = ctx->stride[1];
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ pix_fmt_mp->plane_fmt[2].bytesperline = ctx->stride[2];
+ pix_fmt_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1;
+ }
ctx->src_bufs_cnt = 0;
ctx->output_state = QUEUE_FREE;
@@ -2679,10 +2723,16 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,
psize[0] = ctx->luma_size;
psize[1] = ctx->chroma_size;
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ psize[2] = ctx->chroma_size_1;
if (IS_MFCV6_PLUS(dev)) {
alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];
alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX];
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ alloc_devs[2] = ctx->dev->mem_dev[BANK_L_CTX];
} else {
alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX];
alloc_devs[1] = ctx->dev->mem_dev[BANK_R_CTX];
@@ -2721,6 +2771,10 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb)
vb2_dma_contig_plane_dma_addr(vb, 0);
ctx->src_bufs[i].cookie.raw.chroma =
vb2_dma_contig_plane_dma_addr(vb, 1);
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ ctx->src_bufs[i].cookie.raw.chroma_1 =
+ vb2_dma_contig_plane_dma_addr(vb, 2);
ctx->src_bufs_cnt++;
} else {
mfc_err("invalid queue type: %d\n", vq->type);
@@ -2758,6 +2812,12 @@ static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)
mfc_err("plane size is too small for output\n");
return -EINVAL;
}
+ if ((ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) &&
+ (vb2_plane_size(vb, 2) < ctx->chroma_size_1)) {
+ mfc_err("plane size is too small for output\n");
+ return -EINVAL;
+ }
} else {
mfc_err("invalid queue type: %d\n", vq->type);
return -EINVAL;
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
index a005623e2daa..700704985c26 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
@@ -295,9 +295,11 @@ struct s5p_mfc_hw_ops {
int (*set_enc_stream_buffer)(struct s5p_mfc_ctx *ctx,
unsigned long addr, unsigned int size);
void (*set_enc_frame_buffer)(struct s5p_mfc_ctx *ctx,
- unsigned long y_addr, unsigned long c_addr);
+ unsigned long y_addr, unsigned long c_addr,
+ unsigned long c_1_addr);
void (*get_enc_frame_buffer)(struct s5p_mfc_ctx *ctx,
- unsigned long *y_addr, unsigned long *c_addr);
+ unsigned long *y_addr, unsigned long *c_addr,
+ unsigned long *c_1_addr);
void (*try_run)(struct s5p_mfc_dev *dev);
void (*clear_int_flags)(struct s5p_mfc_dev *dev);
int (*get_dspl_y_adr)(struct s5p_mfc_dev *dev);
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c
index 28a06dc343fd..fcfaf125a5a1 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c
@@ -516,7 +516,8 @@ static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx,
}
static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
- unsigned long y_addr, unsigned long c_addr)
+ unsigned long y_addr, unsigned long c_addr,
+ unsigned long c_1_addr)
{
struct s5p_mfc_dev *dev = ctx->dev;
@@ -525,7 +526,8 @@ static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
}
static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
- unsigned long *y_addr, unsigned long *c_addr)
+ unsigned long *y_addr, unsigned long *c_addr,
+ unsigned long *c_1_addr)
{
struct s5p_mfc_dev *dev = ctx->dev;
@@ -1210,7 +1212,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
if (list_empty(&ctx->src_queue)) {
/* send null frame */
s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->dma_base[BANK_R_CTX],
- dev->dma_base[BANK_R_CTX]);
+ dev->dma_base[BANK_R_CTX], 0);
src_mb = NULL;
} else {
src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
@@ -1220,7 +1222,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
/* send null frame */
s5p_mfc_set_enc_frame_buffer_v5(ctx,
dev->dma_base[BANK_R_CTX],
- dev->dma_base[BANK_R_CTX]);
+ dev->dma_base[BANK_R_CTX], 0);
ctx->state = MFCINST_FINISHING;
} else {
src_y_addr = vb2_dma_contig_plane_dma_addr(
@@ -1228,7 +1230,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
src_c_addr = vb2_dma_contig_plane_dma_addr(
&src_mb->b->vb2_buf, 1);
s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr,
- src_c_addr);
+ src_c_addr, 0);
if (src_mb->flags & MFC_BUF_FLAG_EOS)
ctx->state = MFCINST_FINISHING;
}
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 87bd10b34620..27c2ada381ec 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -506,16 +506,43 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
struct s5p_mfc_dev *dev = ctx->dev;
ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
+ ctx->chroma_size_1 = 0;
mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
"buffer dimensions: %dx%d\n", ctx->img_width,
ctx->img_height, ctx->buf_width, ctx->buf_height);
- ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
- ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
+ switch (ctx->dst_fmt->fourcc) {
+ case V4L2_PIX_FMT_NV12M:
+ case V4L2_PIX_FMT_NV21M:
+ ctx->stride[0] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12MT_HALIGN_V6);
+ ctx->stride[1] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12MT_HALIGN_V6);
+ ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
+ ctx->chroma_size = calc_plane(ctx->stride[1],
+ (ctx->img_height / 2));
+ break;
+ case V4L2_PIX_FMT_YUV420M:
+ case V4L2_PIX_FMT_YVU420M:
+ ctx->stride[0] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12MT_HALIGN_V6);
+ ctx->stride[1] = ALIGN(ctx->img_width / 2,
+ S5P_FIMV_NV12MT_HALIGN_V6);
+ ctx->stride[2] = ALIGN(ctx->img_width / 2,
+ S5P_FIMV_NV12MT_HALIGN_V6);
+ ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
+ ctx->chroma_size = calc_plane(ctx->stride[1],
+ (ctx->img_height / 2));
+ ctx->chroma_size_1 = calc_plane(ctx->stride[2],
+ (ctx->img_height / 2));
+ break;
+ }
+
if (IS_MFCV8_PLUS(ctx->dev)) {
/* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
+ ctx->chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
}
if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
@@ -546,15 +573,53 @@ static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
mb_width = MB_WIDTH(ctx->img_width);
mb_height = MB_HEIGHT(ctx->img_height);
- ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
- ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
- ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
-
- /* MFCv7 needs pad bytes for Luma and Chroma */
- if (IS_MFCV7_PLUS(ctx->dev)) {
+ if (IS_MFCV12(ctx->dev)) {
+ switch (ctx->src_fmt->fourcc) {
+ case V4L2_PIX_FMT_NV12M:
+ case V4L2_PIX_FMT_NV21M:
+ ctx->stride[0] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->stride[1] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->luma_size = ctx->stride[0] *
+ ALIGN(ctx->img_height, 16);
+ ctx->chroma_size = ctx->stride[0] *
+ ALIGN(ctx->img_height / 2, 16);
+ break;
+ case V4L2_PIX_FMT_YUV420M:
+ case V4L2_PIX_FMT_YVU420M:
+ ctx->stride[0] = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->stride[1] = ALIGN(ctx->img_width / 2,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->stride[2] = ALIGN(ctx->img_width / 2,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->luma_size = ctx->stride[0] *
+ ALIGN(ctx->img_height, 16);
+ ctx->chroma_size = ctx->stride[1] *
+ ALIGN(ctx->img_height / 2, 16);
+ ctx->chroma_size_1 = ctx->stride[2] *
+ ALIGN(ctx->img_height / 2, 16);
+ break;
+ }
ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
- ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
+ ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V12;
+ ctx->chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12;
+ } else {
+ ctx->buf_width = ALIGN(ctx->img_width,
+ S5P_FIMV_NV12M_HALIGN_V6);
+ ctx->stride[0] = ctx->buf_width;
+ ctx->stride[1] = ctx->buf_width;
+ ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
+ ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
+ ctx->chroma_size_1 = 0;
+ /* MFCv7 needs pad bytes for Luma and Chroma */
+ if (IS_MFCV7_PLUS(ctx->dev)) {
+ ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
+ ctx->chroma_size += MFC_LUMA_PAD_BYTES_V7;
+ }
}
+
}
/* Set registers for decoding stream buffer */
@@ -600,15 +665,21 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
-
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size);
writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
if (IS_MFCV8_PLUS(dev)) {
- writel(ctx->img_width,
+ writel(ctx->stride[0],
mfc_regs->d_first_plane_dpb_stride_size);
- writel(ctx->img_width,
+ writel(ctx->stride[1],
mfc_regs->d_second_plane_dpb_stride_size);
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ writel(ctx->stride[2],
+ mfc_regs->d_third_plane_dpb_stride_size);
}
buf_addr1 += ctx->scratch_buf_size;
@@ -637,6 +708,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
ctx->dst_bufs[i].cookie.raw.chroma);
writel(ctx->dst_bufs[i].cookie.raw.chroma,
mfc_regs->d_second_plane_dpb + i * 4);
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ mfc_debug(2, "\tChroma_1 %d: %zx\n", i,
+ ctx->dst_bufs[i].cookie.raw.chroma_1);
+ writel(ctx->dst_bufs[i].cookie.raw.chroma_1,
+ mfc_regs->d_third_plane_dpb + i * 4);
+ }
}
if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
@@ -695,20 +773,24 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
}
static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
- unsigned long y_addr, unsigned long c_addr)
+ unsigned long y_addr, unsigned long c_addr,
+ unsigned long c_1_addr)
{
struct s5p_mfc_dev *dev = ctx->dev;
const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
writel(y_addr, mfc_regs->e_source_first_plane_addr);
writel(c_addr, mfc_regs->e_source_second_plane_addr);
+ writel(c_1_addr, mfc_regs->e_source_third_plane_addr);
mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
+ mfc_debug(2, "enc src cr buf addr: 0x%08lx\n", c_1_addr);
}
static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
- unsigned long *y_addr, unsigned long *c_addr)
+ unsigned long *y_addr, unsigned long *c_addr,
+ unsigned long *c_1_addr)
{
struct s5p_mfc_dev *dev = ctx->dev;
const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
@@ -716,12 +798,17 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
*y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
*c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ *c_1_addr = readl(mfc_regs->e_encoded_source_third_plane_addr);
+ else
+ *c_1_addr = 0;
enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);
- mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
+ mfc_debug(2, "recon c addr: 0x%08lx c_addr: 0x%08lx\n", enc_recon_c_addr, *c_addr);
}
/* Set encoding ref & codec buffer */
@@ -898,6 +985,20 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
writel(reg, mfc_regs->e_enc_options);
/* 0: NV12(CbCr), 1: NV21(CrCb) */
writel(0x0, mfc_regs->pixel_format);
+ } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
+ /* 0: Linear, 1: 2D tiled*/
+ reg = readl(mfc_regs->e_enc_options);
+ reg &= ~(0x1 << 7);
+ writel(reg, mfc_regs->e_enc_options);
+ /* 2: YV12(CrCb), 3: I420(CrCb) */
+ writel(0x2, mfc_regs->pixel_format);
+ } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M) {
+ /* 0: Linear, 1: 2D tiled*/
+ reg = readl(mfc_regs->e_enc_options);
+ reg &= ~(0x1 << 7);
+ writel(reg, mfc_regs->e_enc_options);
+ /* 2: YV12(CrCb), 3: I420(CrCb) */
+ writel(0x3, mfc_regs->pixel_format);
}
/* memory structure recon. frame */
@@ -1804,8 +1905,12 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
else
writel(reg, mfc_regs->d_dec_options);
- /* 0: NV12(CbCr), 1: NV21(CrCb) */
- if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
+ /* 0: NV12(CbCr), 1: NV21(CrCb), 2: YV12(CrCb), 3: I420(CbCr) */
+ if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M)
+ writel(0x3, mfc_regs->pixel_format);
+ else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ writel(0x2, mfc_regs->pixel_format);
+ else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
writel(0x1, mfc_regs->pixel_format);
else
writel(0x0, mfc_regs->pixel_format);
@@ -1891,8 +1996,12 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
/* Set stride lengths for v7 & above */
if (IS_MFCV7_PLUS(dev)) {
- writel(ctx->img_width, mfc_regs->e_source_first_plane_stride);
- writel(ctx->img_width, mfc_regs->e_source_second_plane_stride);
+ writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride);
+ writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride);
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ writel(ctx->stride[2],
+ mfc_regs->e_source_third_plane_stride);
}
writel(ctx->inst_no, mfc_regs->instance_id);
@@ -2001,7 +2110,7 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
struct s5p_mfc_dev *dev = ctx->dev;
struct s5p_mfc_buf *dst_mb;
struct s5p_mfc_buf *src_mb;
- unsigned long src_y_addr, src_c_addr, dst_addr;
+ unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;
/*
unsigned int src_y_size, src_c_size;
*/
@@ -2019,22 +2128,29 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
if (list_empty(&ctx->src_queue)) {
/* send null frame */
- s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
+ s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
src_mb = NULL;
} else {
src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
src_mb->flags |= MFC_BUF_FLAG_USED;
if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
- s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
+ s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
ctx->state = MFCINST_FINISHING;
} else {
src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
+ if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M ||
+ ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
+ src_c_1_addr = vb2_dma_contig_plane_dma_addr
+ (&src_mb->b->vb2_buf, 2);
+ else
+ src_c_1_addr = 0;
mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
- s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
+ s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr,
+ src_c_addr, src_c_1_addr);
if (src_mb->flags & MFC_BUF_FLAG_EOS)
ctx->state = MFCINST_FINISHING;
}
@@ -2560,6 +2676,8 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
R(e_encoded_source_second_plane_addr,
S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
+ R(e_encoded_source_third_plane_addr,
+ S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7);
R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
if (!IS_MFCV8_PLUS(dev))
@@ -2574,16 +2692,20 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
+ R(d_third_plane_dpb_size, S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8);
R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
R(d_first_plane_dpb_stride_size,
S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
R(d_second_plane_dpb_stride_size,
S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
+ R(d_third_plane_dpb_stride_size,
+ S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8);
R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
+ R(d_third_plane_dpb, S5P_FIMV_D_THIRD_PLANE_DPB_V8);
R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
--
2.17.1
From: Smitha T Murthy <[email protected]>
Add dmabuf support for mfc encoder
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../media/platform/samsung/s5p-mfc/s5p_mfc.c | 4 ++--
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 21 +++++++++++--------
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
index fe07112f013f..ad04ec68921b 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
@@ -850,7 +850,7 @@ static int s5p_mfc_open(struct file *file)
q->io_modes = VB2_MMAP;
q->ops = get_dec_queue_ops();
} else if (vdev == dev->vfd_enc) {
- q->io_modes = VB2_MMAP | VB2_USERPTR;
+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->ops = get_enc_queue_ops();
} else {
ret = -ENOENT;
@@ -877,7 +877,7 @@ static int s5p_mfc_open(struct file *file)
q->io_modes = VB2_MMAP;
q->ops = get_dec_queue_ops();
} else if (vdev == dev->vfd_enc) {
- q->io_modes = VB2_MMAP | VB2_USERPTR;
+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
q->ops = get_enc_queue_ops();
} else {
ret = -ENOENT;
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index f953a3ed7f20..22f6ebc28e40 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -1705,9 +1705,10 @@ static int vidioc_reqbufs(struct file *file, void *priv,
struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
int ret = 0;
- /* if memory is not mmp or userptr return error */
+ /* if memory is not mmp or userptr or dmabuf return error */
if ((reqbufs->memory != V4L2_MEMORY_MMAP) &&
- (reqbufs->memory != V4L2_MEMORY_USERPTR))
+ (reqbufs->memory != V4L2_MEMORY_USERPTR) &&
+ (reqbufs->memory != V4L2_MEMORY_DMABUF))
return -EINVAL;
if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
if (reqbufs->count == 0) {
@@ -1784,9 +1785,10 @@ static int vidioc_querybuf(struct file *file, void *priv,
struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
int ret = 0;
- /* if memory is not mmp or userptr return error */
+ /* if memory is not mmp or userptr or dmabuf return error */
if ((buf->memory != V4L2_MEMORY_MMAP) &&
- (buf->memory != V4L2_MEMORY_USERPTR))
+ (buf->memory != V4L2_MEMORY_USERPTR) &&
+ (buf->memory != V4L2_MEMORY_DMABUF))
return -EINVAL;
if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
if (ctx->state != MFCINST_GOT_INST) {
@@ -2842,11 +2844,12 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
S5P_MFC_R2H_CMD_SEQ_DONE_RET,
0);
}
-
- if (ctx->src_bufs_cnt < ctx->pb_count) {
- mfc_err("Need minimum %d OUTPUT buffers\n",
- ctx->pb_count);
- return -ENOBUFS;
+ if (q->memory != V4L2_MEMORY_DMABUF) {
+ if (ctx->src_bufs_cnt < ctx->pb_count) {
+ mfc_err("Need minimum %d OUTPUT buffers\n",
+ ctx->pb_count);
+ return -ENOBUFS;
+ }
}
}
--
2.17.1
From: Smitha T Murthy <[email protected]>
This patch allows allocation of DPB buffers based on MFC requirement
so codec buffers allocations has been moved after state
MFCINST_HEAD_PRODUCED. It is taken care that codec buffer allocation
is performed in process context from userspace IOCTL call.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 17 ++---------------
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 9 ++++++++-
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index 22f6ebc28e40..425dcab0cd1c 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -1340,7 +1340,6 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
struct s5p_mfc_dev *dev = ctx->dev;
struct s5p_mfc_enc_params *p = &ctx->enc_params;
struct s5p_mfc_buf *dst_mb;
- unsigned int enc_pb_count;
if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) {
if (!list_empty(&ctx->dst_queue)) {
@@ -1362,10 +1361,8 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
set_work_bit_irqsave(ctx);
s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
} else {
- enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops,
+ ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops,
get_enc_dpb_count, dev);
- if (ctx->pb_count < enc_pb_count)
- ctx->pb_count = enc_pb_count;
if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) {
ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
get_e_min_scratch_buf_size, dev);
@@ -1731,14 +1728,6 @@ static int vidioc_reqbufs(struct file *file, void *priv,
}
ctx->capture_state = QUEUE_BUFS_REQUESTED;
- ret = s5p_mfc_hw_call(ctx->dev->mfc_ops,
- alloc_codec_buffers, ctx);
- if (ret) {
- mfc_err("Failed to allocate encoding buffers\n");
- reqbufs->count = 0;
- ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
- return -ENOMEM;
- }
} else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
if (reqbufs->count == 0) {
mfc_debug(2, "Freeing buffers\n");
@@ -1754,15 +1743,13 @@ static int vidioc_reqbufs(struct file *file, void *priv,
return -EINVAL;
}
- if (IS_MFCV6_PLUS(dev)) {
+ if (IS_MFCV6_PLUS(dev) && (!IS_MFCV12(dev))) {
/* Check for min encoder buffers */
if (ctx->pb_count &&
(reqbufs->count < ctx->pb_count)) {
reqbufs->count = ctx->pb_count;
mfc_debug(2, "Minimum %d output buffers needed\n",
ctx->pb_count);
- } else {
- ctx->pb_count = reqbufs->count;
}
}
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index c4953419be0e..c00debe5db76 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -377,7 +377,6 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
default:
break;
}
-
/* Allocate only if memory from bank 1 is necessary */
if (ctx->bank1.size > 0) {
ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);
@@ -2255,6 +2254,14 @@ static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
struct s5p_mfc_dev *dev = ctx->dev;
int ret;
+ ret = s5p_mfc_hw_call(ctx->dev->mfc_ops,
+ alloc_codec_buffers, ctx);
+ if (ret) {
+ mfc_err("Failed to allocate encoding buffers\n");
+ return -ENOMEM;
+ }
+ mfc_debug(2, "Allocated Internal Encoding Buffers\n");
+
dev->curr_ctx = ctx->num;
ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
if (ret) {
--
2.17.1
From: Smitha T Murthy <[email protected]>
In MFCv12, the rc configs are changed with support for CBR loose,
CBR tight and Variable Bitrate (VBR) added.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 22 +++++++++++++++----
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 1 +
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 27c2ada381ec..2194df7b6fbf 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -1037,10 +1037,24 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
/* reaction coefficient */
if (p->rc_frame) {
- if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
- writel(1, mfc_regs->e_rc_mode);
- else /* loose CBR */
- writel(2, mfc_regs->e_rc_mode);
+ if (IS_MFCV12(dev)) {
+ /* loose CBR */
+ if (p->rc_reaction_coeff < LOOSE_CBR_MAX)
+ writel(1, mfc_regs->e_rc_mode);
+ /* tight CBR */
+ else if (p->rc_reaction_coeff < TIGHT_CBR_MAX)
+ writel(0, mfc_regs->e_rc_mode);
+ /* VBR */
+ else
+ writel(2, mfc_regs->e_rc_mode);
+ } else {
+ /* tight CBR */
+ if (p->rc_reaction_coeff < TIGHT_CBR_MAX)
+ writel(1, mfc_regs->e_rc_mode);
+ /* loose CBR */
+ else
+ writel(2, mfc_regs->e_rc_mode);
+ }
}
/* seq header ctrl */
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
index 30269f3e68e8..24752a712fbf 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
@@ -40,6 +40,7 @@
#define ENC_H264_LEVEL_MAX 42
#define ENC_MPEG4_VOP_TIME_RES_MAX ((1 << 16) - 1)
#define FRAME_DELTA_H264_H263 1
+#define LOOSE_CBR_MAX 5
#define TIGHT_CBR_MAX 10
#define ENC_HEVC_RC_FRAME_RATE_MAX ((1 << 16) - 1)
#define ENC_HEVC_QP_INDEX_MIN -12
--
2.17.1
From: Smitha T Murthy <[email protected]>
Add MFC DT node and reserve memory node for MFC usage.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..b2f7345d2cba 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -340,6 +340,18 @@
#clock-cells = <0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mfc_left: region@84000000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x84000000 0 0x8000000>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -832,6 +844,15 @@
clock-names = "fin_pll", "mct";
};
+ mfc: mfc@12880000 {
+ compatible = "tesla,fsd-mfc";
+ reg = <0x0 0x12880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "mfc";
+ clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>;
+ memory-region = <&mfc_left>;
+ };
+
ufs: ufs@15120000 {
compatible = "tesla,fsd-ufs";
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
--
2.17.1
From: Smitha T Murthy <[email protected]>
In MFCv12, some section of firmware gets updated at each MFC run.
Hence we need to reload original firmware for each run at the start.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
index 877e5bceb75b..a70283d4c519 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
@@ -51,8 +51,9 @@ int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
* into kernel. */
mfc_debug_enter();
- if (dev->fw_get_done)
- return 0;
+ if (!IS_MFCV12(dev))
+ if (dev->fw_get_done)
+ return 0;
for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
if (!dev->variant->fw_name[i])
--
2.17.1
Hi All,
Please find the attached v4l2-compliance complete log(mfc encoder and decoder) along with this mail for reference.
Thanks,
Aakarsh
> -----Original Message-----
> From: aakarsh jain [mailto:[email protected]]
> Sent: 11 October 2022 17:55
> To: [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: [Patch v3 00/15] Add MFC v12 support.
>
> This patch series adds MFC v12 support. MFC v12 is used in Tesla FSD SoC.
>
> This adds support for following:
>
> * Add support for VP9 encoder
> * Add support for YV12 and I420 format (3-plane)
> * Add support for Rate Control, UHD and DMABUF for encoder
> * Add support for DPB buffers allocation based on MFC requirement
> * Update Documentation for control id definitions
>
> Changes since v2:
> - Addressed review comments by Rob Herring.
> - Addressed review comments by Krzysztof Kozlowski.
> - Addressed review comments by Andi Shyti.
>
> Smitha T Murthy (15):
> dt-bindings: media: s5p-mfc: Add new DT schema for MFC
> dt-bindings: media: s5p-mfc: Add mfcv12 variant
> media: s5p-mfc: Rename IS_MFCV10 macro
> media: s5p-mfc: Add initial support for MFCv12
> Documention: v4l: Documentation for VP9 CIDs.
> media: v4l2: Add v4l2 control IDs for VP9 encoder.
> media: s5p-mfc: Add support for VP9 encoder.
> media: s5p-mfc: Add YV12 and I420 multiplanar format support
> media: s5p-mfc: Add support for rate controls in MFCv12
> media: s5p-mfc: Add support for UHD encoding.
> media: s5p-mfc: Add support for DMABUF for encoder
> media: s5p-mfc: Set context for valid case before calling try_run
> media: s5p-mfc: Load firmware for each run in MFCv12.
> media: s5p-mfc: DPB Count Independent of VIDIOC_REQBUF
> arm64: dts: fsd: Add MFC related DT enteries
>
> .../devicetree/bindings/media/s5p-mfc.txt | 75 ---------
> .../bindings/media/samsung,s5p-mfc.yaml | 164 ++++++++++++++++++
> .../media/v4l/ext-ctrls-codec.rst | 167 +++++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 21 +
> .../platform/samsung/s5p-mfc/regs-mfc-v12.h | 60 +++
> .../platform/samsung/s5p-mfc/regs-mfc-v7.h | 1 +
> .../platform/samsung/s5p-mfc/regs-mfc-v8.h | 3 +
> .../media/platform/samsung/s5p-mfc/s5p_mfc.c | 36 +-
> .../platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c | 3 +
> .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 56 ++-
> .../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 9 +-
> .../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 51 ++-
> .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 410 +++++++++++++++--
> .../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 16 +-
> .../platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c | 12 +-
> .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 435
> ++++++++++++++++--
> .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 7 +-
> drivers/media/v4l2-core/v4l2-ctrls-defs.c | 44 ++
> include/uapi/linux/v4l2-controls.h | 33 ++
> 19 files changed, 1349 insertions(+), 203 deletions(-) create mode 100644
> Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> create mode 100644 drivers/media/platform/samsung/s5p-mfc/regs-mfc-
> v12.h
>
> --
> 2.17.1
From: Smitha T Murthy <[email protected]>
Add support for MFCv12, with a new register file and necessary hw
control, decoder, encoder and structural changes. Add luma dbp, chroma
dpb and mv sizes for each codec as per the UM for MFCv12, along with
appropriate alignment.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Aakarsh Jain <[email protected]>
---
.../platform/samsung/s5p-mfc/regs-mfc-v12.h | 50 +++++++++++
.../media/platform/samsung/s5p-mfc/s5p_mfc.c | 30 +++++++
.../platform/samsung/s5p-mfc/s5p_mfc_common.h | 15 +++-
.../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 2 +-
.../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 6 +-
.../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 5 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 8 +-
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 83 ++++++++++++++++---
.../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 6 +-
9 files changed, 175 insertions(+), 30 deletions(-)
create mode 100644 drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
new file mode 100644
index 000000000000..6c68a45082d0
--- /dev/null
+++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Register definition file for Samsung MFC V12.x Interface (FIMV) driver
+ *
+ * Copyright (c) 2020 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ */
+
+#ifndef _REGS_MFC_V12_H
+#define _REGS_MFC_V12_H
+
+#include <linux/sizes.h>
+#include "regs-mfc-v10.h"
+
+/* MFCv12 Context buffer sizes */
+#define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K)
+#define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M)
+#define MFC_OTHER_DEC_CTX_BUF_SIZE_V12 (30 * SZ_1K)
+#define MFC_H264_ENC_CTX_BUF_SIZE_V12 (100 * SZ_1K)
+#define MFC_HEVC_ENC_CTX_BUF_SIZE_V12 (40 * SZ_1K)
+#define MFC_OTHER_ENC_CTX_BUF_SIZE_V12 (25 * SZ_1K)
+
+/* MFCv12 variant defines */
+#define MAX_FW_SIZE_V12 (SZ_1M)
+#define MAX_CPB_SIZE_V12 (7 * SZ_1M)
+#define MFC_VERSION_V12 0xC0
+#define MFC_NUM_PORTS_V12 1
+#define S5P_FIMV_CODEC_VP9_ENC 27
+
+/* Encoder buffer size for MFCv12 */
+#define ENC_V120_BASE_SIZE(x, y) \
+ (((x + 3) * (y + 3) * 8) \
+ + (((y * 64) + 2304) * (x + 7) / 8))
+
+#define ENC_V120_H264_ME_SIZE(x, y) \
+ ALIGN((ENC_V120_BASE_SIZE(x, y) \
+ + (DIV_ROUND_UP(x * y, 64) * 32)), 256)
+
+#define ENC_V120_MPEG4_ME_SIZE(x, y) \
+ ALIGN((ENC_V120_BASE_SIZE(x, y) \
+ + (DIV_ROUND_UP(x * y, 128) * 16)), 256)
+
+#define ENC_V120_VP8_ME_SIZE(x, y) \
+ ALIGN(ENC_V120_BASE_SIZE(x, y), 256)
+
+#define ENC_V120_HEVC_ME_SIZE(x, y) \
+ ALIGN((((x + 3) * (y + 3) * 32) \
+ + (((y * 128) + 2304) * (x + 3) / 4)), 256)
+
+#endif /*_REGS_MFC_V12_H*/
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
index fca5c6405eec..fe07112f013f 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
@@ -775,6 +775,8 @@ static int s5p_mfc_open(struct file *file)
INIT_LIST_HEAD(&ctx->dst_queue);
ctx->src_queue_cnt = 0;
ctx->dst_queue_cnt = 0;
+ ctx->is_422 = 0;
+ ctx->is_10bit = 0;
/* Get context number */
ctx->num = 0;
while (dev->ctx[ctx->num]) {
@@ -1637,6 +1639,31 @@ static struct s5p_mfc_variant mfc_drvdata_v10 = {
.fw_name[0] = "s5p-mfc-v10.fw",
};
+static struct s5p_mfc_buf_size_v6 mfc_buf_size_v12 = {
+ .dev_ctx = MFC_CTX_BUF_SIZE_V12,
+ .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V12,
+ .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V12,
+ .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V12,
+ .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V12,
+ .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V12,
+};
+
+static struct s5p_mfc_buf_size buf_size_v12 = {
+ .fw = MAX_FW_SIZE_V12,
+ .cpb = MAX_CPB_SIZE_V12,
+ .priv = &mfc_buf_size_v12,
+};
+
+static struct s5p_mfc_variant mfc_drvdata_v12 = {
+ .version = MFC_VERSION_V12,
+ .version_bit = MFC_V12_BIT,
+ .port_num = MFC_NUM_PORTS_V12,
+ .buf_size = &buf_size_v12,
+ .fw_name[0] = "s5p-mfc-v12.fw",
+ .clk_names = {"mfc"},
+ .num_clocks = 1,
+};
+
static const struct of_device_id exynos_mfc_match[] = {
{
.compatible = "samsung,mfc-v5",
@@ -1656,6 +1683,9 @@ static const struct of_device_id exynos_mfc_match[] = {
}, {
.compatible = "samsung,mfc-v10",
.data = &mfc_drvdata_v10,
+ }, {
+ .compatible = "tesla,fsd-mfc",
+ .data = &mfc_drvdata_v12,
},
{},
};
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
index e6ec4a43b290..dd2e9f7704ab 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
@@ -19,7 +19,7 @@
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-v4l2.h>
#include "regs-mfc.h"
-#include "regs-mfc-v10.h"
+#include "regs-mfc-v12.h"
#define S5P_MFC_NAME "s5p-mfc"
@@ -720,6 +720,8 @@ struct s5p_mfc_ctx {
struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
struct v4l2_ctrl_handler ctrl_handler;
size_t scratch_buf_size;
+ int is_10bit;
+ int is_422;
};
/*
@@ -775,6 +777,7 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70)
#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80)
#define IS_MFCV10_PLUS(dev) (dev->variant->version >= 0xA0)
+#define IS_MFCV12(dev) (dev->variant->version >= 0xC0)
#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev))
#define MFC_V5_BIT BIT(0)
@@ -782,11 +785,15 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
#define MFC_V7_BIT BIT(2)
#define MFC_V8_BIT BIT(3)
#define MFC_V10_BIT BIT(5)
+#define MFC_V12_BIT BIT(7)
#define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
- MFC_V8_BIT | MFC_V10_BIT)
+ MFC_V8_BIT | MFC_V10_BIT | MFC_V12_BIT)
#define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
- MFC_V10_BIT)
-#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
+ MFC_V10_BIT | MFC_V12_BIT)
+#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT | \
+ MFC_V12_BIT)
+
+#define MFC_V10PLUS_BITS (MFC_V10_BIT | MFC_V12_BIT)
#endif /* S5P_MFC_COMMON_H_ */
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
index ffe9f7e79eca..877e5bceb75b 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c
@@ -130,7 +130,7 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev)
mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
/* check bus reset control before reset */
- if (dev->risc_on)
+ if (dev->risc_on && !IS_MFCV12(dev))
if (s5p_mfc_bus_reset(dev))
return -EIO;
/* Reset
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
index 268ffe4da53c..e219cbcd86d5 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c
@@ -146,7 +146,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_FIMV_CODEC_HEVC_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
- .versions = MFC_V10_BIT,
+ .versions = MFC_V10PLUS_BITS,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION |
V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM,
},
@@ -155,7 +155,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_FIMV_CODEC_VP9_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
- .versions = MFC_V10_BIT,
+ .versions = MFC_V10PLUS_BITS,
.flags = V4L2_FMT_FLAG_DYN_RESOLUTION,
},
};
@@ -355,7 +355,7 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
pix_mp->width = ctx->buf_width;
pix_mp->height = ctx->buf_height;
pix_mp->field = V4L2_FIELD_NONE;
- pix_mp->num_planes = 2;
+ pix_mp->num_planes = ctx->dst_fmt->num_planes;
/* Set pixelformat to the format in which MFC
outputs the decoded frame */
pix_mp->pixelformat = ctx->dst_fmt->fourcc;
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
index b65e506665af..143d95fe2f89 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c
@@ -92,7 +92,7 @@ static struct s5p_mfc_fmt formats[] = {
.codec_mode = S5P_FIMV_CODEC_HEVC_ENC,
.type = MFC_FMT_ENC,
.num_planes = 1,
- .versions = MFC_V10_BIT,
+ .versions = MFC_V10PLUS_BITS,
},
};
@@ -1179,7 +1179,8 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) {
ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
get_e_min_scratch_buf_size, dev);
- ctx->bank1.size += ctx->scratch_buf_size;
+ if (!IS_MFCV12(dev))
+ ctx->bank1.size += ctx->scratch_buf_size;
}
ctx->state = MFCINST_HEAD_PRODUCED;
}
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
index b9831275f3ab..87ac56756a16 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h
@@ -166,9 +166,9 @@ struct s5p_mfc_regs {
void __iomem *d_decoded_third_addr;/* only v7 */
void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */
void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */
- void __iomem *d_min_scratch_buffer_size; /* v10 */
- void __iomem *d_static_buffer_addr; /* v10 */
- void __iomem *d_static_buffer_size; /* v10 */
+ void __iomem *d_min_scratch_buffer_size; /* v10 and v12 */
+ void __iomem *d_static_buffer_addr; /* v10 and v12 */
+ void __iomem *d_static_buffer_size; /* v10 and v12 */
/* encoder registers */
void __iomem *e_frame_width;
@@ -268,7 +268,7 @@ struct s5p_mfc_regs {
void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */
void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
- void __iomem *e_min_scratch_buffer_size; /* v10 */
+ void __iomem *e_min_scratch_buffer_size; /* v10 and v12 */
void __iomem *e_num_t_layer; /* v10 */
void __iomem *e_hier_qp_layer0; /* v10 */
void __iomem *e_hier_bit_rate_layer0; /* v10 */
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
index 728d255e65fc..5d14ccf8b4fe 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
@@ -60,12 +60,14 @@ static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
{
struct s5p_mfc_dev *dev = ctx->dev;
- unsigned int mb_width, mb_height;
+ unsigned int mb_width, mb_height, width64, height32;
unsigned int lcu_width = 0, lcu_height = 0;
int ret;
mb_width = MB_WIDTH(ctx->img_width);
mb_height = MB_HEIGHT(ctx->img_height);
+ width64 = ALIGN(ctx->img_width, 64);
+ height32 = ALIGN(ctx->img_height, 32);
if (ctx->type == MFCINST_DECODER) {
mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
@@ -82,7 +84,44 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
S5P_FIMV_TMV_BUFFER_ALIGN_V6);
- if (IS_MFCV10_PLUS(dev)) {
+ if (IS_MFCV12(dev)) {
+ lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
+ lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
+ if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC &&
+ ctx->is_10bit) {
+ ctx->luma_dpb_size =
+ width64 * height32 +
+ ALIGN(DIV_ROUND_UP(lcu_width * 32, 4),
+ 16) * height32 + 128;
+ if (ctx->is_422)
+ ctx->chroma_dpb_size =
+ ctx->luma_dpb_size;
+ else
+ ctx->chroma_dpb_size =
+ width64 * height32 / 2 +
+ ALIGN(DIV_ROUND_UP(lcu_width *
+ 32, 4), 16) * height32 / 2 + 128;
+ } else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC &&
+ ctx->is_10bit) {
+ ctx->luma_dpb_size =
+ ALIGN(ctx->img_width * 2, 128) *
+ height32 + 64;
+ ctx->chroma_dpb_size =
+ ALIGN(ctx->img_width * 2, 128) *
+ height32 / 2 + 64;
+ } else {
+ ctx->luma_dpb_size =
+ width64 * height32 + 64;
+ if (ctx->is_422)
+ ctx->chroma_dpb_size =
+ ctx->luma_dpb_size;
+ else
+ ctx->chroma_dpb_size =
+ width64 * height32 / 2 + 64;
+ }
+ ctx->luma_dpb_size = ALIGN(ctx->luma_dpb_size + 256, SZ_2K);
+ ctx->chroma_dpb_size = ALIGN(ctx->chroma_dpb_size + 256, SZ_2K);
+ } else if (IS_MFCV10_PLUS(dev)) {
lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
@@ -230,7 +269,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
DEC_VP9_STATIC_BUFFER_SIZE;
break;
case S5P_MFC_CODEC_H264_ENC:
- if (IS_MFCV10_PLUS(dev)) {
+ if (IS_MFCV12(dev)) {
+ mfc_debug(2, "Use min scratch buffer size\n");
+ ctx->me_buffer_size =
+ ENC_V120_H264_ME_SIZE(mb_width, mb_height);
+ } else if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
@@ -254,7 +297,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
break;
case S5P_MFC_CODEC_MPEG4_ENC:
case S5P_MFC_CODEC_H263_ENC:
- if (IS_MFCV10_PLUS(dev)) {
+ if (IS_MFCV12(dev)) {
+ mfc_debug(2, "Use min scratch buffer size\n");
+ ctx->me_buffer_size =
+ ENC_V120_MPEG4_ME_SIZE(mb_width, mb_height);
+ } else if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
@@ -273,7 +320,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->bank2.size = 0;
break;
case S5P_MFC_CODEC_VP8_ENC:
- if (IS_MFCV10_PLUS(dev)) {
+ if (IS_MFCV12(dev)) {
+ mfc_debug(2, "Use min scratch buffer size\n");
+ ctx->me_buffer_size =
+ ENC_V120_VP8_ME_SIZE(mb_width, mb_height);
+ } else if (IS_MFCV10_PLUS(dev)) {
mfc_debug(2, "Use min scratch buffer size\n");
ctx->me_buffer_size =
ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
@@ -297,9 +348,14 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->bank2.size = 0;
break;
case S5P_MFC_CODEC_HEVC_ENC:
+ if (IS_MFCV12(dev))
+ ctx->me_buffer_size =
+ ENC_V120_HEVC_ME_SIZE(lcu_width, lcu_height);
+ else
+ ctx->me_buffer_size =
+ ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width,
+ lcu_height), 16);
mfc_debug(2, "Use min scratch buffer size\n");
- ctx->me_buffer_size =
- ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
ctx->bank1.size =
ctx->scratch_buf_size + ctx->tmv_buffer_size +
@@ -452,12 +508,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
- if (IS_MFCV10_PLUS(dev)) {
- ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
- ctx->img_height);
+ if (IS_MFCV12(dev)) {
+ ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width,
+ ctx->img_height, 1024);
+ } else if (IS_MFCV10_PLUS(dev)) {
+ ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width,
+ ctx->img_height, 512);
} else {
- ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
- ctx->img_height);
+ ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width,
+ ctx->img_height, 128);
}
} else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width,
diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
index e4dd03c5454c..30269f3e68e8 100644
--- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h
@@ -19,10 +19,8 @@
#define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, 16)
#define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16)
-#define S5P_MFC_DEC_MV_SIZE_V6(x, y) (MB_WIDTH(x) * \
- (((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
-#define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \
- (((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
+#define S5P_MFC_DEC_MV_SIZE(x, y, offset) (MB_WIDTH(x) * \
+ (((MB_HEIGHT(y)+1)/2)*2) * 64 + offset)
#define S5P_MFC_LCU_WIDTH(x_size) DIV_ROUND_UP(x_size, 32)
#define S5P_MFC_LCU_HEIGHT(y_size) DIV_ROUND_UP(y_size, 32)
--
2.17.1
Hi aakarsh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on media-tree/master]
[also build test WARNING on robh/for-next arm/for-next arm64/for-next/core kvmarm/next rockchip/for-next shawnguo/for-next soc/for-next linus/master v6.0 next-20221012]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/aakarsh-jain/dt-bindings-media-s5p-mfc-Add-new-DT-schema-for-MFC/20221012-115313
base: git://linuxtv.org/media_tree.git master
config: loongarch-allyesconfig
compiler: loongarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f20d380a7e03f8535b3991efd821fc32fe2baf6e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review aakarsh-jain/dt-bindings-media-s5p-mfc-Add-new-DT-schema-for-MFC/20221012-115313
git checkout f20d380a7e03f8535b3991efd821fc32fe2baf6e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=loongarch SHELL=/bin/bash drivers/media/platform/samsung/s5p-mfc/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c:1667:5: warning: no previous prototype for 's5p_mfc_set_enc_params_vp9' [-Wmissing-prototypes]
1667 | int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/s5p_mfc_set_enc_params_vp9 +1667 drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1666
> 1667 int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
1668 {
1669 struct s5p_mfc_dev *dev = ctx->dev;
1670 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1671 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1672 struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9;
1673 unsigned int reg = 0;
1674 int i;
1675
1676 mfc_debug_enter();
1677
1678 s5p_mfc_set_enc_params(ctx);
1679
1680 /* profile*/
1681 reg = 0;
1682 reg |= (p_vp9->vp9_profile);
1683 writel(reg, mfc_regs->e_picture_profile);
1684
1685 reg = 0;
1686 reg |= ((p_vp9->ivf_header & 0x1) << 12);
1687 reg |= ((p_vp9->hier_qp_enable & 0x1) << 11);
1688 reg |= (p_vp9->max_partition_depth & 0x1) << 3;
1689 reg |= (p_vp9->intra_pu_split_disable & 0x1) << 1;
1690 reg |= (p_vp9->num_refs_for_p - 1) & 0x1;
1691 writel(reg, mfc_regs->e_vp9_options);
1692
1693 reg = 0;
1694 reg |= (p_vp9->vp9_goldenframesel & 0x1);
1695 reg |= (p_vp9->vp9_gfrefreshperiod & 0xffff) << 1;
1696 writel(reg, mfc_regs->e_vp9_golden_frame_option);
1697
1698 reg = 0;
1699 if (p_vp9->num_hier_layer) {
1700 reg |= p_vp9->num_hier_layer & 0x3;
1701 writel(reg, mfc_regs->e_num_t_layer);
1702 /* QP value for each layer */
1703 if (p_vp9->hier_qp_enable) {
1704 for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
1705 writel(p_vp9->hier_qp_layer[i],
1706 mfc_regs->e_hier_qp_layer0
1707 + i * 4);
1708 }
1709 if (p_vp9->hier_rc_enable) {
1710 for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
1711 writel(p_vp9->hier_bit_layer[i],
1712 mfc_regs->e_hier_bit_rate_layer0
1713 + i * 4);
1714 }
1715 }
1716 /* number of coding layer should be zero when hierarchical is disable */
1717 reg |= p_vp9->num_hier_layer;
1718 writel(reg, mfc_regs->e_num_t_layer);
1719
1720 /* qp */
1721 writel(0x0, mfc_regs->e_fixed_picture_qp);
1722 if (!p->rc_frame && !p->rc_mb) {
1723 reg = 0;
1724 reg &= ~(0xff << 8);
1725 reg |= (p_vp9->rc_p_frame_qp << 8);
1726 reg &= ~(0xff);
1727 reg |= p_vp9->rc_frame_qp;
1728 writel(reg, mfc_regs->e_fixed_picture_qp);
1729 }
1730
1731 /* frame rate */
1732 if (p->rc_frame) {
1733 reg = 0;
1734 reg &= ~(0xffff << 16);
1735 reg |= ((p_vp9->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
1736 reg &= ~(0xffff);
1737 reg |= FRAME_DELTA_DEFAULT;
1738 writel(reg, mfc_regs->e_rc_frame_rate);
1739 }
1740
1741 /* rate control config. */
1742 reg = readl(mfc_regs->e_rc_config);
1743 /** macroblock level rate control */
1744 reg &= ~(0x1 << 8);
1745 reg |= ((p->rc_mb & 0x1) << 8);
1746 writel(reg, mfc_regs->e_rc_config);
1747
1748 /* max & min value of QP */
1749 reg = 0;
1750 /** max QP */
1751 reg &= ~(0xFF << 8);
1752 reg |= (p_vp9->rc_max_qp << 8);
1753 /** min QP */
1754 reg &= ~(0xFF);
1755 reg |= p_vp9->rc_min_qp;
1756 writel(reg, mfc_regs->e_rc_qp_bound);
1757
1758 mfc_debug_leave();
1759
1760 return 0;
1761 }
1762
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 11/10/2022 08:25, aakarsh jain wrote:
> From: Smitha T Murthy <[email protected]>
>
> Add Tesla FSD MFC(MFC v12) compatible.
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 11/10/2022 08:25, aakarsh jain wrote:
> From: Smitha T Murthy <[email protected]>
>
> Convert DT schema for s5p-mfc in yaml format
Convert S5P-MFC bindings to DT schema.
You also missed full-stop.
My second comment was ignored here.
>
> Cc: [email protected]
> Signed-off-by: Smitha T Murthy <[email protected]>
> Signed-off-by: Aakarsh Jain <[email protected]>
> ---
> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
> 2 files changed, 163 insertions(+), 75 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> index aa54c8159d9f..8b137891791f 100644
> --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
On Tue, 11 Oct 2022 17:55:02 +0530, aakarsh jain wrote:
> From: Smitha T Murthy <[email protected]>
>
> Convert DT schema for s5p-mfc in yaml format
>
> Cc: [email protected]
> Signed-off-by: Smitha T Murthy <[email protected]>
> Signed-off-by: Aakarsh Jain <[email protected]>
> ---
> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
> 2 files changed, 163 insertions(+), 75 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/
codec@13400000: clock-names: ['mfc', 'sclk_mfc'] is too long
arch/arm/boot/dts/exynos3250-artik5-eval.dtb
arch/arm/boot/dts/exynos3250-monk.dtb
arch/arm/boot/dts/exynos3250-rinato.dtb
codec@13400000: clocks: [[7, 178], [7, 228]] is too long
arch/arm/boot/dts/exynos3250-artik5-eval.dtb
arch/arm/boot/dts/exynos3250-monk.dtb
arch/arm/boot/dts/exynos3250-rinato.dtb
codec@13400000: iommus: [[36]] is too short
arch/arm/boot/dts/exynos3250-monk.dtb
arch/arm/boot/dts/exynos3250-monk.dtb
codec@13400000: iommus: [[40]] is too short
arch/arm/boot/dts/exynos3250-artik5-eval.dtb
arch/arm/boot/dts/exynos3250-artik5-eval.dtb
codec@13400000: iommus: [[47]] is too short
arch/arm/boot/dts/exynos3250-rinato.dtb
arch/arm/boot/dts/exynos3250-rinato.dtb
codec@13400000: memory-region: [[31], [32]] is too long
arch/arm/boot/dts/exynos4210-smdkv310.dtb
codec@13400000: memory-region: [[37], [38]] is too long
arch/arm/boot/dts/exynos4210-origen.dtb
codec@13400000: memory-region: [[41], [42]] is too long
arch/arm/boot/dts/exynos4412-smdk4412.dtb
codec@13400000: memory-region: [[43], [44]] is too long
arch/arm/boot/dts/exynos4412-origen.dtb
codec@13400000: memory-region: [[47], [48]] is too long
arch/arm/boot/dts/exynos4412-itop-elite.dtb
arch/arm/boot/dts/exynos4412-odroidx2.dtb
arch/arm/boot/dts/exynos4412-odroidx.dtb
codec@13400000: memory-region: [[48], [49]] is too long
arch/arm/boot/dts/exynos4412-odroidu3.dtb
codec@f1700000: clock-names:0: 'mfc' was expected
arch/arm/boot/dts/s5pv210-aquila.dtb
arch/arm/boot/dts/s5pv210-fascinate4g.dtb
arch/arm/boot/dts/s5pv210-galaxys.dtb
arch/arm/boot/dts/s5pv210-goni.dtb
arch/arm/boot/dts/s5pv210-smdkc110.dtb
arch/arm/boot/dts/s5pv210-smdkv210.dtb
arch/arm/boot/dts/s5pv210-torbreck.dtb
codec@f1700000: clock-names:1: 'sclk_mfc' was expected
arch/arm/boot/dts/s5pv210-aquila.dtb
arch/arm/boot/dts/s5pv210-fascinate4g.dtb
arch/arm/boot/dts/s5pv210-galaxys.dtb
arch/arm/boot/dts/s5pv210-goni.dtb
arch/arm/boot/dts/s5pv210-smdkc110.dtb
arch/arm/boot/dts/s5pv210-smdkv210.dtb
arch/arm/boot/dts/s5pv210-torbreck.dtb
codec@f1700000: memory-region: [[51], [52]] is too long
arch/arm/boot/dts/s5pv210-fascinate4g.dtb
codec@f1700000: memory-region: [[55], [56]] is too long
arch/arm/boot/dts/s5pv210-galaxys.dtb
On 12/10/2022 09:19, Rob Herring wrote:
> On Tue, 11 Oct 2022 17:55:02 +0530, aakarsh jain wrote:
>> From: Smitha T Murthy <[email protected]>
>>
>> Convert DT schema for s5p-mfc in yaml format
>>
>> Cc: [email protected]
>> Signed-off-by: Smitha T Murthy <[email protected]>
>> Signed-off-by: Aakarsh Jain <[email protected]>
>> ---
>> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
>> .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
>> 2 files changed, 163 insertions(+), 75 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/
>
All these must be fixed before schema can be applied.
Best regards,
Krzysztof
Hi aakarsh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on media-tree/master]
[also build test WARNING on robh/for-next arm/for-next arm64/for-next/core kvmarm/next rockchip/for-next shawnguo/for-next soc/for-next]
[cannot apply to xilinx-xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/aakarsh-jain/dt-bindings-media-s5p-mfc-Add-new-DT-schema-for-MFC/20221012-115313
base: git://linuxtv.org/media_tree.git master
config: hexagon-randconfig-r012-20221012
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 791a7ae1ba3efd6bca96338e10ffde557ba83920)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f20d380a7e03f8535b3991efd821fc32fe2baf6e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review aakarsh-jain/dt-bindings-media-s5p-mfc-Add-new-DT-schema-for-MFC/20221012-115313
git checkout f20d380a7e03f8535b3991efd821fc32fe2baf6e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/media/platform/samsung/s5p-mfc/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c:1667:5: warning: no previous prototype for function 's5p_mfc_set_enc_params_vp9' [-Wmissing-prototypes]
int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
^
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c:1667:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
^
static
1 warning generated.
vim +/s5p_mfc_set_enc_params_vp9 +1667 drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1666
> 1667 int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx)
1668 {
1669 struct s5p_mfc_dev *dev = ctx->dev;
1670 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1671 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1672 struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9;
1673 unsigned int reg = 0;
1674 int i;
1675
1676 mfc_debug_enter();
1677
1678 s5p_mfc_set_enc_params(ctx);
1679
1680 /* profile*/
1681 reg = 0;
1682 reg |= (p_vp9->vp9_profile);
1683 writel(reg, mfc_regs->e_picture_profile);
1684
1685 reg = 0;
1686 reg |= ((p_vp9->ivf_header & 0x1) << 12);
1687 reg |= ((p_vp9->hier_qp_enable & 0x1) << 11);
1688 reg |= (p_vp9->max_partition_depth & 0x1) << 3;
1689 reg |= (p_vp9->intra_pu_split_disable & 0x1) << 1;
1690 reg |= (p_vp9->num_refs_for_p - 1) & 0x1;
1691 writel(reg, mfc_regs->e_vp9_options);
1692
1693 reg = 0;
1694 reg |= (p_vp9->vp9_goldenframesel & 0x1);
1695 reg |= (p_vp9->vp9_gfrefreshperiod & 0xffff) << 1;
1696 writel(reg, mfc_regs->e_vp9_golden_frame_option);
1697
1698 reg = 0;
1699 if (p_vp9->num_hier_layer) {
1700 reg |= p_vp9->num_hier_layer & 0x3;
1701 writel(reg, mfc_regs->e_num_t_layer);
1702 /* QP value for each layer */
1703 if (p_vp9->hier_qp_enable) {
1704 for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
1705 writel(p_vp9->hier_qp_layer[i],
1706 mfc_regs->e_hier_qp_layer0
1707 + i * 4);
1708 }
1709 if (p_vp9->hier_rc_enable) {
1710 for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++)
1711 writel(p_vp9->hier_bit_layer[i],
1712 mfc_regs->e_hier_bit_rate_layer0
1713 + i * 4);
1714 }
1715 }
1716 /* number of coding layer should be zero when hierarchical is disable */
1717 reg |= p_vp9->num_hier_layer;
1718 writel(reg, mfc_regs->e_num_t_layer);
1719
1720 /* qp */
1721 writel(0x0, mfc_regs->e_fixed_picture_qp);
1722 if (!p->rc_frame && !p->rc_mb) {
1723 reg = 0;
1724 reg &= ~(0xff << 8);
1725 reg |= (p_vp9->rc_p_frame_qp << 8);
1726 reg &= ~(0xff);
1727 reg |= p_vp9->rc_frame_qp;
1728 writel(reg, mfc_regs->e_fixed_picture_qp);
1729 }
1730
1731 /* frame rate */
1732 if (p->rc_frame) {
1733 reg = 0;
1734 reg &= ~(0xffff << 16);
1735 reg |= ((p_vp9->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
1736 reg &= ~(0xffff);
1737 reg |= FRAME_DELTA_DEFAULT;
1738 writel(reg, mfc_regs->e_rc_frame_rate);
1739 }
1740
1741 /* rate control config. */
1742 reg = readl(mfc_regs->e_rc_config);
1743 /** macroblock level rate control */
1744 reg &= ~(0x1 << 8);
1745 reg |= ((p->rc_mb & 0x1) << 8);
1746 writel(reg, mfc_regs->e_rc_config);
1747
1748 /* max & min value of QP */
1749 reg = 0;
1750 /** max QP */
1751 reg &= ~(0xFF << 8);
1752 reg |= (p_vp9->rc_max_qp << 8);
1753 /** min QP */
1754 reg &= ~(0xFF);
1755 reg |= p_vp9->rc_min_qp;
1756 writel(reg, mfc_regs->e_rc_qp_bound);
1757
1758 mfc_debug_leave();
1759
1760 return 0;
1761 }
1762
--
0-DAY CI Kernel Test Service
https://01.org/lkp
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:[email protected]]
> Sent: 12 October 2022 18:27
> To: aakarsh jain <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> schema for MFC
>
> On 11/10/2022 08:25, aakarsh jain wrote:
> > From: Smitha T Murthy <[email protected]>
> >
> > Convert DT schema for s5p-mfc in yaml format
>
> Convert S5P-MFC bindings to DT schema.
>
> You also missed full-stop.
>
Ok will address it in next series.
> My second comment was ignored here.
>
I missed one review comment which was related to change in commit message. Will address it in next series.
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> > .../bindings/media/samsung,s5p-mfc.yaml | 163
> ++++++++++++++++++
> > 2 files changed, 163 insertions(+), 75 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > index aa54c8159d9f..8b137891791f 100644
> > --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>
> This is a friendly reminder during the review process.
>
> It seems my previous comments were not fully addressed. Maybe my
> feedback got lost between the quotes, maybe you just forgot to apply it.
> Please go back to the previous discussion and either implement all requested
> changes or keep discussing them.
>
> Thank you.
>
Apart from your second review comment I guess we have addressed all your review comments in the current patch.
Please review other changes as well and let us know if any changes required.
Thanks for the review.
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Rob Herring [mailto:[email protected]]
> Sent: 12 October 2022 18:50
> To: aakarsh jain <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> schema for MFC
>
> On Tue, 11 Oct 2022 17:55:02 +0530, aakarsh jain wrote:
> > From: Smitha T Murthy <[email protected]>
> >
> > Convert DT schema for s5p-mfc in yaml format
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> > .../bindings/media/samsung,s5p-mfc.yaml | 163
> ++++++++++++++++++
> > 2 files changed, 163 insertions(+), 75 deletions(-) create mode
> > 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> >
>
> Running 'make dtbs_check' with the schema in this patch gives the
following
> warnings. Consider if they are expected or the schema is incorrect. These
> may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here:
https://protect2.fireeye.com/v1/url?k=b651482e-
> e9ca7131-b650c361-000babdfecba-bb28230f82534754&q=1&e=25a7ee78-
> 697f-4371-880e-
> dcf4e3072c99&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F
>
>
> codec@13400000: clock-names: ['mfc', 'sclk_mfc'] is too long
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb
> arch/arm/boot/dts/exynos3250-monk.dtb
> arch/arm/boot/dts/exynos3250-rinato.dtb
>
> codec@13400000: clocks: [[7, 178], [7, 228]] is too long
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb
> arch/arm/boot/dts/exynos3250-monk.dtb
> arch/arm/boot/dts/exynos3250-rinato.dtb
>
> codec@13400000: iommus: [[36]] is too short
> arch/arm/boot/dts/exynos3250-monk.dtb
> arch/arm/boot/dts/exynos3250-monk.dtb
>
> codec@13400000: iommus: [[40]] is too short
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb
> arch/arm/boot/dts/exynos3250-artik5-eval.dtb
>
> codec@13400000: iommus: [[47]] is too short
> arch/arm/boot/dts/exynos3250-rinato.dtb
> arch/arm/boot/dts/exynos3250-rinato.dtb
>
> codec@13400000: memory-region: [[31], [32]] is too long
> arch/arm/boot/dts/exynos4210-smdkv310.dtb
>
> codec@13400000: memory-region: [[37], [38]] is too long
> arch/arm/boot/dts/exynos4210-origen.dtb
>
> codec@13400000: memory-region: [[41], [42]] is too long
> arch/arm/boot/dts/exynos4412-smdk4412.dtb
>
> codec@13400000: memory-region: [[43], [44]] is too long
> arch/arm/boot/dts/exynos4412-origen.dtb
>
> codec@13400000: memory-region: [[47], [48]] is too long
> arch/arm/boot/dts/exynos4412-itop-elite.dtb
> arch/arm/boot/dts/exynos4412-odroidx2.dtb
> arch/arm/boot/dts/exynos4412-odroidx.dtb
>
> codec@13400000: memory-region: [[48], [49]] is too long
> arch/arm/boot/dts/exynos4412-odroidu3.dtb
>
> codec@f1700000: clock-names:0: 'mfc' was expected
> arch/arm/boot/dts/s5pv210-aquila.dtb
> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
> arch/arm/boot/dts/s5pv210-galaxys.dtb
> arch/arm/boot/dts/s5pv210-goni.dtb
> arch/arm/boot/dts/s5pv210-smdkc110.dtb
> arch/arm/boot/dts/s5pv210-smdkv210.dtb
> arch/arm/boot/dts/s5pv210-torbreck.dtb
>
> codec@f1700000: clock-names:1: 'sclk_mfc' was expected
> arch/arm/boot/dts/s5pv210-aquila.dtb
> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
> arch/arm/boot/dts/s5pv210-galaxys.dtb
> arch/arm/boot/dts/s5pv210-goni.dtb
> arch/arm/boot/dts/s5pv210-smdkc110.dtb
> arch/arm/boot/dts/s5pv210-smdkv210.dtb
> arch/arm/boot/dts/s5pv210-torbreck.dtb
>
> codec@f1700000: memory-region: [[51], [52]] is too long
> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
>
> codec@f1700000: memory-region: [[55], [56]] is too long
> arch/arm/boot/dts/s5pv210-galaxys.dtb
Hi Rob,
We tried reproducing warnings as reported above, but I am not able to see
these warnings after running make dtbs_check & make DT_CHECKER_FLAGS=-m
dt_binding_check.
Packages used-
yamllint 1.10.0
$ dt-mk-schema --version
2022.9
Am I missing anything? Do let me know.
Thanks,
Aakarsh
On 17/10/2022 10:16, Aakarsh Jain wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: 12 October 2022 18:27
>> To: aakarsh jain <[email protected]>; linux-arm-
>> [email protected]; [email protected]; linux-
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]
>> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
>> schema for MFC
>>
>> On 11/10/2022 08:25, aakarsh jain wrote:
>>> From: Smitha T Murthy <[email protected]>
>>>
>>> Convert DT schema for s5p-mfc in yaml format
>>
>> Convert S5P-MFC bindings to DT schema.
>>
>> You also missed full-stop.
>>
> Ok will address it in next series.
>
>> My second comment was ignored here.
>>
> I missed one review comment which was related to change in commit message. Will address it in next series.
>>>
>>> Cc: [email protected]
>>> Signed-off-by: Smitha T Murthy <[email protected]>
>>> Signed-off-by: Aakarsh Jain <[email protected]>
>>> ---
>>> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
>>> .../bindings/media/samsung,s5p-mfc.yaml | 163
>> ++++++++++++++++++
>>> 2 files changed, 163 insertions(+), 75 deletions(-) create mode
>>> 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>>> b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>>> index aa54c8159d9f..8b137891791f 100644
>>> --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>>> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>>
>> This is a friendly reminder during the review process.
>>
>> It seems my previous comments were not fully addressed. Maybe my
>> feedback got lost between the quotes, maybe you just forgot to apply it.
>> Please go back to the previous discussion and either implement all requested
>> changes or keep discussing them.
>>
>> Thank you.
>>
> Apart from your second review comment I guess we have addressed all your review comments in the current patch.
> Please review other changes as well and let us know if any changes required.
No, as I said you did not. Instead of bouncing back immediately, go
through previous emails and through reviews.
I already reviewed this patch and it did not apply all my comments.
Asking me to review second time is not the solution here. The solution
here is for you to go through the comments and implement them, or answer
and keep discussion going.
Best regards,
Krzysztof
On 18/10/2022 06:48, Aakarsh Jain wrote:
>>
>> codec@f1700000: clock-names:1: 'sclk_mfc' was expected
>> arch/arm/boot/dts/s5pv210-aquila.dtb
>> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
>> arch/arm/boot/dts/s5pv210-galaxys.dtb
>> arch/arm/boot/dts/s5pv210-goni.dtb
>> arch/arm/boot/dts/s5pv210-smdkc110.dtb
>> arch/arm/boot/dts/s5pv210-smdkv210.dtb
>> arch/arm/boot/dts/s5pv210-torbreck.dtb
>>
>> codec@f1700000: memory-region: [[51], [52]] is too long
>> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
>>
>> codec@f1700000: memory-region: [[55], [56]] is too long
>> arch/arm/boot/dts/s5pv210-galaxys.dtb
>
>
>
> Hi Rob,
>
> We tried reproducing warnings as reported above, but I am not able to see
> these warnings after running make dtbs_check & make DT_CHECKER_FLAGS=-m
> dt_binding_check.
> Packages used-
> yamllint 1.10.0
> $ dt-mk-schema --version
> 2022.9
Are you sure you are running these commands on proper config and arch?
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:[email protected]]
> Sent: 18 October 2022 18:40
> To: Aakarsh Jain <[email protected]>; 'Rob Herring'
> <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> schema for MFC
>
> On 18/10/2022 06:48, Aakarsh Jain wrote:
> >>
> >> codec@f1700000: clock-names:1: 'sclk_mfc' was expected
> >> arch/arm/boot/dts/s5pv210-aquila.dtb
> >> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
> >> arch/arm/boot/dts/s5pv210-galaxys.dtb
> >> arch/arm/boot/dts/s5pv210-goni.dtb
> >> arch/arm/boot/dts/s5pv210-smdkc110.dtb
> >> arch/arm/boot/dts/s5pv210-smdkv210.dtb
> >> arch/arm/boot/dts/s5pv210-torbreck.dtb
> >>
> >> codec@f1700000: memory-region: [[51], [52]] is too long
> >> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
> >>
> >> codec@f1700000: memory-region: [[55], [56]] is too long
> >> arch/arm/boot/dts/s5pv210-galaxys.dtb
> >
> >
> >
> > Hi Rob,
> >
> > We tried reproducing warnings as reported above, but I am not able to
> > see these warnings after running make dtbs_check & make
> > DT_CHECKER_FLAGS=-m dt_binding_check.
> > Packages used-
> > yamllint 1.10.0
> > $ dt-mk-schema --version
> > 2022.9
>
>
> Are you sure you are running these commands on proper config and arch?
>
yes. arm64/defconfig .
> Best regards,
> Krzysztof
On 18/10/2022 09:21, Aakarsh Jain wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: 18 October 2022 18:40
>> To: Aakarsh Jain <[email protected]>; 'Rob Herring'
>> <[email protected]>
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
>> schema for MFC
>>
>> On 18/10/2022 06:48, Aakarsh Jain wrote:
>>>>
>>>> codec@f1700000: clock-names:1: 'sclk_mfc' was expected
>>>> arch/arm/boot/dts/s5pv210-aquila.dtb
>>>> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
>>>> arch/arm/boot/dts/s5pv210-galaxys.dtb
>>>> arch/arm/boot/dts/s5pv210-goni.dtb
>>>> arch/arm/boot/dts/s5pv210-smdkc110.dtb
>>>> arch/arm/boot/dts/s5pv210-smdkv210.dtb
>>>> arch/arm/boot/dts/s5pv210-torbreck.dtb
>>>>
>>>> codec@f1700000: memory-region: [[51], [52]] is too long
>>>> arch/arm/boot/dts/s5pv210-fascinate4g.dtb
>>>>
>>>> codec@f1700000: memory-region: [[55], [56]] is too long
>>>> arch/arm/boot/dts/s5pv210-galaxys.dtb
>>>
>>>
>>>
>>> Hi Rob,
>>>
>>> We tried reproducing warnings as reported above, but I am not able to
>>> see these warnings after running make dtbs_check & make
>>> DT_CHECKER_FLAGS=-m dt_binding_check.
>>> Packages used-
>>> yamllint 1.10.0
>>> $ dt-mk-schema --version
>>> 2022.9
>>
>>
>> Are you sure you are running these commands on proper config and arch?
>>
> yes. arm64/defconfig .
Which does not look like proper arch. Look at the warnings Rob robot
provided.
Best regards,
Krzysztof
Hi,
thanks for your patch, very minor comment below.
Le mardi 11 octobre 2022 à 17:55 +0530, aakarsh jain a écrit :
> From: Smitha T Murthy <[email protected]>
>
> Adds V4l2 controls for VP9 encoder documention.
>
> Cc: [email protected]
> Signed-off-by: Smitha T Murthy <[email protected]>
> Signed-off-by: Aakarsh Jain <[email protected]>
> ---
> .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> 1 file changed, 167 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> index 2a165ae063fb..2277d83a7cf0 100644
> --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> - Profile 3
>
> +VP9 Control Reference
> +---------------------
> +
> +The VP9 controls include controls for encoding parameters of VP9 video
> +codec.
> +
> +.. _vp9-control-id:
> +
> +VP9 Control IDs
> +
> .. _v4l2-mpeg-video-vp9-profile:
>
> ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> - Level 6.2
>
> +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
> + Quantization parameter for an I frame for VP9. Valid range: from 1 to 255.
> +
> +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> + Quantization parameter for an P frame for VP9. Valid range: from 1 to 255.
> +
> +``V4L2_CID_CODEC_VP9_MAX_QP``
> + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> + Recommended range for MFC is from 230 to 255.
We don't usually want every single HW to be documented in the generic part of
the documentation. The range supported by the HW should be found at run-time I
suppose, by querying the control. Would that work for you to remove the MFC
specifics here and in other controls ?
> +
> +``V4L2_CID_CODEC_VP9_MIN_QP``
> + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> + Recommended range for MFC is from 1 to 24.
> +
> +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> + Indicates the number of evenly spaced subintervals, called ticks, within
> + one second. This is a 16 bit unsigned integer and has a maximum value up to
> + 0xffff and a minimum value of 1.
> +
> +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> + Indicates the refresh period of the golden frame for VP9 encoder.
> +
> +.. _v4l2-vp9-golden-frame-sel:
> +
> +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_golden_framesel -
> + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> + Possible values are:
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> + - Use the (n-2)th frame as a golden frame, current frame index being
> + 'n'.
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> + - Use the previous specific frame indicated by
> + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> + golden frame.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> + Allows host to specify the quantization parameter values for each
> + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> + value to 1 enables setting of the QP values for the layers.
> +
> +.. _v4l2-vp9-ref-number-of-pframes:
> +
> +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> + Number of reference pictures for encoding P frames.
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> + - Indicates one reference frame, last encoded frame will be searched.
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> + - Indicates 2 reference frames, last encoded frame and golden frame
> + will be searched.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> + Indicates the number of hierarchial coding layer.
> + In normal encoding (non-hierarchial coding), it should be zero.
> + VP9 has upto 3 layer of encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> + Indicates quantization parameter for hierarchical coding layer 0.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> + Indicates quantization parameter for hierarchical coding layer 1.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> + Indicates quantization parameter for hierarchical coding layer 2.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +.. _v4l2-vp9-max-partition-depth:
> +
> +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_num_partitions -
> + Indicate maximum coding unit depth.
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> + - No coding unit partition depth.
> + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> + - Allows one coding unit partition depth.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> + Zero indicates enable intra NxN PU split.
> + One indicates disable intra NxN PU split.
> +
> +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> + Indicates IVF header generation. Zero indicates enable IVF format.
> + One indicates disable IVF format.
> +
>
> High Efficiency Video Coding (HEVC/H.265) Control Reference
> ===========================================================
> -----Original Message-----
> From: Nicolas Dufresne [mailto:[email protected]]
> Sent: 18 October 2022 20:36
> To: aakarsh jain <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
>
> Hi,
>
> thanks for your patch, very minor comment below.
>
> Le mardi 11 octobre 2022 à 17:55 +0530, aakarsh jain a écrit :
> > From: Smitha T Murthy <[email protected]>
> >
> > Adds V4l2 controls for VP9 encoder documention.
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > 1 file changed, 167 insertions(+)
> >
> > diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > index 2a165ae063fb..2277d83a7cf0 100644
> > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > - Profile 3
> >
> > +VP9 Control Reference
> > +---------------------
> > +
> > +The VP9 controls include controls for encoding parameters of VP9
> > +video codec.
> > +
> > +.. _vp9-control-id:
> > +
> > +VP9 Control IDs
> > +
> > .. _v4l2-mpeg-video-vp9-profile:
> >
> > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > - Level 6.2
> >
> > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
> > + Quantization parameter for an I frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > + Quantization parameter for an P frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 230 to 255.
>
> We don't usually want every single HW to be documented in the generic part
> of the documentation. The range supported by the HW should be found at
> run-time I suppose, by querying the control. Would that work for you to
> remove the MFC specifics here and in other controls ?
>
ok. will remove it in next series.
> > +
> > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 1 to 24.
> > +
> > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > + Indicates the number of evenly spaced subintervals, called ticks, within
> > + one second. This is a 16 bit unsigned integer and has a maximum value
> up to
> > + 0xffff and a minimum value of 1.
> > +
> > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > + Indicates the refresh period of the golden frame for VP9 encoder.
> > +
> > +.. _v4l2-vp9-golden-frame-sel:
> > +
> > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_golden_framesel -
> > + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> > + Possible values are:
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > + - Use the (n-2)th frame as a golden frame, current frame index being
> > + 'n'.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Use the previous specific frame indicated by
> > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > + golden frame.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > + Allows host to specify the quantization parameter values for each
> > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> > + value to 1 enables setting of the QP values for the layers.
> > +
> > +.. _v4l2-vp9-ref-number-of-pframes:
> > +
> > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > + Number of reference pictures for encoding P frames.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > + - Indicates one reference frame, last encoded frame will be searched.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Indicates 2 reference frames, last encoded frame and golden frame
> > + will be searched.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > + Indicates the number of hierarchial coding layer.
> > + In normal encoding (non-hierarchial coding), it should be zero.
> > + VP9 has upto 3 layer of encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > + Indicates quantization parameter for hierarchical coding layer 0.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > + Indicates quantization parameter for hierarchical coding layer 1.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > + Indicates quantization parameter for hierarchical coding layer 2.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +.. _v4l2-vp9-max-partition-depth:
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_num_partitions -
> > + Indicate maximum coding unit depth.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > + - No coding unit partition depth.
> > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > + - Allows one coding unit partition depth.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > + Zero indicates enable intra NxN PU split.
> > + One indicates disable intra NxN PU split.
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > + Indicates IVF header generation. Zero indicates enable IVF format.
> > + One indicates disable IVF format.
> > +
> >
> > High Efficiency Video Coding (HEVC/H.265) Control Reference
> >
> ==========================================================
> =
Thanks for the review.
Hi Aakarsh
Thanks for the patch.
>-----Original Message-----
>From: aakarsh jain [mailto:[email protected]]
>Sent: Tuesday, October 11, 2022 5:55 PM
>To: [email protected]; [email protected]; linux-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]
>Subject: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT schema for
>MFC
>
>From: Smitha T Murthy <[email protected]>
>
>Convert DT schema for s5p-mfc in yaml format
>
>Cc: [email protected]
>Signed-off-by: Smitha T Murthy <[email protected]>
>Signed-off-by: Aakarsh Jain <[email protected]>
>---
> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
> 2 files changed, 163 insertions(+), 75 deletions(-) create mode 100644
>Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>
>diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>index aa54c8159d9f..8b137891791f 100644
>--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
>+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
>@@ -1,76 +1 @@
>-* Samsung Multi Format Codec (MFC)
>
>-Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports
>high resolution decoding and encoding functionalities.
>-The MFC device driver is a v4l2 driver which can encode/decode -video
>raw/elementary streams and has support for all popular -video codecs.
>-
>-Required properties:
>- - compatible : value should be either one among the following
>- (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
>- (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
>- (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
>- (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
>- (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
>- (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
>-
>- - reg : Physical base address of the IP registers and length of memory
>- mapped region.
>-
>- - interrupts : MFC interrupt number to the CPU.
>- - clocks : from common clock binding: handle to mfc clock.
>- - clock-names : from common clock binding: must contain "mfc",
>- corresponding to entry in the clocks property.
>-
>-Optional properties:
>- - power-domains : power-domain property defined with a phandle
>- to respective power domain.
>- - memory-region : from reserved memory binding: phandles to two
>reserved
>- memory regions, first is for "left" mfc memory bus interfaces,
>- second if for the "right" mfc memory bus, used when no SYSMMU
>- support is available; used only by MFC v5 present in Exynos4 SoCs
>-
>-Obsolete properties:
>- - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-
>region
>- property instead
>-
>-
>-Example:
>-SoC specific DT entry:
>-
>-mfc: codec@13400000 {
>- compatible = "samsung,mfc-v5";
>- reg = <0x13400000 0x10000>;
>- interrupts = <0 94 0>;
>- power-domains = <&pd_mfc>;
>- clocks = <&clock 273>;
>- clock-names = "mfc";
>-};
>-
>-Reserved memory specific DT entry for given board (see reserved memory
>binding -for more information):
>-
>-reserved-memory {
>- #address-cells = <1>;
>- #size-cells = <1>;
>- ranges;
>-
>- mfc_left: region@51000000 {
>- compatible = "shared-dma-pool";
>- no-map;
>- reg = <0x51000000 0x800000>;
>- };
>-
>- mfc_right: region@43000000 {
>- compatible = "shared-dma-pool";
>- no-map;
>- reg = <0x43000000 0x800000>;
>- };
>-};
>-
>-Board specific DT entry:
>-
>-codec@13400000 {
>- memory-region = <&mfc_left>, <&mfc_right>;
>-};
>diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-
>mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-
>mfc.yaml
>new file mode 100644
>index 000000000000..ad61b509846f
>--- /dev/null
>+++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>@@ -0,0 +1,163 @@
>+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Samsung Exynos Multi Format Codec (MFC)
>+
>+maintainers:
>+ - Marek Szyprowski <[email protected]>
>+ - Smitha T Murthy <[email protected]>
>+ - Aakarsh Jain <[email protected]>
>+
>+description:
>+ Multi Format Codec (MFC) is the IP present in Samsung SoCs which
>+ supports high resolution decoding and encoding functionalities.
>+
>+properties:
>+ compatible:
>+ enum:
>+ - samsung,mfc-v5 # Exynos4
>+ - samsung,mfc-v6 # Exynos5
>+ - samsung,mfc-v7 # Exynos5420
>+ - samsung,mfc-v8 # Exynos5800
>+ - samsung,exynos5433-mfc # Exynos5433
>+ - samsung,mfc-v10 # Exynos7880
>+
>+ reg:
>+ maxItems: 1
>+
>+ clocks:
>+ minItems: 1
>+ maxItems: 3
>+
>+ clock-names:
>+ minItems: 1
>+ maxItems: 3
>+
>+ interrupts:
>+ maxItems: 1
>+
>+ iommus:
>+ maxItems: 2
>+
>+ iommu-names:
>+ maxItems: 2
>+
>+ power-domains:
>+ maxItems: 1
>+
>+ memory-region:
>+ maxItems: 1
>+
>+required:
>+ - compatible
>+ - reg
>+ - clocks
>+ - clock-names
>+ - interrupts
>+
>+allOf:
>+ - if:
>+ properties:
>+ compatible:
>+ contains:
>+ enum:
>+ - samsung,mfc-v6
>+ - samsung,mfc-v7
>+ - samsung,mfc-v8
>+ - tesla,fsd-mfc
You have not introduce "tesla,fsd-mfc" compatible yet, so this should be part of the patch which adds fsd-mfc compatible
>+ then:
>+ properties:
>+ clocks:
>+ maxItems: 1
>+ clock-names:
>+ items:
>+ - const: mfc
>+
>+ - if:
>+ properties:
>+ compatible:
>+ contains:
>+ enum:
>+ - samsung,mfc-v5
>+ then:
>+ properties:
>+ clocks:
>+ minItems: 2
>+ maxItems: 2
>+ clock-names:
>+ items:
>+ - const: mfc
>+ - const: sclk_mfc
>+
>+ - if:
>+ properties:
>+ compatible:
>+ contains:
>+ enum:
>+ - samsung,exynos5433-mfc
>+ then:
>+ properties:
>+ clocks:
>+ minItems: 3
>+ maxItems: 3
>+ clock-names:
>+ items:
>+ - const: pclk
>+ - const: aclk
>+ - const: aclk_xiu
>+
>+ - if:
>+ properties:
>+ compatible:
>+ contains:
>+ enum:
>+ - samsung,mfc-v5
>+ - samsung,mfc-v6
>+ - samsung,mfc-v7
>+ - samsung,mfc-v8
>+ - samsung,exynos5433-mfc
>+
>+ then:
>+ properties:
>+ iommus:
>+ minItems: 2
>+ maxItems: 2
>+ iommu-names:
>+ items:
>+ - const: left
>+ - const: right
>+
>+ - if:
>+ properties:
>+ compatible:
>+ contains:
>+ enum:
>+ - tesla,fsd-mfc
Same comments as above.
My suggestion, first just convert the current s5p-mfc.txt to yaml format and then add fsd-mfc support.
That way it will be easy for reviewer to understand the changes.
While reviewing and code walk through, I also noticed that exynos3250.dtsi and exynos5420.dtsi
are using same compatible as "samsung,mfc-v7" but there "clocks" property is different. That doesn't look correct.
This will cause issues when you convert s5p-mfc.txt to schema format.
I don’t know why that was done that way, but surely this need to be _fixed_ first as h/w itself are different.
So my suggestion is to fix exynos3250.dtsi and exynos5420.dtsi compatible and mfc driver for it first (as a separate patch series).
You can use the same approach what was done for mfc-v8 and mfc-v8-5433.
>+ then:
>+ properties:
>+ memory-region:
>+ maxItems: 1
>+
>+additionalProperties: false
>+
>+examples:
>+ - |
>+ #include <dt-bindings/clock/exynos4.h>
>+ #include <dt-bindings/clock/exynos-audss-clk.h>
>+ #include <dt-bindings/interrupt-controller/arm-gic.h>
>+ #include <dt-bindings/interrupt-controller/irq.h>
>+
>+ codec@13400000 {
>+ compatible = "samsung,mfc-v5";
>+ reg = <0x13400000 0x10000>;
>+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>+ power-domains = <&pd_mfc>;
>+ clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
>+ clock-names = "mfc", "sclk_mfc";
>+ iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
>+ iommu-names = "left", "right";
>+
>+ };
>--
>2.17.1
> -----Original Message-----
> From: Alim Akhtar [mailto:[email protected]]
> Sent: 27 October 2022 16:10
> To: 'aakarsh jain' <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: RE: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> schema for MFC
>
> Hi Aakarsh
> Thanks for the patch.
>
> >-----Original Message-----
> >From: aakarsh jain [mailto:[email protected]]
> >Sent: Tuesday, October 11, 2022 5:55 PM
> >To: [email protected]; [email protected];
> >linux- [email protected]; [email protected]
> >Cc: [email protected]; [email protected];
> >[email protected]; [email protected];
> >[email protected]; [email protected];
> >[email protected]; [email protected];
> >[email protected]; [email protected];
> >[email protected]; [email protected]; [email protected];
> >[email protected]; [email protected];
> [email protected];
> >[email protected]; [email protected];
> [email protected];
> >[email protected]
> >Subject: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> >schema for MFC
> >
> >From: Smitha T Murthy <[email protected]>
> >
> >Convert DT schema for s5p-mfc in yaml format
> >
> >Cc: [email protected]
> >Signed-off-by: Smitha T Murthy <[email protected]>
> >Signed-off-by: Aakarsh Jain <[email protected]>
> >---
> > .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> > .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
> > 2 files changed, 163 insertions(+), 75 deletions(-) create mode
> >100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> >
> >diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> >b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> >index aa54c8159d9f..8b137891791f 100644
> >--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> >+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> >@@ -1,76 +1 @@
> >-* Samsung Multi Format Codec (MFC)
> >
> >-Multi Format Codec (MFC) is the IP present in Samsung SoCs which
> >-supports high resolution decoding and encoding functionalities.
> >-The MFC device driver is a v4l2 driver which can encode/decode -video
> >raw/elementary streams and has support for all popular -video codecs.
> >-
> >-Required properties:
> >- - compatible : value should be either one among the following
> >- (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
> >- (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
> >- (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
> >- (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
> >- (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433
> SoC
> >- (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
> >-
> >- - reg : Physical base address of the IP registers and length of memory
> >- mapped region.
> >-
> >- - interrupts : MFC interrupt number to the CPU.
> >- - clocks : from common clock binding: handle to mfc clock.
> >- - clock-names : from common clock binding: must contain "mfc",
> >- corresponding to entry in the clocks property.
> >-
> >-Optional properties:
> >- - power-domains : power-domain property defined with a phandle
> >- to respective power domain.
> >- - memory-region : from reserved memory binding: phandles to two
> >reserved
> >- memory regions, first is for "left" mfc memory bus interfaces,
> >- second if for the "right" mfc memory bus, used when no SYSMMU
> >- support is available; used only by MFC v5 present in Exynos4 SoCs
> >-
> >-Obsolete properties:
> >- - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-
> >region
> >- property instead
> >-
> >-
> >-Example:
> >-SoC specific DT entry:
> >-
> >-mfc: codec@13400000 {
> >- compatible = "samsung,mfc-v5";
> >- reg = <0x13400000 0x10000>;
> >- interrupts = <0 94 0>;
> >- power-domains = <&pd_mfc>;
> >- clocks = <&clock 273>;
> >- clock-names = "mfc";
> >-};
> >-
> >-Reserved memory specific DT entry for given board (see reserved memory
> >binding -for more information):
> >-
> >-reserved-memory {
> >- #address-cells = <1>;
> >- #size-cells = <1>;
> >- ranges;
> >-
> >- mfc_left: region@51000000 {
> >- compatible = "shared-dma-pool";
> >- no-map;
> >- reg = <0x51000000 0x800000>;
> >- };
> >-
> >- mfc_right: region@43000000 {
> >- compatible = "shared-dma-pool";
> >- no-map;
> >- reg = <0x43000000 0x800000>;
> >- };
> >-};
> >-
> >-Board specific DT entry:
> >-
> >-codec@13400000 {
> >- memory-region = <&mfc_left>, <&mfc_right>;
> >-};
> >diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-
> >mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-
> >mfc.yaml
> >new file mode 100644
> >index 000000000000..ad61b509846f
> >--- /dev/null
> >+++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> >@@ -0,0 +1,163 @@
> >+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
> >+---
> >+$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml#
> >+$schema: http://devicetree.org/meta-schemas/core.yaml#
> >+
> >+title: Samsung Exynos Multi Format Codec (MFC)
> >+
> >+maintainers:
> >+ - Marek Szyprowski <[email protected]>
> >+ - Smitha T Murthy <[email protected]>
> >+ - Aakarsh Jain <[email protected]>
> >+
> >+description:
> >+ Multi Format Codec (MFC) is the IP present in Samsung SoCs which
> >+ supports high resolution decoding and encoding functionalities.
> >+
> >+properties:
> >+ compatible:
> >+ enum:
> >+ - samsung,mfc-v5 # Exynos4
> >+ - samsung,mfc-v6 # Exynos5
> >+ - samsung,mfc-v7 # Exynos5420
> >+ - samsung,mfc-v8 # Exynos5800
> >+ - samsung,exynos5433-mfc # Exynos5433
> >+ - samsung,mfc-v10 # Exynos7880
> >+
> >+ reg:
> >+ maxItems: 1
> >+
> >+ clocks:
> >+ minItems: 1
> >+ maxItems: 3
> >+
> >+ clock-names:
> >+ minItems: 1
> >+ maxItems: 3
> >+
> >+ interrupts:
> >+ maxItems: 1
> >+
> >+ iommus:
> >+ maxItems: 2
> >+
> >+ iommu-names:
> >+ maxItems: 2
> >+
> >+ power-domains:
> >+ maxItems: 1
> >+
> >+ memory-region:
> >+ maxItems: 1
> >+
> >+required:
> >+ - compatible
> >+ - reg
> >+ - clocks
> >+ - clock-names
> >+ - interrupts
> >+
> >+allOf:
> >+ - if:
> >+ properties:
> >+ compatible:
> >+ contains:
> >+ enum:
> >+ - samsung,mfc-v6
> >+ - samsung,mfc-v7
> >+ - samsung,mfc-v8
> >+ - tesla,fsd-mfc
> You have not introduce "tesla,fsd-mfc" compatible yet, so this should be part
> of the patch which adds fsd-mfc compatible
>
ok.
> >+ then:
> >+ properties:
> >+ clocks:
> >+ maxItems: 1
> >+ clock-names:
> >+ items:
> >+ - const: mfc
> >+
> >+ - if:
> >+ properties:
> >+ compatible:
> >+ contains:
> >+ enum:
> >+ - samsung,mfc-v5
> >+ then:
> >+ properties:
> >+ clocks:
> >+ minItems: 2
> >+ maxItems: 2
> >+ clock-names:
> >+ items:
> >+ - const: mfc
> >+ - const: sclk_mfc
> >+
> >+ - if:
> >+ properties:
> >+ compatible:
> >+ contains:
> >+ enum:
> >+ - samsung,exynos5433-mfc
> >+ then:
> >+ properties:
> >+ clocks:
> >+ minItems: 3
> >+ maxItems: 3
> >+ clock-names:
> >+ items:
> >+ - const: pclk
> >+ - const: aclk
> >+ - const: aclk_xiu
> >+
> >+ - if:
> >+ properties:
> >+ compatible:
> >+ contains:
> >+ enum:
> >+ - samsung,mfc-v5
> >+ - samsung,mfc-v6
> >+ - samsung,mfc-v7
> >+ - samsung,mfc-v8
> >+ - samsung,exynos5433-mfc
> >+
> >+ then:
> >+ properties:
> >+ iommus:
> >+ minItems: 2
> >+ maxItems: 2
> >+ iommu-names:
> >+ items:
> >+ - const: left
> >+ - const: right
> >+
> >+ - if:
> >+ properties:
> >+ compatible:
> >+ contains:
> >+ enum:
> >+ - tesla,fsd-mfc
>
> Same comments as above.
>
> My suggestion, first just convert the current s5p-mfc.txt to yaml format and
> then add fsd-mfc support.
> That way it will be easy for reviewer to understand the changes.
>
> While reviewing and code walk through, I also noticed that exynos3250.dtsi
> and exynos5420.dtsi are using same compatible as "samsung,mfc-v7" but
> there "clocks" property is different. That doesn't look correct.
> This will cause issues when you convert s5p-mfc.txt to schema format.
> I don’t know why that was done that way, but surely this need to be _fixed_
> first as h/w itself are different.
>
> So my suggestion is to fix exynos3250.dtsi and exynos5420.dtsi compatible
> and mfc driver for it first (as a separate patch series).
> You can use the same approach what was done for mfc-v8 and mfc-v8-5433.
>
>
ok will fix this issue .
> >+ then:
> >+ properties:
> >+ memory-region:
> >+ maxItems: 1
> >+
> >+additionalProperties: false
> >+
> >+examples:
> >+ - |
> >+ #include <dt-bindings/clock/exynos4.h>
> >+ #include <dt-bindings/clock/exynos-audss-clk.h>
> >+ #include <dt-bindings/interrupt-controller/arm-gic.h>
> >+ #include <dt-bindings/interrupt-controller/irq.h>
> >+
> >+ codec@13400000 {
> >+ compatible = "samsung,mfc-v5";
> >+ reg = <0x13400000 0x10000>;
> >+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> >+ power-domains = <&pd_mfc>;
> >+ clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
> >+ clock-names = "mfc", "sclk_mfc";
> >+ iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
> >+ iommu-names = "left", "right";
> >+
> >+ };
> >--
> >2.17.1
>
>
Thanks for the review.
On 11/10/2022 14:25, aakarsh jain wrote:
> From: Smitha T Murthy <[email protected]>
>
> Adds V4l2 controls for VP9 encoder documention.
>
> Cc: [email protected]
> Signed-off-by: Smitha T Murthy <[email protected]>
> Signed-off-by: Aakarsh Jain <[email protected]>
> ---
> .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> 1 file changed, 167 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> index 2a165ae063fb..2277d83a7cf0 100644
> --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> - Profile 3
>
> +VP9 Control Reference
This is wrong. There is a VPX Control Reference section for both VP8 and VP9
controls. That's where this should be added. I suspect several of the controls
you are adding here already exist, e.g. V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The
documentation may have to be updated to specify that it is for both VP8 and VP9.
> +---------------------
> +
> +The VP9 controls include controls for encoding parameters of VP9 video
> +codec.
> +
> +.. _vp9-control-id:
> +
> +VP9 Control IDs
> +
> .. _v4l2-mpeg-video-vp9-profile:
>
> ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> - Level 6.2
>
> +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
If you do need to add new controls, then please use the same MPEG_VIDEO_ prefix.
It's a bit ugly and historical, but let's keep it consistent with the others.
Regards,
Hans
> + Quantization parameter for an I frame for VP9. Valid range: from 1 to 255.
> +
> +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> + Quantization parameter for an P frame for VP9. Valid range: from 1 to 255.
> +
> +``V4L2_CID_CODEC_VP9_MAX_QP``
> + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> + Recommended range for MFC is from 230 to 255.
> +
> +``V4L2_CID_CODEC_VP9_MIN_QP``
> + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> + Recommended range for MFC is from 1 to 24.
> +
> +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> + Indicates the number of evenly spaced subintervals, called ticks, within
> + one second. This is a 16 bit unsigned integer and has a maximum value up to
> + 0xffff and a minimum value of 1.
> +
> +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> + Indicates the refresh period of the golden frame for VP9 encoder.
> +
> +.. _v4l2-vp9-golden-frame-sel:
> +
> +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_golden_framesel -
> + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> + Possible values are:
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> + - Use the (n-2)th frame as a golden frame, current frame index being
> + 'n'.
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> + - Use the previous specific frame indicated by
> + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> + golden frame.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> + Allows host to specify the quantization parameter values for each
> + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> + value to 1 enables setting of the QP values for the layers.
> +
> +.. _v4l2-vp9-ref-number-of-pframes:
> +
> +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> + Number of reference pictures for encoding P frames.
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> + - Indicates one reference frame, last encoded frame will be searched.
> + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> + - Indicates 2 reference frames, last encoded frame and golden frame
> + will be searched.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> + Indicates the number of hierarchial coding layer.
> + In normal encoding (non-hierarchial coding), it should be zero.
> + VP9 has upto 3 layer of encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> + Indicates quantization parameter for hierarchical coding layer 0.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> + Indicates quantization parameter for hierarchical coding layer 1.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> + Indicates quantization parameter for hierarchical coding layer 2.
> + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> + V4L2_CID_CODEC_VP9_MAX_QP].
> +
> +.. _v4l2-vp9-max-partition-depth:
> +
> +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> + (enum)
> +
> +enum v4l2_mpeg_vp9_num_partitions -
> + Indicate maximum coding unit depth.
> +
> +.. raw:: latex
> +
> + \footnotesize
> +
> +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> +
> +.. flat-table::
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> + - No coding unit partition depth.
> + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> + - Allows one coding unit partition depth.
> +
> +.. raw:: latex
> +
> + \normalsize
> +
> +
> +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> + Zero indicates enable intra NxN PU split.
> + One indicates disable intra NxN PU split.
> +
> +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> + Indicates IVF header generation. Zero indicates enable IVF format.
> + One indicates disable IVF format.
> +
>
> High Efficiency Video Coding (HEVC/H.265) Control Reference
> ===========================================================
> -----Original Message-----
> From: Hans Verkuil [mailto:[email protected]]
> Sent: 24 November 2022 16:54
> To: aakarsh jain <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
>
> On 11/10/2022 14:25, aakarsh jain wrote:
> > From: Smitha T Murthy <[email protected]>
> >
> > Adds V4l2 controls for VP9 encoder documention.
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > 1 file changed, 167 insertions(+)
> >
> > diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > index 2a165ae063fb..2277d83a7cf0 100644
> > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > - Profile 3
> >
> > +VP9 Control Reference
>
> This is wrong. There is a VPX Control Reference section for both VP8 and VP9
> controls. That's where this should be added. I suspect several of the controls
> you are adding here already exist, e.g.
> V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The documentation may have to be
> updated to specify that it is for both VP8 and VP9.
>
okay. I will add all VP9 Control IDs in VPX Control reference section.
> > +---------------------
> > +
> > +The VP9 controls include controls for encoding parameters of VP9
> > +video codec.
> > +
> > +.. _vp9-control-id:
> > +
> > +VP9 Control IDs
> > +
> > .. _v4l2-mpeg-video-vp9-profile:
> >
> > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > - Level 6.2
> >
> > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
>
> If you do need to add new controls, then please use the same
> MPEG_VIDEO_ prefix.
> It's a bit ugly and historical, but let's keep it consistent with the others.
>
But initially you recommended to use CODEC instead of MPEG_VIDEO.
https://patchwork.kernel.org/project/linux-media/patch/[email protected]/
Anyway I will rename from CODEC to MPEG_VIDEO again.
> Regards,
>
> Hans
>
> > + Quantization parameter for an I frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > + Quantization parameter for an P frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 230 to 255.
> > +
> > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 1 to 24.
> > +
> > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > + Indicates the number of evenly spaced subintervals, called ticks, within
> > + one second. This is a 16 bit unsigned integer and has a maximum value
> up to
> > + 0xffff and a minimum value of 1.
> > +
> > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > + Indicates the refresh period of the golden frame for VP9 encoder.
> > +
> > +.. _v4l2-vp9-golden-frame-sel:
> > +
> > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_golden_framesel -
> > + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> > + Possible values are:
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > + - Use the (n-2)th frame as a golden frame, current frame index being
> > + 'n'.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Use the previous specific frame indicated by
> > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > + golden frame.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > + Allows host to specify the quantization parameter values for each
> > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> > + value to 1 enables setting of the QP values for the layers.
> > +
> > +.. _v4l2-vp9-ref-number-of-pframes:
> > +
> > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > + Number of reference pictures for encoding P frames.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > + - Indicates one reference frame, last encoded frame will be searched.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Indicates 2 reference frames, last encoded frame and golden frame
> > + will be searched.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > + Indicates the number of hierarchial coding layer.
> > + In normal encoding (non-hierarchial coding), it should be zero.
> > + VP9 has upto 3 layer of encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > + Indicates quantization parameter for hierarchical coding layer 0.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > + Indicates quantization parameter for hierarchical coding layer 1.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > + Indicates quantization parameter for hierarchical coding layer 2.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +.. _v4l2-vp9-max-partition-depth:
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_num_partitions -
> > + Indicate maximum coding unit depth.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > + - No coding unit partition depth.
> > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > + - Allows one coding unit partition depth.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > + Zero indicates enable intra NxN PU split.
> > + One indicates disable intra NxN PU split.
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > + Indicates IVF header generation. Zero indicates enable IVF format.
> > + One indicates disable IVF format.
> > +
> >
> > High Efficiency Video Coding (HEVC/H.265) Control Reference
> >
> ==========================================================
> =
Thanks for the review.
> -----Original Message-----
> From: Hans Verkuil [mailto:[email protected]]
> Sent: 24 November 2022 16:54
> To: aakarsh jain <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
>
> On 11/10/2022 14:25, aakarsh jain wrote:
> > From: Smitha T Murthy <[email protected]>
> >
> > Adds V4l2 controls for VP9 encoder documention.
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > 1 file changed, 167 insertions(+)
> >
> > diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > index 2a165ae063fb..2277d83a7cf0 100644
> > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > - Profile 3
> >
> > +VP9 Control Reference
>
> This is wrong. There is a VPX Control Reference section for both VP8 and VP9
> controls. That's where this should be added. I suspect several of the controls
> you are adding here already exist, e.g.
> V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The documentation may have to be
> updated to specify that it is for both VP8 and VP9.
>
Since MFC has different profiles, different quantization parameter ranges for both VP8 and VP9. So we can't use same control ID's for both.
So for example in VP8 with control ID (V4L2_CID_MPEG_VIDEO_VPX_MIN_QP), QP ranges from 0-11 and in VP9 with control ID (V4L2_CID_CODEC_VP9_MIN_QP) QP ranges from 1-24. So we can't club together into single control.
> > +---------------------
> > +
> > +The VP9 controls include controls for encoding parameters of VP9
> > +video codec.
> > +
> > +.. _vp9-control-id:
> > +
> > +VP9 Control IDs
> > +
> > .. _v4l2-mpeg-video-vp9-profile:
> >
> > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > - Level 6.2
> >
> > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
>
> If you do need to add new controls, then please use the same
> MPEG_VIDEO_ prefix.
> It's a bit ugly and historical, but let's keep it consistent with the others.
>
> Regards,
>
> Hans
>
> > + Quantization parameter for an I frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > + Quantization parameter for an P frame for VP9. Valid range: from 1 to
> 255.
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 230 to 255.
> > +
> > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> > + Recommended range for MFC is from 1 to 24.
> > +
> > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > + Indicates the number of evenly spaced subintervals, called ticks, within
> > + one second. This is a 16 bit unsigned integer and has a maximum value
> up to
> > + 0xffff and a minimum value of 1.
> > +
> > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > + Indicates the refresh period of the golden frame for VP9 encoder.
> > +
> > +.. _v4l2-vp9-golden-frame-sel:
> > +
> > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_golden_framesel -
> > + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> > + Possible values are:
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > + - Use the (n-2)th frame as a golden frame, current frame index being
> > + 'n'.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Use the previous specific frame indicated by
> > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > + golden frame.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > + Allows host to specify the quantization parameter values for each
> > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> > + value to 1 enables setting of the QP values for the layers.
> > +
> > +.. _v4l2-vp9-ref-number-of-pframes:
> > +
> > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > + Number of reference pictures for encoding P frames.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > + - Indicates one reference frame, last encoded frame will be searched.
> > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > + - Indicates 2 reference frames, last encoded frame and golden frame
> > + will be searched.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > + Indicates the number of hierarchial coding layer.
> > + In normal encoding (non-hierarchial coding), it should be zero.
> > + VP9 has upto 3 layer of encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > + Indicates quantization parameter for hierarchical coding layer 0.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > + Indicates quantization parameter for hierarchical coding layer 1.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > + Indicates quantization parameter for hierarchical coding layer 2.
> > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > + V4L2_CID_CODEC_VP9_MAX_QP].
> > +
> > +.. _v4l2-vp9-max-partition-depth:
> > +
> > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > + (enum)
> > +
> > +enum v4l2_mpeg_vp9_num_partitions -
> > + Indicate maximum coding unit depth.
> > +
> > +.. raw:: latex
> > +
> > + \footnotesize
> > +
> > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > +
> > +.. flat-table::
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > + - No coding unit partition depth.
> > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > + - Allows one coding unit partition depth.
> > +
> > +.. raw:: latex
> > +
> > + \normalsize
> > +
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > + Zero indicates enable intra NxN PU split.
> > + One indicates disable intra NxN PU split.
> > +
> > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > + Indicates IVF header generation. Zero indicates enable IVF format.
> > + One indicates disable IVF format.
> > +
> >
> > High Efficiency Video Coding (HEVC/H.265) Control Reference
> >
> ==========================================================
> =
Le mercredi 14 décembre 2022 à 15:52 +0530, Aakarsh Jain a écrit :
>
> > -----Original Message-----
> > From: Hans Verkuil [mailto:[email protected]]
> > Sent: 24 November 2022 16:54
> > To: aakarsh jain <[email protected]>; linux-arm-
> > [email protected]; [email protected]; linux-
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]
> > Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
> >
> > On 11/10/2022 14:25, aakarsh jain wrote:
> > > From: Smitha T Murthy <[email protected]>
> > >
> > > Adds V4l2 controls for VP9 encoder documention.
> > >
> > > Cc: [email protected]
> > > Signed-off-by: Smitha T Murthy <[email protected]>
> > > Signed-off-by: Aakarsh Jain <[email protected]>
> > > ---
> > > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > > 1 file changed, 167 insertions(+)
> > >
> > > diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > index 2a165ae063fb..2277d83a7cf0 100644
> > > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > > - Profile 3
> > >
> > > +VP9 Control Reference
> >
> > This is wrong. There is a VPX Control Reference section for both VP8 and VP9
> > controls. That's where this should be added. I suspect several of the controls
> > you are adding here already exist, e.g.
> > V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The documentation may have to be
> > updated to specify that it is for both VP8 and VP9.
> >
> Since MFC has different profiles, different quantization parameter ranges for both VP8 and VP9. So we can't use same control ID's for both.
> So for example in VP8 with control ID (V4L2_CID_MPEG_VIDEO_VPX_MIN_QP), QP ranges from 0-11 and in VP9 with control ID (V4L2_CID_CODEC_VP9_MIN_QP) QP ranges from 1-24. So we can't club together into single control.
>
V4L2_CID_MPEG_VIDEO_VPX_PROFILE has been deprecated, and replace with menu
controls. So we now have a V4L2_CID_MPEG_VIDEO_VP8_PROFILE and a
V4L2_CID_MPEG_VIDEO_VP9_PROFILE as menues. Newly written drivers should use
these. I see that GStreamer notably has never been ported, I'll fix it.
When you implement a driver, the generic uAPI will cover all possible items, as
menus (a integer was an API mistake made in 2011, hence the deprecation). You
driver can then select which menu items it support, and its server at telling
userspace what this HW supports. Though, this should be no problem if you want
to keep the old CID for backward compat, since the range is just totally
undefined there.
For V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (and friends), the doc says "Minimum
quantization parameter for VP8.". A bit strange for a supposedly VPX parameter.
But its defines in the code as "VPX Minimum QP Value". Clearly something to be
fixed. There is no VP9 encoder drivers yet in mainline.
Though, the range for these controls is driver defined. In Venus, for VP8:
v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_VPX_MIN_QP, 1, 128, 1, 1);
It seems to be 1 to 128. While in MFC, it oddly 1 to 11:
{
.id = V4L2_CID_MPEG_VIDEO_VPX_MIN_QP,
.type = V4L2_CTRL_TYPE_INTEGER,
.minimum = 0,
.maximum = 11,
.step = 1,
.default_value = 0,
},
While I'm not a huge fan of this, since we all know QP does not scale linearly,
this is how it is, and this is kind of part of the kernel API now. So userspace
must ask the driver what is the QP range, and adapt. And in your case, you
should have no issue adding VP9 encoder with a 1 to 24 range (even if this is a
bit odd and hw specific).
Nicolas
> > > +---------------------
> > > +
> > > +The VP9 controls include controls for encoding parameters of VP9
> > > +video codec.
> > > +
> > > +.. _vp9-control-id:
> > > +
> > > +VP9 Control IDs
> > > +
> > > .. _v4l2-mpeg-video-vp9-profile:
> > >
> > > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > > - Level 6.2
> > >
> > > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
> >
> > If you do need to add new controls, then please use the same
> > MPEG_VIDEO_ prefix.
> > It's a bit ugly and historical, but let's keep it consistent with the others.
> >
> > Regards,
> >
> > Hans
> >
> > > + Quantization parameter for an I frame for VP9. Valid range: from 1 to
> > 255.
> > > +
> > > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > > + Quantization parameter for an P frame for VP9. Valid range: from 1 to
> > 255.
> > > +
> > > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > > + Maximum quantization parameter for VP9. Valid range: from 1 to 255.
> > > + Recommended range for MFC is from 230 to 255.
> > > +
> > > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > > + Minimum quantization parameter for VP9. Valid range: from 1 to 255.
> > > + Recommended range for MFC is from 1 to 24.
> > > +
> > > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > > + Indicates the number of evenly spaced subintervals, called ticks, within
> > > + one second. This is a 16 bit unsigned integer and has a maximum value
> > up to
> > > + 0xffff and a minimum value of 1.
> > > +
> > > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > > + Indicates the refresh period of the golden frame for VP9 encoder.
> > > +
> > > +.. _v4l2-vp9-golden-frame-sel:
> > > +
> > > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > > + (enum)
> > > +
> > > +enum v4l2_mpeg_vp9_golden_framesel -
> > > + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2.
> > > + Possible values are:
> > > +
> > > +.. raw:: latex
> > > +
> > > + \footnotesize
> > > +
> > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > +
> > > +.. flat-table::
> > > + :header-rows: 0
> > > + :stub-columns: 0
> > > +
> > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > > + - Use the (n-2)th frame as a golden frame, current frame index being
> > > + 'n'.
> > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > + - Use the previous specific frame indicated by
> > > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > > + golden frame.
> > > +
> > > +.. raw:: latex
> > > +
> > > + \normalsize
> > > +
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > > + Allows host to specify the quantization parameter values for each
> > > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control
> > > + value to 1 enables setting of the QP values for the layers.
> > > +
> > > +.. _v4l2-vp9-ref-number-of-pframes:
> > > +
> > > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > > + (enum)
> > > +
> > > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > > + Number of reference pictures for encoding P frames.
> > > +
> > > +.. raw:: latex
> > > +
> > > + \footnotesize
> > > +
> > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > +
> > > +.. flat-table::
> > > + :header-rows: 0
> > > + :stub-columns: 0
> > > +
> > > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > > + - Indicates one reference frame, last encoded frame will be searched.
> > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > + - Indicates 2 reference frames, last encoded frame and golden frame
> > > + will be searched.
> > > +
> > > +.. raw:: latex
> > > +
> > > + \normalsize
> > > +
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > > + Indicates the number of hierarchial coding layer.
> > > + In normal encoding (non-hierarchial coding), it should be zero.
> > > + VP9 has upto 3 layer of encoder.
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > > + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder.
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > > + Indicates quantization parameter for hierarchical coding layer 0.
> > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > > + Indicates quantization parameter for hierarchical coding layer 1.
> > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > +
> > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > > + Indicates quantization parameter for hierarchical coding layer 2.
> > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > +
> > > +.. _v4l2-vp9-max-partition-depth:
> > > +
> > > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > > + (enum)
> > > +
> > > +enum v4l2_mpeg_vp9_num_partitions -
> > > + Indicate maximum coding unit depth.
> > > +
> > > +.. raw:: latex
> > > +
> > > + \footnotesize
> > > +
> > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > +
> > > +.. flat-table::
> > > + :header-rows: 0
> > > + :stub-columns: 0
> > > +
> > > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > > + - No coding unit partition depth.
> > > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > > + - Allows one coding unit partition depth.
> > > +
> > > +.. raw:: latex
> > > +
> > > + \normalsize
> > > +
> > > +
> > > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > > + Zero indicates enable intra NxN PU split.
> > > + One indicates disable intra NxN PU split.
> > > +
> > > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > > + Indicates IVF header generation. Zero indicates enable IVF format.
> > > + One indicates disable IVF format.
> > > +
> > >
> > > High Efficiency Video Coding (HEVC/H.265) Control Reference
> > >
> > ==========================================================
> > =
>
>
> -----Original Message-----
> From: Nicolas Dufresne [mailto:[email protected]]
> Sent: 16 December 2022 22:51
> To: Aakarsh Jain <[email protected]>; 'Hans Verkuil' <hverkuil-
> [email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
>
> Le mercredi 14 décembre 2022 à 15:52 +0530, Aakarsh Jain a écrit :
> >
> > > -----Original Message-----
> > > From: Hans Verkuil [mailto:[email protected]]
> > > Sent: 24 November 2022 16:54
> > > To: aakarsh jain <[email protected]>; linux-arm-
> > > [email protected]; [email protected]; linux-
> > > [email protected]; [email protected]
> > > Cc: [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected];
> [email protected]
> > > Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9
> CIDs.
> > >
> > > On 11/10/2022 14:25, aakarsh jain wrote:
> > > > From: Smitha T Murthy <[email protected]>
> > > >
> > > > Adds V4l2 controls for VP9 encoder documention.
> > > >
> > > > Cc: [email protected]
> > > > Signed-off-by: Smitha T Murthy <[email protected]>
> > > > Signed-off-by: Aakarsh Jain <[email protected]>
> > > > ---
> > > > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > > > 1 file changed, 167 insertions(+)
> > > >
> > > > diff --git
> > > > a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > index 2a165ae063fb..2277d83a7cf0 100644
> > > > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > > > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > > > - Profile 3
> > > >
> > > > +VP9 Control Reference
> > >
> > > This is wrong. There is a VPX Control Reference section for both VP8
> > > and VP9 controls. That's where this should be added. I suspect
> > > several of the controls you are adding here already exist, e.g.
> > > V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The documentation may have
> to be
> > > updated to specify that it is for both VP8 and VP9.
> > >
> > Since MFC has different profiles, different quantization parameter ranges
> for both VP8 and VP9. So we can't use same control ID's for both.
> > So for example in VP8 with control ID
> (V4L2_CID_MPEG_VIDEO_VPX_MIN_QP), QP ranges from 0-11 and in VP9
> with control ID (V4L2_CID_CODEC_VP9_MIN_QP) QP ranges from 1-24. So
> we can't club together into single control.
> >
>
> V4L2_CID_MPEG_VIDEO_VPX_PROFILE has been deprecated, and replace
> with menu controls. So we now have a
> V4L2_CID_MPEG_VIDEO_VP8_PROFILE and a
> V4L2_CID_MPEG_VIDEO_VP9_PROFILE as menues. Newly written drivers
> should use these. I see that GStreamer notably has never been ported, I'll fix
> it.
>
> When you implement a driver, the generic uAPI will cover all possible items,
> as menus (a integer was an API mistake made in 2011, hence the
> deprecation). You driver can then select which menu items it support, and its
> server at telling userspace what this HW supports. Though, this should be no
> problem if you want to keep the old CID for backward compat, since the
> range is just totally undefined there.
>
> For V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (and friends), the doc says
> "Minimum quantization parameter for VP8.". A bit strange for a supposedly
> VPX parameter.
> But its defines in the code as "VPX Minimum QP Value". Clearly something to
> be fixed. There is no VP9 encoder drivers yet in mainline.
>
> Though, the range for these controls is driver defined. In Venus, for VP8:
>
>
> v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
> V4L2_CID_MPEG_VIDEO_VPX_MIN_QP, 1, 128, 1, 1);
>
> It seems to be 1 to 128. While in MFC, it oddly 1 to 11:
>
>
> {
> .id = V4L2_CID_MPEG_VIDEO_VPX_MIN_QP,
> .type = V4L2_CTRL_TYPE_INTEGER,
> .minimum = 0,
> .maximum = 11,
> .step = 1,
> .default_value = 0,
> },
>
> While I'm not a huge fan of this, since we all know QP does not scale linearly,
> this is how it is, and this is kind of part of the kernel API now. So userspace
> must ask the driver what is the QP range, and adapt. And in your case, you
> should have no issue adding VP9 encoder with a 1 to 24 range (even if this is a
> bit odd and hw specific).
>
> Nicolas
>
So all controls which I am using in VP9 similar to VPX will implement that as menu control. Will not touch VPX controls for backward compatibility.
Also will change all remaining VP9 controls implementation from Integer to menu control.
Will this be fine ?
>
> > > > +---------------------
> > > > +
> > > > +The VP9 controls include controls for encoding parameters of VP9
> > > > +video codec.
> > > > +
> > > > +.. _vp9-control-id:
> > > > +
> > > > +VP9 Control IDs
> > > > +
> > > > .. _v4l2-mpeg-video-vp9-profile:
> > > >
> > > > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > > > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > > > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > > > - Level 6.2
> > > >
> > > > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
> > >
> > > If you do need to add new controls, then please use the same
> > > MPEG_VIDEO_ prefix.
> > > It's a bit ugly and historical, but let's keep it consistent with the others.
> > >
> > > Regards,
> > >
> > > Hans
> > >
> > > > + Quantization parameter for an I frame for VP9. Valid range:
> > > > + from 1 to
> > > 255.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > > > + Quantization parameter for an P frame for VP9. Valid range:
> > > > +from 1 to
> > > 255.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > > > + Maximum quantization parameter for VP9. Valid range: from 1 to
> 255.
> > > > + Recommended range for MFC is from 230 to 255.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > > > + Minimum quantization parameter for VP9. Valid range: from 1 to
> 255.
> > > > + Recommended range for MFC is from 1 to 24.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > > > + Indicates the number of evenly spaced subintervals, called ticks,
> within
> > > > + one second. This is a 16 bit unsigned integer and has a
> > > > +maximum value
> > > up to
> > > > + 0xffff and a minimum value of 1.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > > > + Indicates the refresh period of the golden frame for VP9 encoder.
> > > > +
> > > > +.. _v4l2-vp9-golden-frame-sel:
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > > > + (enum)
> > > > +
> > > > +enum v4l2_mpeg_vp9_golden_framesel -
> > > > + Selects the golden frame for encoding. Valid when NUM_OF_REF is
> 2.
> > > > + Possible values are:
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \footnotesize
> > > > +
> > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > +
> > > > +.. flat-table::
> > > > + :header-rows: 0
> > > > + :stub-columns: 0
> > > > +
> > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > > > + - Use the (n-2)th frame as a golden frame, current frame index
> being
> > > > + 'n'.
> > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > > + - Use the previous specific frame indicated by
> > > > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > > > + golden frame.
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \normalsize
> > > > +
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > > > + Allows host to specify the quantization parameter values for each
> > > > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > > > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the
> control
> > > > + value to 1 enables setting of the QP values for the layers.
> > > > +
> > > > +.. _v4l2-vp9-ref-number-of-pframes:
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > > > + (enum)
> > > > +
> > > > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > > > + Number of reference pictures for encoding P frames.
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \footnotesize
> > > > +
> > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > +
> > > > +.. flat-table::
> > > > + :header-rows: 0
> > > > + :stub-columns: 0
> > > > +
> > > > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > > > + - Indicates one reference frame, last encoded frame will be
> searched.
> > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > > + - Indicates 2 reference frames, last encoded frame and golden
> frame
> > > > + will be searched.
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \normalsize
> > > > +
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > > > + Indicates the number of hierarchial coding layer.
> > > > + In normal encoding (non-hierarchial coding), it should be zero.
> > > > + VP9 has upto 3 layer of encoder.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > > > + Indicates enabling of bit rate for hierarchical coding layers VP9
> encoder.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > > > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > > > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > > > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > > > + Indicates quantization parameter for hierarchical coding layer 0.
> > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > > > + Indicates quantization parameter for hierarchical coding layer 1.
> > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > > > + Indicates quantization parameter for hierarchical coding layer 2.
> > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > +
> > > > +.. _v4l2-vp9-max-partition-depth:
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > > > + (enum)
> > > > +
> > > > +enum v4l2_mpeg_vp9_num_partitions -
> > > > + Indicate maximum coding unit depth.
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \footnotesize
> > > > +
> > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > +
> > > > +.. flat-table::
> > > > + :header-rows: 0
> > > > + :stub-columns: 0
> > > > +
> > > > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > > > + - No coding unit partition depth.
> > > > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > > > + - Allows one coding unit partition depth.
> > > > +
> > > > +.. raw:: latex
> > > > +
> > > > + \normalsize
> > > > +
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > > > + Zero indicates enable intra NxN PU split.
> > > > + One indicates disable intra NxN PU split.
> > > > +
> > > > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > > > + Indicates IVF header generation. Zero indicates enable IVF format.
> > > > + One indicates disable IVF format.
> > > > +
> > > >
> > > > High Efficiency Video Coding (HEVC/H.265) Control Reference
> > > >
> > >
> ==========================================================
> > > =
> >
> >
Le mercredi 21 décembre 2022 à 15:26 +0530, Aakarsh Jain a écrit :
>
> > -----Original Message-----
> > From: Nicolas Dufresne [mailto:[email protected]]
> > Sent: 16 December 2022 22:51
> > To: Aakarsh Jain <[email protected]>; 'Hans Verkuil' <hverkuil-
> > [email protected]>; [email protected]; linux-
> > [email protected]; [email protected];
> > [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]
> > Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs.
> >
> > Le mercredi 14 décembre 2022 à 15:52 +0530, Aakarsh Jain a écrit :
> > >
> > > > -----Original Message-----
> > > > From: Hans Verkuil [mailto:[email protected]]
> > > > Sent: 24 November 2022 16:54
> > > > To: aakarsh jain <[email protected]>; linux-arm-
> > > > [email protected]; [email protected]; linux-
> > > > [email protected]; [email protected]
> > > > Cc: [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > > > [email protected]; [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > > > [email protected]; [email protected];
> > [email protected]
> > > > Subject: Re: [Patch v3 05/15] Documention: v4l: Documentation for VP9
> > CIDs.
> > > >
> > > > On 11/10/2022 14:25, aakarsh jain wrote:
> > > > > From: Smitha T Murthy <[email protected]>
> > > > >
> > > > > Adds V4l2 controls for VP9 encoder documention.
> > > > >
> > > > > Cc: [email protected]
> > > > > Signed-off-by: Smitha T Murthy <[email protected]>
> > > > > Signed-off-by: Aakarsh Jain <[email protected]>
> > > > > ---
> > > > > .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++
> > > > > 1 file changed, 167 insertions(+)
> > > > >
> > > > > diff --git
> > > > > a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > > index 2a165ae063fb..2277d83a7cf0 100644
> > > > > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> > > > > @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile -
> > > > > * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3``
> > > > > - Profile 3
> > > > >
> > > > > +VP9 Control Reference
> > > >
> > > > This is wrong. There is a VPX Control Reference section for both VP8
> > > > and VP9 controls. That's where this should be added. I suspect
> > > > several of the controls you are adding here already exist, e.g.
> > > > V4L2_CID_MPEG_VIDEO_VPX_MIN_QP. The documentation may have
> > to be
> > > > updated to specify that it is for both VP8 and VP9.
> > > >
> > > Since MFC has different profiles, different quantization parameter ranges
> > for both VP8 and VP9. So we can't use same control ID's for both.
> > > So for example in VP8 with control ID
> > (V4L2_CID_MPEG_VIDEO_VPX_MIN_QP), QP ranges from 0-11 and in VP9
> > with control ID (V4L2_CID_CODEC_VP9_MIN_QP) QP ranges from 1-24. So
> > we can't club together into single control.
> > >
> >
> > V4L2_CID_MPEG_VIDEO_VPX_PROFILE has been deprecated, and replace
> > with menu controls. So we now have a
> > V4L2_CID_MPEG_VIDEO_VP8_PROFILE and a
> > V4L2_CID_MPEG_VIDEO_VP9_PROFILE as menues. Newly written drivers
> > should use these. I see that GStreamer notably has never been ported, I'll fix
> > it.
> >
> > When you implement a driver, the generic uAPI will cover all possible items,
> > as menus (a integer was an API mistake made in 2011, hence the
> > deprecation). You driver can then select which menu items it support, and its
> > server at telling userspace what this HW supports. Though, this should be no
> > problem if you want to keep the old CID for backward compat, since the
> > range is just totally undefined there.
> >
> > For V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (and friends), the doc says
> > "Minimum quantization parameter for VP8.". A bit strange for a supposedly
> > VPX parameter.
> > But its defines in the code as "VPX Minimum QP Value". Clearly something to
> > be fixed. There is no VP9 encoder drivers yet in mainline.
> >
> > Though, the range for these controls is driver defined. In Venus, for VP8:
> >
> >
> > v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops,
> > V4L2_CID_MPEG_VIDEO_VPX_MIN_QP, 1, 128, 1, 1);
> >
> > It seems to be 1 to 128. While in MFC, it oddly 1 to 11:
> >
> >
> > {
> > .id = V4L2_CID_MPEG_VIDEO_VPX_MIN_QP,
> > .type = V4L2_CTRL_TYPE_INTEGER,
> > .minimum = 0,
> > .maximum = 11,
> > .step = 1,
> > .default_value = 0,
> > },
> >
> > While I'm not a huge fan of this, since we all know QP does not scale linearly,
> > this is how it is, and this is kind of part of the kernel API now. So userspace
> > must ask the driver what is the QP range, and adapt. And in your case, you
> > should have no issue adding VP9 encoder with a 1 to 24 range (even if this is a
> > bit odd and hw specific).
> >
> > Nicolas
> >
>
> So all controls which I am using in VP9 similar to VPX will implement that as menu control. Will not touch VPX controls for backward compatibility.
> Also will change all remaining VP9 controls implementation from Integer to menu control.
>
> Will this be fine ?
I think so, I'd add menu control to the existing VP8 decoder, so that both are
supported, but I'd only implement menu controls for newly added formats. This is
to maintain backward compatibility indeed.
>
> >
> > > > > +---------------------
> > > > > +
> > > > > +The VP9 controls include controls for encoding parameters of VP9
> > > > > +video codec.
> > > > > +
> > > > > +.. _vp9-control-id:
> > > > > +
> > > > > +VP9 Control IDs
> > > > > +
> > > > > .. _v4l2-mpeg-video-vp9-profile:
> > > > >
> > > > > ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE``
> > > > > @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level -
> > > > > * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2``
> > > > > - Level 6.2
> > > > >
> > > > > +``V4L2_CID_CODEC_VP9_I_FRAME_QP``
> > > >
> > > > If you do need to add new controls, then please use the same
> > > > MPEG_VIDEO_ prefix.
> > > > It's a bit ugly and historical, but let's keep it consistent with the others.
> > > >
> > > > Regards,
> > > >
> > > > Hans
> > > >
> > > > > + Quantization parameter for an I frame for VP9. Valid range:
> > > > > + from 1 to
> > > > 255.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_P_FRAME_QP``
> > > > > + Quantization parameter for an P frame for VP9. Valid range:
> > > > > +from 1 to
> > > > 255.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_MAX_QP``
> > > > > + Maximum quantization parameter for VP9. Valid range: from 1 to
> > 255.
> > > > > + Recommended range for MFC is from 230 to 255.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_MIN_QP``
> > > > > + Minimum quantization parameter for VP9. Valid range: from 1 to
> > 255.
> > > > > + Recommended range for MFC is from 1 to 24.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE``
> > > > > + Indicates the number of evenly spaced subintervals, called ticks,
> > within
> > > > > + one second. This is a 16 bit unsigned integer and has a
> > > > > +maximum value
> > > > up to
> > > > > + 0xffff and a minimum value of 1.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD``
> > > > > + Indicates the refresh period of the golden frame for VP9 encoder.
> > > > > +
> > > > > +.. _v4l2-vp9-golden-frame-sel:
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL``
> > > > > + (enum)
> > > > > +
> > > > > +enum v4l2_mpeg_vp9_golden_framesel -
> > > > > + Selects the golden frame for encoding. Valid when NUM_OF_REF is
> > 2.
> > > > > + Possible values are:
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \footnotesize
> > > > > +
> > > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > > +
> > > > > +.. flat-table::
> > > > > + :header-rows: 0
> > > > > + :stub-columns: 0
> > > > > +
> > > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV``
> > > > > + - Use the (n-2)th frame as a golden frame, current frame index
> > being
> > > > > + 'n'.
> > > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > > > + - Use the previous specific frame indicated by
> > > > > + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a
> > > > > + golden frame.
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \normalsize
> > > > > +
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE``
> > > > > + Allows host to specify the quantization parameter values for each
> > > > > + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only
> > > > > + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the
> > control
> > > > > + value to 1 enables setting of the QP values for the layers.
> > > > > +
> > > > > +.. _v4l2-vp9-ref-number-of-pframes:
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES``
> > > > > + (enum)
> > > > > +
> > > > > +enum v4l2_mpeg_vp9_ref_num_for_pframes -
> > > > > + Number of reference pictures for encoding P frames.
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \footnotesize
> > > > > +
> > > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > > +
> > > > > +.. flat-table::
> > > > > + :header-rows: 0
> > > > > + :stub-columns: 0
> > > > > +
> > > > > + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME``
> > > > > + - Indicates one reference frame, last encoded frame will be
> > searched.
> > > > > + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD``
> > > > > + - Indicates 2 reference frames, last encoded frame and golden
> > frame
> > > > > + will be searched.
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \normalsize
> > > > > +
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER``
> > > > > + Indicates the number of hierarchial coding layer.
> > > > > + In normal encoding (non-hierarchial coding), it should be zero.
> > > > > + VP9 has upto 3 layer of encoder.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE``
> > > > > + Indicates enabling of bit rate for hierarchical coding layers VP9
> > encoder.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR``
> > > > > + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR``
> > > > > + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR``
> > > > > + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP``
> > > > > + Indicates quantization parameter for hierarchical coding layer 0.
> > > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP``
> > > > > + Indicates quantization parameter for hierarchical coding layer 1.
> > > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP``
> > > > > + Indicates quantization parameter for hierarchical coding layer 2.
> > > > > + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP,
> > > > > + V4L2_CID_CODEC_VP9_MAX_QP].
> > > > > +
> > > > > +.. _v4l2-vp9-max-partition-depth:
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH``
> > > > > + (enum)
> > > > > +
> > > > > +enum v4l2_mpeg_vp9_num_partitions -
> > > > > + Indicate maximum coding unit depth.
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \footnotesize
> > > > > +
> > > > > +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}|
> > > > > +
> > > > > +.. flat-table::
> > > > > + :header-rows: 0
> > > > > + :stub-columns: 0
> > > > > +
> > > > > + * - ``V4L2_CID_CODEC_VP9_0_PARTITION``
> > > > > + - No coding unit partition depth.
> > > > > + * - ``V4L2_CID_CODEC_VP9_1_PARTITION``
> > > > > + - Allows one coding unit partition depth.
> > > > > +
> > > > > +.. raw:: latex
> > > > > +
> > > > > + \normalsize
> > > > > +
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT``
> > > > > + Zero indicates enable intra NxN PU split.
> > > > > + One indicates disable intra NxN PU split.
> > > > > +
> > > > > +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER``
> > > > > + Indicates IVF header generation. Zero indicates enable IVF format.
> > > > > + One indicates disable IVF format.
> > > > > +
> > > > >
> > > > > High Efficiency Video Coding (HEVC/H.265) Control Reference
> > > > >
> > > >
> > ==========================================================
> > > > =
> > >
> > >
>
>
>
On 11/10/2022 14:25, aakarsh jain wrote:
> From: Smitha T Murthy <[email protected]>
>
> Convert DT schema for s5p-mfc in yaml format
>
> Cc: [email protected]
> Signed-off-by: Smitha T Murthy <[email protected]>
> Signed-off-by: Aakarsh Jain <[email protected]>
> ---
> .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++
Hi Aakarsh,
Any plans for new version of this DT schema conversion? The Samsung MFC
is one of last remaining bigger pieces for conversion. We already have
100% bindings compliance for ARM64 but the MFC is missing for ARMv7:
https://pastebin.com/D8jXnjEe
(that's on my pending branch with all patches from LKML collected).
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:[email protected]]
> Sent: 21 February 2023 21:56
> To: aakarsh jain <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Subject: Re: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT
> schema for MFC
>
> On 11/10/2022 14:25, aakarsh jain wrote:
> > From: Smitha T Murthy <[email protected]>
> >
> > Convert DT schema for s5p-mfc in yaml format
> >
> > Cc: [email protected]
> > Signed-off-by: Smitha T Murthy <[email protected]>
> > Signed-off-by: Aakarsh Jain <[email protected]>
> > ---
> > .../devicetree/bindings/media/s5p-mfc.txt | 75 --------
> > .../bindings/media/samsung,s5p-mfc.yaml | 163
> ++++++++++++++++++
>
> Hi Aakarsh,
>
> Any plans for new version of this DT schema conversion? The Samsung MFC
> is one of last remaining bigger pieces for conversion. We already have 100%
> bindings compliance for ARM64 but the MFC is missing for ARMv7:
>
> https://protect2.fireeye.com/v1/url?k=9661b377-f7eaa63c-96603838-
> 74fe485fb305-bc4c89dbd0204557&q=1&e=1485ea1d-43e8-4541-8078-
> 4d13ff6cc42f&u=https%3A%2F%2Fpastebin.com%2FD8jXnjEe
> (that's on my pending branch with all patches from LKML collected).
>
> Best regards,
> Krzysztof
Hi Krzysztof,
I was little occupied with other stuff. I will fix all warnings and errors. Will post the patch soon.
Thanks,
Aakarsh