This series adds support for UFS controller found in FSD SoC.
The HCI is almost same as found on other Exynos SoCs with minor
differences. This also adds the required UFS-PHY driver changes.
Patch 2/6: common change to handle different CDR offsets
*Changes since v3:
- Addressed review comments on patch 6/6 from Chanho
*Changes since v2:
- Addressed review comments from Chanho
- collected reviewed-by, tested-by tags
- rebased on next-20220609
*Changes since v1:
- Addressed review comments from Bart, Krzysztof, Chanho
- collected Ack-by tags
- rebased on next-20220602
Alim Akhtar (6):
dt-bindings: phy: Add FSD UFS PHY bindings
phy: samsung-ufs: move cdr offset to drvdata
phy: samsung-ufs: add support for FSD ufs phy driver
dt-bindings: ufs: exynos-ufs: add fsd compatible
ufs: host: ufs-exynos: add mphy apb clock mask
ufs: host: ufs-exynos: add support for fsd ufs hci
.../bindings/phy/samsung,ufs-phy.yaml | 1 +
.../bindings/ufs/samsung,exynos-ufs.yaml | 1 +
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 +
drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++
drivers/phy/samsung/phy-samsung-ufs.c | 7 +-
drivers/phy/samsung/phy-samsung-ufs.h | 3 +-
drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++-
drivers/ufs/host/ufs-exynos.h | 1 +
10 files changed, 217 insertions(+), 3 deletions(-)
create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c
base-commit: ff539ac73ea559a8c146d99ab14bfcaddd30547a
--
2.25.1
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index 17897a3b5c9e..8da99461e817 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
+ - tesla,fsd-ufs-phy
reg:
maxItems: 1
--
2.25.1
Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.
Signed-off-by: Alim Akhtar <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
Tested-by: Chanho Park <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index a81d8cbd542f..cc128aff8871 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -52,11 +52,12 @@
#define HCI_ERR_EN_DME_LAYER 0x88
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
+#define MPHY_APBCLK_STOP BIT(3)
#define REFCLK_STOP BIT(2)
#define UNIPRO_MCLK_STOP BIT(1)
#define UNIPRO_PCLK_STOP BIT(0)
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
- UNIPRO_MCLK_STOP |\
+ UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
--
2.25.1
Move CDR lock offset to drv data so that it can be extended for other SoCs
which are having CDR lock at different register offset.
Signed-off-by: Bharat Uppal <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
drivers/phy/samsung/phy-samsung-ufs.c | 4 +++-
drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index d1e9d0ae5c1d..72854336f59d 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -11,6 +11,8 @@
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
+
/* Calibration for phy initialization */
static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
@@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 1,
+ .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index fa4d2983eec6..2b256070d657 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -10,6 +10,7 @@
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
@@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
},
.has_symbol_clk = 0,
+ .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 206a79c69a6c..8cec7652b459 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
}
err = readl_poll_timeout(
- ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
+ ufs_phy->reg_pma +
+ PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
if (err)
dev_err(ufs_phy->dev,
@@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
drvdata = match->data;
phy->dev = dev;
+ phy->drvdata = drvdata;
phy->cfgs = drvdata->cfgs;
phy->has_symbol_clk = drvdata->has_symbol_clk;
memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 854b53bdf347..913542ebff7a 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -40,7 +40,6 @@
/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS 0x1e
-#define PHY_CDR_LOCK_STATUS 0x5e
#define PHY_PLL_LOCK_BIT BIT(5)
#define PHY_CDR_LOCK_BIT BIT(4)
@@ -111,6 +110,7 @@ struct samsung_ufs_phy_drvdata {
const struct samsung_ufs_phy_cfg **cfgs;
struct samsung_ufs_phy_pmu_isol isol;
bool has_symbol_clk;
+ u32 cdr_lock_status_offset;
};
struct samsung_ufs_phy {
--
2.25.1
> Subject: [PATCH v4 2/6] phy: samsung-ufs: move cdr offset to drvdata
>
> Move CDR lock offset to drv data so that it can be extended for other SoCs
> which are having CDR lock at different register offset.
>
> Signed-off-by: Bharat Uppal <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> Reviewed-by: Chanho Park <[email protected]>
- Reviewed-by: Chanho Park <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++
> drivers/phy/samsung/phy-samsung-ufs.c | 4 +++-
> drivers/phy/samsung/phy-samsung-ufs.h | 2 +-
> 4 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c
> b/drivers/phy/samsung/phy-exynos7-ufs.c
> index d1e9d0ae5c1d..72854336f59d 100644
> --- a/drivers/phy/samsung/phy-exynos7-ufs.c
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.c
> @@ -11,6 +11,8 @@
> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
>
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
> +
> /* Calibration for phy initialization */ static const struct
> samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -74,4 +76,5 @@
> const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
> .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
> },
> .has_symbol_clk = 1,
> + .cdr_lock_status_offset =
> EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> };
> diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c
> b/drivers/phy/samsung/phy-exynosautov9-ufs.c
> index fa4d2983eec6..2b256070d657 100644
> --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
> +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
> @@ -10,6 +10,7 @@
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
> #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
>
> #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
> PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -64,4 +65,5 @@ const
> struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
> .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN,
> },
> .has_symbol_clk = 0,
> + .cdr_lock_status_offset =
> +EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
> };
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> b/drivers/phy/samsung/phy-samsung-ufs.c
> index 206a79c69a6c..8cec7652b459 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy
> *phy)
> }
>
> err = readl_poll_timeout(
> - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS),
> + ufs_phy->reg_pma +
> + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset),
> val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us);
> if (err)
> dev_err(ufs_phy->dev,
> @@ -327,6 +328,7 @@ static int samsung_ufs_phy_probe(struct
> platform_device *pdev)
>
> drvdata = match->data;
> phy->dev = dev;
> + phy->drvdata = drvdata;
This can be reversing changes of below patch.
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/commit/?h=next&id=f86c1d0a58b1f63a176f537e2f6851be49c20ad4
By suggestion of Krzysztof, I removed drvdata assignment to samsung_ufs_phy struct and moved has_symbol_clk from drvdata to samsung_ufs_phy struct.
However, I forgot to remove drvdata from samsung_ufs_phy struct...
Anyway, you want to get back the drvdata, you may need to add a preceding patch with reconsideration of has_symbol_clk to the drvdata again.
Otherwise, you can simply put cdr_lock_status_offset to the samsung_ufs_phy struct and assign the data from drvdata same as has_symbol_clk and isol.
Best Regards,
Chanho Park
On 10/06/2022 12:41, Alim Akhtar wrote:
> Move CDR lock offset to drv data so that it can be extended for other SoCs
> which are having CDR lock at different register offset.
>
> Signed-off-by: Bharat Uppal <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> Reviewed-by: Chanho Park <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 10/06/2022 12:41, Alim Akhtar wrote:
> Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
> clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
> during clock masking/unmasking.
>
> Signed-off-by: Alim Akhtar <[email protected]>
> Reviewed-by: Chanho Park <[email protected]>
> Tested-by: Chanho Park <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Vinod
>-----Original Message-----
>From: Alim Akhtar [mailto:[email protected]]
>Sent: Friday, June 10, 2022 4:11 PM
>To: [email protected]; [email protected]; linux-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; Alim Akhtar
><[email protected]>
>Subject: [PATCH v4 0/6] Add support for UFS controller found in FSD SoC
>
>
>This series adds support for UFS controller found in FSD SoC.
>The HCI is almost same as found on other Exynos SoCs with minor differences.
>This also adds the required UFS-PHY driver changes.
>
>Patch 2/6: common change to handle different CDR offsets
>
>*Changes since v3:
>- Addressed review comments on patch 6/6 from Chanho
>
>*Changes since v2:
>- Addressed review comments from Chanho
>- collected reviewed-by, tested-by tags
>- rebased on next-20220609
>
>*Changes since v1:
>- Addressed review comments from Bart, Krzysztof, Chanho
>- collected Ack-by tags
>- rebased on next-20220602
>
>
>Alim Akhtar (6):
> dt-bindings: phy: Add FSD UFS PHY bindings
> phy: samsung-ufs: move cdr offset to drvdata
> phy: samsung-ufs: add support for FSD ufs phy driver
Can you please take patch-{1/6, 2/6 and 3/6} via phy tree?
The UFS patches has been picked by Martin via SCSI tree.
Thanks.
> dt-bindings: ufs: exynos-ufs: add fsd compatible
> ufs: host: ufs-exynos: add mphy apb clock mask
> ufs: host: ufs-exynos: add support for fsd ufs hci
>
> .../bindings/phy/samsung,ufs-phy.yaml | 1 +
> .../bindings/ufs/samsung,exynos-ufs.yaml | 1 +
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos7-ufs.c | 3 +
> drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 +
> drivers/phy/samsung/phy-fsd-ufs.c | 58 +++++++
> drivers/phy/samsung/phy-samsung-ufs.c | 7 +-
> drivers/phy/samsung/phy-samsung-ufs.h | 3 +-
> drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++-
> drivers/ufs/host/ufs-exynos.h | 1 +
> 10 files changed, 217 insertions(+), 3 deletions(-) create mode 100644
>drivers/phy/samsung/phy-fsd-ufs.c
>
>
>base-commit: ff539ac73ea559a8c146d99ab14bfcaddd30547a
>--
>2.25.1
On 10-06-22, 16:11, Alim Akhtar wrote:
>
> This series adds support for UFS controller found in FSD SoC.
> The HCI is almost same as found on other Exynos SoCs with minor
> differences. This also adds the required UFS-PHY driver changes.
Applied 1-3, thanks
--
~Vinod
On Fri, 10 Jun 2022 16:11:13 +0530, Alim Akhtar wrote:
> This series adds support for UFS controller found in FSD SoC.
> The HCI is almost same as found on other Exynos SoCs with minor
> differences. This also adds the required UFS-PHY driver changes.
>
> Patch 2/6: common change to handle different CDR offsets
>
> *Changes since v3:
> - Addressed review comments on patch 6/6 from Chanho
>
> [...]
Applied to 5.20/scsi-queue, thanks!
[4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible
https://git.kernel.org/mkp/scsi/c/ea83df8e3bd0
[5/6] ufs: host: ufs-exynos: add mphy apb clock mask
https://git.kernel.org/mkp/scsi/c/daa782a51ec8
[6/6] ufs: host: ufs-exynos: add support for fsd ufs hci
https://git.kernel.org/mkp/scsi/c/216f74e8059a
--
Martin K. Petersen Oracle Linux Engineering