2020-12-21 01:58:34

by Shradha Todi

Subject: [PATCH] PCI: dwc: Add upper limit address for outbound iATU

The size parameter is unsigned long type which can accept
size > 4GB. In that case, the upper limit address must be
programmed. Add support to program the upper limit
address and set INCREASE_REGION_SIZE in case size > 4GB.

Signed-off-by: Shradha Todi <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 28c56a1..7eba3b2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -290,12 +290,16 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
upper_32_bits(cpu_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
+ upper_32_bits(cpu_addr + size - 1));
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
lower_32_bits(pci_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
upper_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
- PCIE_ATU_FUNC_NUM(func_no));
+ val = type | PCIE_ATU_FUNC_NUM(func_no);
+ val = upper_32_bits(size - 1) ?
+ val | PCIE_ATU_INCREASE_REGION_SIZE : val;
+ dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);

/*
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b09329b..28b72fb 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -106,6 +106,7 @@
#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_ATU_UPPER_LIMIT 0x924

#define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_DBI_RO_WR_EN BIT(0)
--
2.7.4

2020-12-21 16:08:41

by Rob Herring (Arm)

Subject: Re: [PATCH] PCI: dwc: Add upper limit address for outbound iATU

On Sun, Dec 20, 2020 at 6:56 PM Shradha Todi <[email protected]> wrote:
>
> The size parameter is unsigned long type which can accept
> size > 4GB. In that case, the upper limit address must be
> programmed. Add support to program the upper limit
> address and set INCREASE_REGION_SIZE in case size > 4GB.

Not all DWC h/w versions have the upper register and bit. Is it safe
to write to the non-existent register?

>
> Signed-off-by: Shradha Todi <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 28c56a1..7eba3b2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -290,12 +290,16 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> upper_32_bits(cpu_addr));
> dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
> lower_32_bits(cpu_addr + size - 1));
> + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> + upper_32_bits(cpu_addr + size - 1));

If not safe, perhaps only write if non-zero.

> dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
> lower_32_bits(pci_addr));
> dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
> upper_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> - PCIE_ATU_FUNC_NUM(func_no));
> + val = type | PCIE_ATU_FUNC_NUM(func_no);
> + val = upper_32_bits(size - 1) ?
> + val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
> dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>
> /*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index b09329b..28b72fb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -106,6 +106,7 @@
> #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
> #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
> #define PCIE_ATU_UPPER_TARGET 0x91C
> +#define PCIE_ATU_UPPER_LIMIT 0x924
>
> #define PCIE_MISC_CONTROL_1_OFF 0x8BC
> #define PCIE_DBI_RO_WR_EN BIT(0)
> --
> 2.7.4
>

2020-12-24 05:51:20

by Shradha Todi

Subject: RE: [PATCH] PCI: dwc: Add upper limit address for outbound iATU

> From: Rob Herring <[email protected]>
> Subject: Re: [PATCH] PCI: dwc: Add upper limit address for outbound iATU
>
> On Sun, Dec 20, 2020 at 6:56 PM Shradha Todi <[email protected]>
> wrote:
> >
> > The size parameter is unsigned long type which can accept size > 4GB.
> > In that case, the upper limit address must be programmed. Add support
> > to program the upper limit address and set INCREASE_REGION_SIZE in
> > case size > 4GB.
>
> Not all DWC h/w versions have the upper register and bit. Is it safe to write to
> the non-existent register?

Thanks for the review.
Surely it exists post 4.80a version of controller but I am not sure in
which version of the controller this was introduced. I can figure this
out from the SNPS team and update the patch accordingly.

>
> >
> > Signed-off-by: Shradha Todi <[email protected]>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
> > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > 2 files changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> > b/drivers/pci/controller/dwc/pcie-designware.c
> > index 28c56a1..7eba3b2 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -290,12 +290,16 @@ static void __dw_pcie_prog_outbound_atu(struct
> dw_pcie *pci, u8 func_no,
> > upper_32_bits(cpu_addr));
> > dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
> > lower_32_bits(cpu_addr + size - 1));
> > + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> > + upper_32_bits(cpu_addr + size - 1));
>
> If not safe, perhaps only write if non-zero.
>
Writing zero has no side-affect and we have tested this.

> > dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
> > lower_32_bits(pci_addr));
> > dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
> > upper_32_bits(pci_addr));
> > - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> > - PCIE_ATU_FUNC_NUM(func_no));
> > + val = type | PCIE_ATU_FUNC_NUM(func_no);
> > + val = upper_32_bits(size - 1) ?
> > + val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
> > dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> >
> > /*
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> > b/drivers/pci/controller/dwc/pcie-designware.h
> > index b09329b..28b72fb 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -106,6 +106,7 @@
> > #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
> > #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
> > #define PCIE_ATU_UPPER_TARGET 0x91C
> > +#define PCIE_ATU_UPPER_LIMIT 0x924
> >
> > #define PCIE_MISC_CONTROL_1_OFF 0x8BC
> > #define PCIE_DBI_RO_WR_EN BIT(0)
> > --
> > 2.7.4
> >