by Alexandre Mergnat

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Subject: Re: [PATCH RESEND v6 09/11] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195

On 31/07/2023 12:27, AngeloGioacchino Del Regno wrote:
> Il 28/07/23 14:58, Alexandre Mergnat ha scritto:
>> Hi Angelo
>>
>> On 27/07/2023 15:06, AngeloGioacchino Del Regno wrote:
>>>>> +/* For 10 bit LUT layout, R/G/B are in the same register */
>>>>> #define DISP_GAMMA_LUT_10BIT_R            GENMASK(29, 20)
>>>>> #define DISP_GAMMA_LUT_10BIT_G            GENMASK(19, 10)
>>>>> #define DISP_GAMMA_LUT_10BIT_B            GENMASK(9, 0)
>>>>> +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */
>>>>
>>>> As I understood from the application processor registers (v0.4), R/G
>>>> are in LUT, B is in LUT1 for 10bit and 12bit for MT8195. Can you
>>>> check please to be sure ?
>>>>
>>>
>>> That's right, but here I'm implying that 10-bit LUT is only for older
>>> SoCs, and
>>> all of them have got the same register layout with one LUT register
>>> for R, G, B,
>>> while all the new SoCs, which have got 12-bits LUT support, have got
>>> the new
>>> register layout with two LUT registers (and multiple banks).
>>> Infact, the MT8195 SoC was added here with 12-bits LUT support only
>>> (as the LUT
>>> parameters extraction is easily handled by the
>>> drm_color_lut_extract() function).
>>>
>>> The alternative would've been to add two compatibles, like
>>> "mediatek,mt8195-disp-gamma-10bits" and
>>> "mediatek,mt8195-disp-gamma-12bits",
>>> or a boolean property like "mediatek,lut-12bits" which would appear
>>> literally
>>> everywhere starting from a certain point in time (since there's no
>>> reason to
>>> use 10-bits LUT on MT8195, that starts now!).
>>>
>>> Even then, consider the complication in code, where
>>> mtk_gamma_set_common()
>>> would have to handle:
>>> - 10-bits, layout A
>>> - 10-bits, layout B -> but fallback to layout A if this is AAL
>>> - 12-bits layout
>>>
>>> is_aal = !(gamma && gamma->data);
>>>
>>> for_each_bank()
>>> {
>>>      if (num_lut_banks > 1) write_num_bank();
>>>
>>>      for (i = 0; i < lut_bank_size; i++) {
>>>          .......
>>>
>>>          if (!lut_diff || (i % 2 == 0)) {
>>>              if (lut_bits == 12 || (lut_bits == 10 && layout_b)) {
>>>                  ... setup word[0],[1] ...
>>>              } else if (layout_b && !is_aal) {
>>>                  ...setup word[0],[1]...
>>>              } else {
>>>                  ...setup word[0]
>>>              }
>>>          } else {
>>>               ^^^ almost repeat the same ^^^
>>>          }
>>>          writel(word[0], (...));
>>>          if (lut_bits == 12 || (lut_bits == 10 && layout_b) && !is_aal)
>>>              writel(word[i] (....));
>>>      }
>>> }
>>>
>>> probe() {
>>>      if (of_property_read_bool(dev->of_node, "mediatek,lut-12bits") ||
>>>          data->supports_only_12bits)
>>>          priv->lut_bits = 12;
>>>      else
>>>          priv->lut_bits = 10;
>>> }
>>>
>>> ...at least, that's the implementation that I would do to solve your
>>> concern,
>>> which isn't *too bad*, but still, a big question arises here...
>>>
>>>
>>> Why should we care about supporting *both* 10-bit and 12-bit Gamma
>>> LUTs on
>>> the *same* SoC?
>>>
>>>
>>> A 12-bit LUT gives us more precision and there's no penalty if we
>>> want to
>>> convert a 10-bit LUT to a 12-bits one, as we're simply "ignoring" the
>>> value
>>> of two bits per component (no expensive calculation involved)...
>>>
>>> Is there anything that I'm underestimating here?
>>
>> Thanks for you explanation !
>> I think your choice is not bad, but it's not clear that MT8195 10 bit
>> LUT isn't supported at all.
>> So, IMHO, the first solution is to support it like you explained it
>> above, and the second solution is to add comment somewhere to clarify
>> that driver doesn't support 10 bit LUT if the SoC is able to use 12
>> bit LUT, like MT8195 10 bit.
>>
>> Is that relevant ? :D
>>
>
> Even though the same as whhat I'm doing here was already done before, as
> the
> current 10-bits LUT support ignores 9-bits LUT support, I can add a
> comment to
> the code:
>
> /*
> * SoCs supporting 12-bits LUTs are using a new register layout that does
> * always support (by HW) both 12-bits and 10-bits LUT but, on those, we
> * ignore the support for 10-bits in this driver and always use 12-bits.
> *
> * Summarizing:
> * - SoC HW support 9/10-bits LUT only
> *   - Old register layout
> *     - 10-bits LUT supported
> *     - 9-bits LUT not supported
> * - SoC HW support both 10/12bits LUT
> *   - New register layout
> *    - 12-bits LUT supported
> *    - 10-its LUT not supported
> */
>
> Where the SoCs supporting 9-bits and 10-bits: mt6795, 8173, 8192,others and
> 12-bits are 8195, 8186, others.. of course.
>
> Would that work for you?

Sound good for me. After that:

Reviewed-by: Alexandre Mergnat <[email protected]>

--
Regards,
Alexandre

2023-07-31 12:50:38

by AngeloGioacchino Del Regno

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Subject: Re: [PATCH RESEND v6 03/11] drm/mediatek: gamma: Support SoC specific LUT size

Il 31/07/23 12:40, AngeloGioacchino Del Regno ha scritto:
> Il 31/07/23 09:49, CK Hu (胡俊光) ha scritto:
>> Hi, Angelo:
>>
>> On Thu, 2023-07-27 at 11:46 +0200, AngeloGioacchino Del Regno wrote:
>>> Newer SoCs support a bigger Gamma LUT table: wire up a callback
>>> to retrieve the correct LUT size for each different Gamma IP.
>>>
>>> Co-developed-by: Jason-JH.Lin <[email protected]>
>>> Signed-off-by: Jason-JH.Lin <[email protected]>
>>> [Angelo: Rewritten commit message/description + porting]
>>> Signed-off-by: AngeloGioacchino Del Regno <
>>> [email protected]>
>>> Reviewed-by: Jason-JH.Lin <[email protected]>
>>> ---
>>> drivers/gpu/drm/mediatek/mtk_disp_drv.h     | 1 +
>>> drivers/gpu/drm/mediatek/mtk_disp_gamma.c   | 25 ++++++++++++++++++-
>>> --
>>> drivers/gpu/drm/mediatek/mtk_drm_crtc.c     | 4 ++--
>>> drivers/gpu/drm/mediatek/mtk_drm_crtc.h     | 1 -
>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
>>> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++++++++
>>> 6 files changed, 35 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
>>> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
>>> index 75045932353e..e554b19f4830 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
>>> @@ -53,6 +53,7 @@ void mtk_gamma_clk_disable(struct device *dev);
>>> void mtk_gamma_config(struct device *dev, unsigned int w,
>>>                 unsigned int h, unsigned int vrefresh,
>>>                 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
>>> +unsigned int mtk_gamma_get_lut_size(struct device *dev);
>>> void mtk_gamma_set(struct device *dev, struct drm_crtc_state
>>> *state);
>>> void mtk_gamma_set_common(struct device *dev, void __iomem *regs,
>>> struct drm_crtc_state *state);
>>> void mtk_gamma_start(struct device *dev);
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>>> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>>> index ce6f2499b891..b25ba209e7a4 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>>> @@ -25,10 +25,12 @@
>>> #define DISP_GAMMA_LUT                0x0700
>>> #define LUT_10BIT_MASK                0x03ff
>>> +#define LUT_SIZE_DEFAULT            512
>>> struct mtk_disp_gamma_data {
>>>       bool has_dither;
>>>       bool lut_diff;
>>> +    u16 lut_size;
>>> };
>>> /*
>>> @@ -55,6 +57,17 @@ void mtk_gamma_clk_disable(struct device *dev)
>>>       clk_disable_unprepare(gamma->clk);
>>> }
>>> +unsigned int mtk_gamma_get_lut_size(struct device *dev)
>>> +{
>>> +    struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
>>> +    unsigned int lut_size = LUT_SIZE_DEFAULT;
>>> +
>>> +    if (gamma && gamma->data)
>>> +        lut_size = gamma->data->lut_size;
>>> +
>>> +    return lut_size;
>>> +}
>>> +
>>> void mtk_gamma_set_common(struct device *dev, void __iomem *regs,
>>> struct drm_crtc_state *state)
>>> {
>>>       struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
>>> @@ -62,6 +75,7 @@ void mtk_gamma_set_common(struct device *dev, void
>>> __iomem *regs, struct drm_crt
>>>       struct drm_color_lut *lut;
>>>       void __iomem *lut_base;
>>>       bool lut_diff;
>>> +    u16 lut_size;
>>>       u32 word;
>>>       u32 diff[3] = {0};
>>> @@ -69,17 +83,20 @@ void mtk_gamma_set_common(struct device *dev,
>>> void __iomem *regs, struct drm_crt
>>>       if (!state->gamma_lut)
>>>           return;
>>> -    if (gamma && gamma->data)
>>> +    if (gamma && gamma->data) {
>>>           lut_diff = gamma->data->lut_diff;
>>> -    else
>>> +        lut_size = gamma->data->lut_size;
>>> +    } else {
>>>           lut_diff = false;
>>> +        lut_size = LUT_SIZE_DEFAULT;
>>> +    }
>>>       reg = readl(regs + DISP_GAMMA_CFG);
>>>       reg = reg | GAMMA_LUT_EN;
>>>       writel(reg, regs + DISP_GAMMA_CFG);
>>>       lut_base = regs + DISP_GAMMA_LUT;
>>>       lut = (struct drm_color_lut *)state->gamma_lut->data;
>>> -    for (i = 0; i < MTK_LUT_SIZE; i++) {
>>> +    for (i = 0; i < lut_size; i++) {
>>>           if (!lut_diff || (i % 2 == 0)) {
>>>               word = (((lut[i].red >> 6) & LUT_10BIT_MASK) <<
>>> 20) +
>>>                   (((lut[i].green >> 6) & LUT_10BIT_MASK)
>>> << 10) +
>>> @@ -196,10 +213,12 @@ static int mtk_disp_gamma_remove(struct
>>> platform_device *pdev)
>>> static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
>>>       .has_dither = true,
>>> +    .lut_size = 512,
>>> };
>>> static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = {
>>>       .lut_diff = true,
>>> +    .lut_size = 512,
>>> };
>>> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =
>>> {
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> index d40142842f85..0df62b076f49 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> @@ -958,8 +958,8 @@ int mtk_drm_crtc_create(struct drm_device
>>> *drm_dev,
>>>           mtk_crtc->ddp_comp[i] = comp;
>>>           if (comp->funcs) {
>>> -            if (comp->funcs->gamma_set)
>>> -                gamma_lut_size = MTK_LUT_SIZE;
>>> +            if (comp->funcs->gamma_set && comp->funcs-
>>>> gamma_get_lut_size)
>>> +                gamma_lut_size =
>>> mtk_ddp_gamma_get_lut_size(comp);
>>
>> In this patch, for AAL, the gamma_lut_size is not defined.
>>
>
> It is defined: AAL will call mtk_gamma_set_common(), which will use
> the "DEFAULT" (512) LUT size if no platform data was provided and the
> platform data can only come from the mtk_gamma driver - so, if the
> call to mtk_gamma_set_common() comes from mtk_aal, it will use 512.
>
> P.S.: The call to drm_mode_crtc_set_gamma_size() is performed only if
>       gamma_lut_size > 0.
>

Actually, I see what you mean now. Gets fixed in v7. Thanks!

> Regards,
> Angelo
>
>> Regards,
>> CK
>>
>>>               if (comp->funcs->ctm_set)
>>>                   has_ctm = true;
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
>>> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
>>> index 3e9046993d09..b2e50292e57d 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
>>> @@ -10,7 +10,6 @@
>>> #include "mtk_drm_ddp_comp.h"
>>> #include "mtk_drm_plane.h"
>>> -#define MTK_LUT_SIZE    512
>>> #define MTK_MAX_BPC    10
>>> #define MTK_MIN_BPC    3
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
>>> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
>>> index f114da4d36a9..c77af2e4000f 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
>>> @@ -322,6 +322,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi =
>>> {
>>> static const struct mtk_ddp_comp_funcs ddp_gamma = {
>>>       .clk_enable = mtk_gamma_clk_enable,
>>>       .clk_disable = mtk_gamma_clk_disable,
>>> +    .gamma_get_lut_size = mtk_gamma_get_lut_size,
>>>       .gamma_set = mtk_gamma_set,
>>>       .config = mtk_gamma_config,
>>>       .start = mtk_gamma_start,
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
>>> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
>>> index febcaeef16a1..c1355960e195 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
>>> @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs {
>>>       void (*layer_config)(struct device *dev, unsigned int idx,
>>>                    struct mtk_plane_state *state,
>>>                    struct cmdq_pkt *cmdq_pkt);
>>> +    unsigned int (*gamma_get_lut_size)(struct device *dev);
>>>       void (*gamma_set)(struct device *dev,
>>>                 struct drm_crtc_state *state);
>>>       void (*bgclr_in_on)(struct device *dev);
>>> @@ -186,6 +187,14 @@ static inline void
>>> mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp,
>>>           comp->funcs->layer_config(comp->dev, idx, state,
>>> cmdq_pkt);
>>> }
>>> +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct
>>> mtk_ddp_comp *comp)
>>> +{
>>> +    if (comp->funcs && comp->funcs->gamma_get_lut_size)
>>> +        return comp->funcs->gamma_get_lut_size(comp->dev);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp,
>>>                        struct drm_crtc_state *state)
>>> {
>
>
>