Add support for clock and power domain nodes in dts for zynqmp.
Rajan Vaja (3):
arm64: dts: xilinx: Add the clock nodes for zynqmp
arm64: dts: xilinx: Remove dtsi for fixed clock
arm64: dts: xilinx: Add the power nodes for zynqmp
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 --------------------
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 72 ++++++-
16 files changed, 318 insertions(+), 239 deletions(-)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
delete mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
--
2.7.4
Add power domain nodes for zynqmp.
Signed-off-by: Rajan Vaja <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 ++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 59a547b..f915bc0 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,8 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/power/xlnx-zynqmp-power.h>
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
@@ -127,7 +129,14 @@
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <0x1>;
method = "smc";
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ };
+
zynqmp_clk: clock-controller {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
@@ -180,6 +189,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ power-domains = <&zynqmp_firmware PD_CAN_0>;
};
can1: can@ff070000 {
@@ -191,6 +201,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ power-domains = <&zynqmp_firmware PD_CAN_1>;
};
cci: cci@fd6e0000 {
@@ -221,6 +232,7 @@
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan2: dma@fd510000 {
@@ -231,6 +243,7 @@
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan3: dma@fd520000 {
@@ -241,6 +254,7 @@
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan4: dma@fd530000 {
@@ -251,6 +265,7 @@
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan5: dma@fd540000 {
@@ -261,6 +276,7 @@
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan6: dma@fd550000 {
@@ -271,6 +287,7 @@
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan7: dma@fd560000 {
@@ -281,6 +298,7 @@
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
fpd_dma_chan8: dma@fd570000 {
@@ -291,6 +309,7 @@
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
+ power-domains = <&zynqmp_firmware PD_GDMA>;
};
/* LPDDMA default allows only secured access. inorder to enable
@@ -305,6 +324,7 @@
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan2: dma@ffa90000 {
@@ -315,6 +335,7 @@
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan3: dma@ffaa0000 {
@@ -325,6 +346,7 @@
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan4: dma@ffab0000 {
@@ -335,6 +357,7 @@
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan5: dma@ffac0000 {
@@ -345,6 +368,7 @@
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan6: dma@ffad0000 {
@@ -355,6 +379,7 @@
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan7: dma@ffae0000 {
@@ -365,6 +390,7 @@
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
lpd_dma_chan8: dma@ffaf0000 {
@@ -375,6 +401,7 @@
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <64>;
+ power-domains = <&zynqmp_firmware PD_ADMA>;
};
mc: memory-controller@fd070000 {
@@ -393,6 +420,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_0>;
};
gem1: ethernet@ff0c0000 {
@@ -404,6 +432,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_1>;
};
gem2: ethernet@ff0d0000 {
@@ -415,6 +444,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_2>;
};
gem3: ethernet@ff0e0000 {
@@ -426,6 +456,7 @@
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_ETH_3>;
};
gpio: gpio@ff0a0000 {
@@ -438,6 +469,7 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
+ power-domains = <&zynqmp_firmware PD_GPIO>;
};
i2c0: i2c@ff020000 {
@@ -448,6 +480,7 @@
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_I2C_0>;
};
i2c1: i2c@ff030000 {
@@ -458,6 +491,7 @@
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_I2C_1>;
};
pcie: pcie@fd0e0000 {
@@ -489,6 +523,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
@@ -512,6 +547,7 @@
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
+ power-domains = <&zynqmp_firmware PD_SATA>;
};
sdhci0: mmc@ff160000 {
@@ -521,6 +557,7 @@
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_SD_0>;
};
sdhci1: mmc@ff170000 {
@@ -530,6 +567,7 @@
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_SD_1>;
};
smmu: smmu@fd800000 {
@@ -554,6 +592,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_SPI_0>;
};
spi1: spi@ff050000 {
@@ -565,6 +604,7 @@
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
+ power-domains = <&zynqmp_firmware PD_SPI_1>;
};
ttc0: timer@ff110000 {
@@ -574,6 +614,7 @@
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_0>;
};
ttc1: timer@ff120000 {
@@ -583,6 +624,7 @@
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_1>;
};
ttc2: timer@ff130000 {
@@ -592,6 +634,7 @@
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_2>;
};
ttc3: timer@ff140000 {
@@ -601,6 +644,7 @@
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
+ power-domains = <&zynqmp_firmware PD_TTC_3>;
};
uart0: serial@ff000000 {
@@ -610,6 +654,7 @@
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
+ power-domains = <&zynqmp_firmware PD_UART_0>;
};
uart1: serial@ff010000 {
@@ -619,6 +664,7 @@
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
+ power-domains = <&zynqmp_firmware PD_UART_1>;
};
usb0: usb@fe200000 {
@@ -628,6 +674,7 @@
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_USB_0>;
};
usb1: usb@fe300000 {
@@ -637,6 +684,7 @@
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
+ power-domains = <&zynqmp_firmware PD_USB_1>;
};
watchdog0: watchdog@fd4d0000 {
--
2.7.4
Add clock nodes for zynqmp based on CCF.
Signed-off-by: Rajan Vaja <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
15 files changed, 270 insertions(+), 26 deletions(-)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
new file mode 100644
index 0000000..9868ca1
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ *
+ * Michal Simek <[email protected]>
+ */
+
+#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+/ {
+ pss_ref_clk: pss_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>;
+ };
+
+ video_clk: video_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ pss_alt_ref_clk: pss_alt_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ gt_crx_ref_clk: gt_crx_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <108000000>;
+ };
+
+ aux_ref_clk: aux_ref_clk {
+ u-boot,dm-pre-reloc;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+};
+
+&can0 {
+ clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&can1 {
+ clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&cpu0 {
+ clocks = <&zynqmp_clk ACPU>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&gem0 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
+ <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem1 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+ <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem2 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
+ <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gem3 {
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
+ <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+};
+
+&gpio {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&i2c0 {
+ clocks = <&zynqmp_clk I2C0_REF>;
+};
+
+&i2c1 {
+ clocks = <&zynqmp_clk I2C1_REF>;
+};
+
+&pcie {
+ clocks = <&zynqmp_clk PCIE_REF>;
+};
+
+&sata {
+ clocks = <&zynqmp_clk SATA_REF>;
+};
+
+&sdhci0 {
+ clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&sdhci1 {
+ clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&spi0 {
+ clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&spi1 {
+ clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc0 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc1 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc2 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&ttc3 {
+ clocks = <&zynqmp_clk LPD_LSBUS>;
+};
+
+&uart0 {
+ clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&uart1 {
+ clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
+&usb0 {
+ clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&usb1 {
+ clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+};
+
+&watchdog0 {
+ clocks = <&zynqmp_clk WDT>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
index 0f7b4cf..2e05fa4 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1232 RevA";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
index 9092828..3d0aaa0 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
* Siva Durga Prasad Paladugu <[email protected]>
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1254 RevA";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
index 4f404c5..1a8127d4 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
index 9a3e39d..fa7eb1b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
index 2421ec7..4191dfa 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
index 7a49dee..3750690 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
index 54c7b4f..2366cd9 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
index b8b5ff1..9a894e6 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Siva Durga Prasad <[email protected]>
* Michal Simek <[email protected]>
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
index e5699d0..3e39454 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
- * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ * (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
* Nathalie Chan King Choy
@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 2a3b665..f6e9558 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
index 8f45614..f457f8a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 93ce7eb..f15b99a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
index 8bb0001..e27cd60 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*/
@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 9aa6734..59a547b 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
- * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ * (C) Copyright 2014 - 2019, Xilinx, Inc.
*
* Michal Simek <[email protected]>
*
@@ -124,6 +124,28 @@
<1 10 0xf08>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ zynqmp_clk: clock-controller {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>,
+ <&video_clk>,
+ <&pss_alt_ref_clk>,
+ <&aux_ref_clk>,
+ <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk",
+ "video_clk",
+ "pss_alt_ref_clk",
+ "aux_ref_clk",
+ "gt_crx_ref_clk";
+ };
+ };
+ };
+
amba_apu: amba-apu@0 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.7.4
Currently CCF clocks sre used in zynqmp dts. So there is no use of
dtsi for fixed clock. Remove dtsi for fixed clock.
Signed-off-by: Rajan Vaja <[email protected]>
---
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 -----------------------------
1 file changed, 213 deletions(-)
delete mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
deleted file mode 100644
index 306ad21..0000000
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Clock specification for Xilinx ZynqMP
- *
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
- *
- * Michal Simek <[email protected]>
- */
-
-/ {
- clk100: clk100 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- clk125: clk125 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
-
- clk200: clk200 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-
- clk250: clk250 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
-
- clk300: clk300 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <300000000>;
- };
-
- clk600: clk600 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- };
-
- dp_aclk: clock0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-accuracy = <100>;
- };
-
- dp_aud_clk: clock1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24576000>;
- clock-accuracy = <100>;
- };
-
- dpdma_clk: dpdma-clk {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <533000000>;
- };
-
- drm_clock: drm-clock {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <262750000>;
- clock-accuracy = <0x64>;
- };
-};
-
-&can0 {
- clocks = <&clk100 &clk100>;
-};
-
-&can1 {
- clocks = <&clk100 &clk100>;
-};
-
-&fpd_dma_chan1 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan2 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan3 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan4 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan5 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan6 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan7 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&fpd_dma_chan8 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan1 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan2 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan3 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan4 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan5 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan6 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan7 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&lpd_dma_chan8 {
- clocks = <&clk600>, <&clk100>;
-};
-
-&gem0 {
- clocks = <&clk125>, <&clk125>, <&clk125>;
-};
-
-&gem1 {
- clocks = <&clk125>, <&clk125>, <&clk125>;
-};
-
-&gem2 {
- clocks = <&clk125>, <&clk125>, <&clk125>;
-};
-
-&gem3 {
- clocks = <&clk125>, <&clk125>, <&clk125>;
-};
-
-&gpio {
- clocks = <&clk100>;
-};
-
-&i2c0 {
- clocks = <&clk100>;
-};
-
-&i2c1 {
- clocks = <&clk100>;
-};
-
-&sata {
- clocks = <&clk250>;
-};
-
-&sdhci0 {
- clocks = <&clk200 &clk200>;
-};
-
-&sdhci1 {
- clocks = <&clk200 &clk200>;
-};
-
-&spi0 {
- clocks = <&clk200 &clk200>;
-};
-
-&spi1 {
- clocks = <&clk200 &clk200>;
-};
-
-&uart0 {
- clocks = <&clk100 &clk100>;
-};
-
-&uart1 {
- clocks = <&clk100 &clk100>;
-};
-
-&usb0 {
- clocks = <&clk250>, <&clk250>;
-};
-
-&usb1 {
- clocks = <&clk250>, <&clk250>;
-};
-
-&watchdog0 {
- clocks = <&clk250>;
-};
--
2.7.4
On 07. 11. 19 10:44, Rajan Vaja wrote:
> Add power domain nodes for zynqmp.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 ++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 59a547b..f915bc0 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -12,6 +12,8 @@
> * the License, or (at your option) any later version.
> */
>
> +#include <dt-bindings/power/xlnx-zynqmp-power.h>
> +
> / {
> compatible = "xlnx,zynqmp";
> #address-cells = <2>;
> @@ -127,7 +129,14 @@
> firmware {
> zynqmp_firmware: zynqmp-firmware {
> compatible = "xlnx,zynqmp-firmware";
> + #power-domain-cells = <0x1>;
Applied but here with just 1 instead of 0x1
Thanks,
Michal
On 07. 11. 19 10:44, Rajan Vaja wrote:
> Add support for clock and power domain nodes in dts for zynqmp.
>
> Rajan Vaja (3):
> arm64: dts: xilinx: Add the clock nodes for zynqmp
> arm64: dts: xilinx: Remove dtsi for fixed clock
> arm64: dts: xilinx: Add the power nodes for zynqmp
>
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 --------------------
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 72 ++++++-
> 16 files changed, 318 insertions(+), 239 deletions(-)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> delete mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>
Applied all and rebased on v5.5-rc1.
Thanks,
Michal
On 07.11.19 10:44, Rajan Vaja wrote:
> Add clock nodes for zynqmp based on CCF.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
> 15 files changed, 270 insertions(+), 26 deletions(-)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> new file mode 100644
> index 0000000..9868ca1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Clock specification for Xilinx ZynqMP
> + *
> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
> + *
> + * Michal Simek <[email protected]>
> + */
> +
> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
> +/ {
> + pss_ref_clk: pss_ref_clk {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <33333333>;
> + };
> +
> + video_clk: video_clk {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + };
> +
> + pss_alt_ref_clk: pss_alt_ref_clk {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +
> + gt_crx_ref_clk: gt_crx_ref_clk {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <108000000>;
> + };
> +
> + aux_ref_clk: aux_ref_clk {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + };
> +};
> +
> +&can0 {
> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&can1 {
> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&cpu0 {
> + clocks = <&zynqmp_clk ACPU>;
> +};
> +
> +&fpd_dma_chan1 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan2 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan3 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan4 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan5 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan6 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan7 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&fpd_dma_chan8 {
> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan1 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan2 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan3 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan4 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan5 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan6 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan7 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&lpd_dma_chan8 {
> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&gem0 {
> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
> + <&zynqmp_clk GEM_TSU>;
> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> +};
> +
> +&gem1 {
> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
> + <&zynqmp_clk GEM_TSU>;
> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> +};
> +
> +&gem2 {
> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
> + <&zynqmp_clk GEM_TSU>;
> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> +};
> +
> +&gem3 {
> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
> + <&zynqmp_clk GEM_TSU>;
> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
> +};
> +
> +&gpio {
> + clocks = <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&i2c0 {
> + clocks = <&zynqmp_clk I2C0_REF>;
> +};
> +
> +&i2c1 {
> + clocks = <&zynqmp_clk I2C1_REF>;
> +};
> +
> +&pcie {
> + clocks = <&zynqmp_clk PCIE_REF>;
> +};
> +
> +&sata {
> + clocks = <&zynqmp_clk SATA_REF>;
> +};
> +
> +&sdhci0 {
> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&sdhci1 {
> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&spi0 {
> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&spi1 {
> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&ttc0 {
> + clocks = <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&ttc1 {
> + clocks = <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&ttc2 {
> + clocks = <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&ttc3 {
> + clocks = <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&uart0 {
> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&uart1 {
> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
> +};
> +
> +&usb0 {
> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
> +};
> +
> +&usb1 {
> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
> +};
> +
> +&watchdog0 {
> + clocks = <&zynqmp_clk WDT>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> index 0f7b4cf..2e05fa4 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZC1232
> *
> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
>
> / {
> model = "ZynqMP ZC1232 RevA";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> index 9092828..3d0aaa0 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZC1254
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> * Siva Durga Prasad Paladugu <[email protected]>
> @@ -11,7 +11,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
>
> / {
> model = "ZynqMP ZC1254 RevA";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> index 4f404c5..1a8127d4 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> @@ -11,7 +11,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
>
> / {
> model = "ZynqMP ZC1275 RevA";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> index 9a3e39d..fa7eb1b 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> index 2421ec7..4191dfa 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
> index 7a49dee..3750690 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
> *
> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
>
> / {
> model = "ZynqMP zc1751-xm017-dc3 RevA";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> index 54c7b4f..2366cd9 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
>
> / {
> model = "ZynqMP zc1751-xm018-dc4";
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> index b8b5ff1..9a894e6 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Siva Durga Prasad <[email protected]>
> * Michal Simek <[email protected]>
> @@ -11,7 +11,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> index e5699d0..3e39454 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZCU100 revC
> *
> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> * Nathalie Chan King Choy
> @@ -11,7 +11,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/gpio/gpio.h>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> index 2a3b665..f6e9558 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZCU102 RevA
> *
> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/gpio/gpio.h>
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> index 8f45614..f457f8a 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZCU104
> *
> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index 93ce7eb..f15b99a 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZCU106
> *
> - * (C) Copyright 2016, Xilinx, Inc.
> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/gpio/gpio.h>
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> index 8bb0001..e27cd60 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZCU111
> *
> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> */
> @@ -10,7 +10,7 @@
> /dts-v1/;
>
> #include "zynqmp.dtsi"
> -#include "zynqmp-clk.dtsi"
> +#include "zynqmp-clk-ccf.dtsi"
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/gpio/gpio.h>
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 9aa6734..59a547b 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP
> *
> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> *
> @@ -124,6 +124,28 @@
> <1 10 0xf08>;
> };
>
> + firmware {
> + zynqmp_firmware: zynqmp-firmware {
> + compatible = "xlnx,zynqmp-firmware";
> + method = "smc";
> + zynqmp_clk: clock-controller {
> + u-boot,dm-pre-reloc;
> + #clock-cells = <1>;
> + compatible = "xlnx,zynqmp-clk";
> + clocks = <&pss_ref_clk>,
> + <&video_clk>,
> + <&pss_alt_ref_clk>,
> + <&aux_ref_clk>,
> + <>_crx_ref_clk>;
> + clock-names = "pss_ref_clk",
> + "video_clk",
> + "pss_alt_ref_clk",
> + "aux_ref_clk",
> + "gt_crx_ref_clk";
> + };
> + };
> + };
> +
> amba_apu: amba-apu@0 {
> compatible = "simple-bus";
> #address-cells = <2>;
>
Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
Starting from this commit on, I'm no longer getting the kernel to boot
on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
DTBs back before this commit, even a kernel from today's head is fine.
Further versions of potential relevance:
- PMUFW 2019.1 and 2020.2
- TF-A 2.3
- U-Boot 2020.10
What's missing? I suspect someone forgot to document a subtle dependency
of this change.
Thanks,
Jan
On 01.04.21 13:42, Michal Simek wrote:
> Hi Jan,
>
> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>> On 07.11.19 10:44, Rajan Vaja wrote:
>>> Add clock nodes for zynqmp based on CCF.
>>>
>>> Signed-off-by: Rajan Vaja <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>> new file mode 100644
>>> index 0000000..9868ca1
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>> @@ -0,0 +1,222 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Clock specification for Xilinx ZynqMP
>>> + *
>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>> + *
>>> + * Michal Simek <[email protected]>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>> +/ {
>>> + pss_ref_clk: pss_ref_clk {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <33333333>;
>>> + };
>>> +
>>> + video_clk: video_clk {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <27000000>;
>>> + };
>>> +
>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <0>;
>>> + };
>>> +
>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <108000000>;
>>> + };
>>> +
>>> + aux_ref_clk: aux_ref_clk {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <27000000>;
>>> + };
>>> +};
>>> +
>>> +&can0 {
>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&can1 {
>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&cpu0 {
>>> + clocks = <&zynqmp_clk ACPU>;
>>> +};
>>> +
>>> +&fpd_dma_chan1 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan2 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan3 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan4 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan5 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan6 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan7 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&fpd_dma_chan8 {
>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan1 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan2 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan3 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan4 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan5 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan6 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan7 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&lpd_dma_chan8 {
>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&gem0 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>> + <&zynqmp_clk GEM_TSU>;
>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>> +};
>>> +
>>> +&gem1 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>> + <&zynqmp_clk GEM_TSU>;
>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>> +};
>>> +
>>> +&gem2 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>> + <&zynqmp_clk GEM_TSU>;
>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>> +};
>>> +
>>> +&gem3 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>> + <&zynqmp_clk GEM_TSU>;
>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>> +};
>>> +
>>> +&gpio {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&i2c0 {
>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>> +};
>>> +
>>> +&i2c1 {
>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>> +};
>>> +
>>> +&pcie {
>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>> +};
>>> +
>>> +&sata {
>>> + clocks = <&zynqmp_clk SATA_REF>;
>>> +};
>>> +
>>> +&sdhci0 {
>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&sdhci1 {
>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&spi0 {
>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&spi1 {
>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&ttc0 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&ttc1 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&ttc2 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&ttc3 {
>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&uart0 {
>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&uart1 {
>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>> +};
>>> +
>>> +&usb0 {
>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>> +};
>>> +
>>> +&usb1 {
>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>> +};
>>> +
>>> +&watchdog0 {
>>> + clocks = <&zynqmp_clk WDT>;
>>> +};
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> index 0f7b4cf..2e05fa4 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZC1232
>>> *
>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>>
>>> / {
>>> model = "ZynqMP ZC1232 RevA";
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> index 9092828..3d0aaa0 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZC1254
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> * Siva Durga Prasad Paladugu <[email protected]>
>>> @@ -11,7 +11,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>>
>>> / {
>>> model = "ZynqMP ZC1254 RevA";
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>> index 4f404c5..1a8127d4 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>> @@ -11,7 +11,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>>
>>> / {
>>> model = "ZynqMP ZC1275 RevA";
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> index 9a3e39d..fa7eb1b 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> / {
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>> index 2421ec7..4191dfa 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> / {
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>> index 7a49dee..3750690 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>> *
>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>>
>>> / {
>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> index 54c7b4f..2366cd9 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>>
>>> / {
>>> model = "ZynqMP zc1751-xm018-dc4";
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>> index b8b5ff1..9a894e6 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Siva Durga Prasad <[email protected]>
>>> * Michal Simek <[email protected]>
>>> @@ -11,7 +11,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> / {
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>> index e5699d0..3e39454 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>> *
>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> * Nathalie Chan King Choy
>>> @@ -11,7 +11,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/input/input.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> index 2a3b665..f6e9558 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>> *
>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/input/input.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>> index 8f45614..f457f8a 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZCU104
>>> *
>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> / {
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>> index 93ce7eb..f15b99a 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZCU106
>>> *
>>> - * (C) Copyright 2016, Xilinx, Inc.
>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/input/input.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>> index 8bb0001..e27cd60 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP ZCU111
>>> *
>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> */
>>> @@ -10,7 +10,7 @@
>>> /dts-v1/;
>>>
>>> #include "zynqmp.dtsi"
>>> -#include "zynqmp-clk.dtsi"
>>> +#include "zynqmp-clk-ccf.dtsi"
>>> #include <dt-bindings/input/input.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> index 9aa6734..59a547b 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> @@ -2,7 +2,7 @@
>>> /*
>>> * dts file for Xilinx ZynqMP
>>> *
>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>> *
>>> * Michal Simek <[email protected]>
>>> *
>>> @@ -124,6 +124,28 @@
>>> <1 10 0xf08>;
>>> };
>>>
>>> + firmware {
>>> + zynqmp_firmware: zynqmp-firmware {
>>> + compatible = "xlnx,zynqmp-firmware";
>>> + method = "smc";
>>> + zynqmp_clk: clock-controller {
>>> + u-boot,dm-pre-reloc;
>>> + #clock-cells = <1>;
>>> + compatible = "xlnx,zynqmp-clk";
>>> + clocks = <&pss_ref_clk>,
>>> + <&video_clk>,
>>> + <&pss_alt_ref_clk>,
>>> + <&aux_ref_clk>,
>>> + <>_crx_ref_clk>;
>>> + clock-names = "pss_ref_clk",
>>> + "video_clk",
>>> + "pss_alt_ref_clk",
>>> + "aux_ref_clk",
>>> + "gt_crx_ref_clk";
>>> + };
>>> + };
>>> + };
>>> +
>>> amba_apu: amba-apu@0 {
>>> compatible = "simple-bus";
>>> #address-cells = <2>;
>>>
>>
>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>> Starting from this commit on, I'm no longer getting the kernel to boot
>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>> DTBs back before this commit, even a kernel from today's head is fine.
>>
>> Further versions of potential relevance:
>> - PMUFW 2019.1 and 2020.2
>> - TF-A 2.3
>> - U-Boot 2020.10
>>
>> What's missing? I suspect someone forgot to document a subtle dependency
>> of this change.
>
> Does this fix your issue?
> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
missing even more. If you have some reference, I'm happy to try. I
suspect that earlyprintk will also not reveal more without clocks (but I
didn't play with that yet).
Meanwhile, I'm carrying a revert of this commit and a related cleanup.
That helps for now.
Jan
Hi Jan,
On 3/27/21 8:55 PM, Jan Kiszka wrote:
> On 07.11.19 10:44, Rajan Vaja wrote:
>> Add clock nodes for zynqmp based on CCF.
>>
>> Signed-off-by: Rajan Vaja <[email protected]>
>> ---
>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>> 15 files changed, 270 insertions(+), 26 deletions(-)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>> new file mode 100644
>> index 0000000..9868ca1
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>> @@ -0,0 +1,222 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Clock specification for Xilinx ZynqMP
>> + *
>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>> + *
>> + * Michal Simek <[email protected]>
>> + */
>> +
>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>> +/ {
>> + pss_ref_clk: pss_ref_clk {
>> + u-boot,dm-pre-reloc;
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <33333333>;
>> + };
>> +
>> + video_clk: video_clk {
>> + u-boot,dm-pre-reloc;
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <27000000>;
>> + };
>> +
>> + pss_alt_ref_clk: pss_alt_ref_clk {
>> + u-boot,dm-pre-reloc;
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <0>;
>> + };
>> +
>> + gt_crx_ref_clk: gt_crx_ref_clk {
>> + u-boot,dm-pre-reloc;
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <108000000>;
>> + };
>> +
>> + aux_ref_clk: aux_ref_clk {
>> + u-boot,dm-pre-reloc;
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <27000000>;
>> + };
>> +};
>> +
>> +&can0 {
>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&can1 {
>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&cpu0 {
>> + clocks = <&zynqmp_clk ACPU>;
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan1 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan2 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan3 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan4 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan5 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan6 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan7 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&lpd_dma_chan8 {
>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&gem0 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>> + <&zynqmp_clk GEM_TSU>;
>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>> +};
>> +
>> +&gem1 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>> + <&zynqmp_clk GEM_TSU>;
>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>> +};
>> +
>> +&gem2 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>> + <&zynqmp_clk GEM_TSU>;
>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>> +};
>> +
>> +&gem3 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>> + <&zynqmp_clk GEM_TSU>;
>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>> +};
>> +
>> +&gpio {
>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&i2c0 {
>> + clocks = <&zynqmp_clk I2C0_REF>;
>> +};
>> +
>> +&i2c1 {
>> + clocks = <&zynqmp_clk I2C1_REF>;
>> +};
>> +
>> +&pcie {
>> + clocks = <&zynqmp_clk PCIE_REF>;
>> +};
>> +
>> +&sata {
>> + clocks = <&zynqmp_clk SATA_REF>;
>> +};
>> +
>> +&sdhci0 {
>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&sdhci1 {
>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&spi0 {
>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&spi1 {
>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&ttc0 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&ttc1 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&ttc2 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&ttc3 {
>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&uart0 {
>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&uart1 {
>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>> +};
>> +
>> +&usb0 {
>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>> +};
>> +
>> +&usb1 {
>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>> +};
>> +
>> +&watchdog0 {
>> + clocks = <&zynqmp_clk WDT>;
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>> index 0f7b4cf..2e05fa4 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZC1232
>> *
>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>>
>> / {
>> model = "ZynqMP ZC1232 RevA";
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>> index 9092828..3d0aaa0 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZC1254
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> * Siva Durga Prasad Paladugu <[email protected]>
>> @@ -11,7 +11,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>>
>> / {
>> model = "ZynqMP ZC1254 RevA";
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>> index 4f404c5..1a8127d4 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>> @@ -11,7 +11,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>>
>> / {
>> model = "ZynqMP ZC1275 RevA";
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>> index 9a3e39d..fa7eb1b 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>> index 2421ec7..4191dfa 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>> index 7a49dee..3750690 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>> *
>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>>
>> / {
>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>> index 54c7b4f..2366cd9 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>>
>> / {
>> model = "ZynqMP zc1751-xm018-dc4";
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>> index b8b5ff1..9a894e6 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Siva Durga Prasad <[email protected]>
>> * Michal Simek <[email protected]>
>> @@ -11,7 +11,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> index e5699d0..3e39454 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZCU100 revC
>> *
>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> * Nathalie Chan King Choy
>> @@ -11,7 +11,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/gpio/gpio.h>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> index 2a3b665..f6e9558 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZCU102 RevA
>> *
>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>> index 8f45614..f457f8a 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZCU104
>> *
>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>> index 93ce7eb..f15b99a 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZCU106
>> *
>> - * (C) Copyright 2016, Xilinx, Inc.
>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>> index 8bb0001..e27cd60 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP ZCU111
>> *
>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> */
>> @@ -10,7 +10,7 @@
>> /dts-v1/;
>>
>> #include "zynqmp.dtsi"
>> -#include "zynqmp-clk.dtsi"
>> +#include "zynqmp-clk-ccf.dtsi"
>> #include <dt-bindings/input/input.h>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> index 9aa6734..59a547b 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>> @@ -2,7 +2,7 @@
>> /*
>> * dts file for Xilinx ZynqMP
>> *
>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>> *
>> * Michal Simek <[email protected]>
>> *
>> @@ -124,6 +124,28 @@
>> <1 10 0xf08>;
>> };
>>
>> + firmware {
>> + zynqmp_firmware: zynqmp-firmware {
>> + compatible = "xlnx,zynqmp-firmware";
>> + method = "smc";
>> + zynqmp_clk: clock-controller {
>> + u-boot,dm-pre-reloc;
>> + #clock-cells = <1>;
>> + compatible = "xlnx,zynqmp-clk";
>> + clocks = <&pss_ref_clk>,
>> + <&video_clk>,
>> + <&pss_alt_ref_clk>,
>> + <&aux_ref_clk>,
>> + <>_crx_ref_clk>;
>> + clock-names = "pss_ref_clk",
>> + "video_clk",
>> + "pss_alt_ref_clk",
>> + "aux_ref_clk",
>> + "gt_crx_ref_clk";
>> + };
>> + };
>> + };
>> +
>> amba_apu: amba-apu@0 {
>> compatible = "simple-bus";
>> #address-cells = <2>;
>>
>
> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
> Starting from this commit on, I'm no longer getting the kernel to boot
> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
> DTBs back before this commit, even a kernel from today's head is fine.
>
> Further versions of potential relevance:
> - PMUFW 2019.1 and 2020.2
> - TF-A 2.3
> - U-Boot 2020.10
>
> What's missing? I suspect someone forgot to document a subtle dependency
> of this change.
Does this fix your issue?
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Thanks,
Michal
On 01.04.21 16:52, Jan Kiszka wrote:
> On 01.04.21 13:42, Michal Simek wrote:
>> Hi Jan,
>>
>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>> Add clock nodes for zynqmp based on CCF.
>>>>
>>>> Signed-off-by: Rajan Vaja <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>> new file mode 100644
>>>> index 0000000..9868ca1
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>> @@ -0,0 +1,222 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * Clock specification for Xilinx ZynqMP
>>>> + *
>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>> + *
>>>> + * Michal Simek <[email protected]>
>>>> + */
>>>> +
>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>> +/ {
>>>> + pss_ref_clk: pss_ref_clk {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <33333333>;
>>>> + };
>>>> +
>>>> + video_clk: video_clk {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <27000000>;
>>>> + };
>>>> +
>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <0>;
>>>> + };
>>>> +
>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <108000000>;
>>>> + };
>>>> +
>>>> + aux_ref_clk: aux_ref_clk {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "fixed-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <27000000>;
>>>> + };
>>>> +};
>>>> +
>>>> +&can0 {
>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&can1 {
>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&cpu0 {
>>>> + clocks = <&zynqmp_clk ACPU>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan1 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan2 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan3 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan4 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan5 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan6 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan7 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&fpd_dma_chan8 {
>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan1 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan2 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan3 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan4 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan5 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan6 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan7 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&lpd_dma_chan8 {
>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&gem0 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>> + <&zynqmp_clk GEM_TSU>;
>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>> +};
>>>> +
>>>> +&gem1 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>> + <&zynqmp_clk GEM_TSU>;
>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>> +};
>>>> +
>>>> +&gem2 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>> + <&zynqmp_clk GEM_TSU>;
>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>> +};
>>>> +
>>>> +&gem3 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>> + <&zynqmp_clk GEM_TSU>;
>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>> +};
>>>> +
>>>> +&gpio {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&i2c0 {
>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>> +};
>>>> +
>>>> +&i2c1 {
>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>> +};
>>>> +
>>>> +&pcie {
>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>> +};
>>>> +
>>>> +&sata {
>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>> +};
>>>> +
>>>> +&sdhci0 {
>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&sdhci1 {
>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&spi0 {
>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&spi1 {
>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&ttc0 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&ttc1 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&ttc2 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&ttc3 {
>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&uart0 {
>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&uart1 {
>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>> +};
>>>> +
>>>> +&usb0 {
>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>> +};
>>>> +
>>>> +&usb1 {
>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>> +};
>>>> +
>>>> +&watchdog0 {
>>>> + clocks = <&zynqmp_clk WDT>;
>>>> +};
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>> index 0f7b4cf..2e05fa4 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZC1232
>>>> *
>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>
>>>> / {
>>>> model = "ZynqMP ZC1232 RevA";
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>> index 9092828..3d0aaa0 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZC1254
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> * Siva Durga Prasad Paladugu <[email protected]>
>>>> @@ -11,7 +11,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>
>>>> / {
>>>> model = "ZynqMP ZC1254 RevA";
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>> index 4f404c5..1a8127d4 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>> @@ -11,7 +11,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>
>>>> / {
>>>> model = "ZynqMP ZC1275 RevA";
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>> index 9a3e39d..fa7eb1b 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> / {
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>> index 2421ec7..4191dfa 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> / {
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>> index 7a49dee..3750690 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>> *
>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>
>>>> / {
>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>> index 54c7b4f..2366cd9 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>
>>>> / {
>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>> index b8b5ff1..9a894e6 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Siva Durga Prasad <[email protected]>
>>>> * Michal Simek <[email protected]>
>>>> @@ -11,7 +11,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> / {
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> index e5699d0..3e39454 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>> *
>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> * Nathalie Chan King Choy
>>>> @@ -11,7 +11,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/input/input.h>
>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>> #include <dt-bindings/gpio/gpio.h>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>> index 2a3b665..f6e9558 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>> *
>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/input/input.h>
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>> index 8f45614..f457f8a 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZCU104
>>>> *
>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> / {
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>> index 93ce7eb..f15b99a 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZCU106
>>>> *
>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/input/input.h>
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>> index 8bb0001..e27cd60 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP ZCU111
>>>> *
>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> */
>>>> @@ -10,7 +10,7 @@
>>>> /dts-v1/;
>>>>
>>>> #include "zynqmp.dtsi"
>>>> -#include "zynqmp-clk.dtsi"
>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>> #include <dt-bindings/input/input.h>
>>>> #include <dt-bindings/gpio/gpio.h>
>>>>
>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> index 9aa6734..59a547b 100644
>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>> @@ -2,7 +2,7 @@
>>>> /*
>>>> * dts file for Xilinx ZynqMP
>>>> *
>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>> *
>>>> * Michal Simek <[email protected]>
>>>> *
>>>> @@ -124,6 +124,28 @@
>>>> <1 10 0xf08>;
>>>> };
>>>>
>>>> + firmware {
>>>> + zynqmp_firmware: zynqmp-firmware {
>>>> + compatible = "xlnx,zynqmp-firmware";
>>>> + method = "smc";
>>>> + zynqmp_clk: clock-controller {
>>>> + u-boot,dm-pre-reloc;
>>>> + #clock-cells = <1>;
>>>> + compatible = "xlnx,zynqmp-clk";
>>>> + clocks = <&pss_ref_clk>,
>>>> + <&video_clk>,
>>>> + <&pss_alt_ref_clk>,
>>>> + <&aux_ref_clk>,
>>>> + <>_crx_ref_clk>;
>>>> + clock-names = "pss_ref_clk",
>>>> + "video_clk",
>>>> + "pss_alt_ref_clk",
>>>> + "aux_ref_clk",
>>>> + "gt_crx_ref_clk";
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> amba_apu: amba-apu@0 {
>>>> compatible = "simple-bus";
>>>> #address-cells = <2>;
>>>>
>>>
>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>
>>> Further versions of potential relevance:
>>> - PMUFW 2019.1 and 2020.2
>>> - TF-A 2.3
>>> - U-Boot 2020.10
>>>
>>> What's missing? I suspect someone forgot to document a subtle dependency
>>> of this change.
>>
>> Does this fix your issue?
>> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>>
>
> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
> missing even more. If you have some reference, I'm happy to try. I
> suspect that earlyprintk will also not reveal more without clocks (but I
> didn't play with that yet).
>
> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
> That helps for now.
>
OK, dependencies resolved (unfortunately the hard way): It either
requires TF-A master or latest release v2.4 + [1] and [2].
Those TF-A commits were upstream about a year after the firmware-based
clock control hit the kernel. A note would have been nice - or better
sychronization between both upstreaming efforts.
Jan
[1]
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c23cf053037ecc4521a7e03ba0100f1c78afd580
[2]
https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=a8b10c6490e5a4656bfa06fae5c0f19fabfe4ab2
On 19.04.21 12:52, Michal Simek wrote:
> Hi Jan,
>
> On 4/18/21 2:12 PM, Jan Kiszka wrote:
>> On 01.04.21 16:52, Jan Kiszka wrote:
>>> On 01.04.21 13:42, Michal Simek wrote:
>>>> Hi Jan,
>>>>
>>>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>>>> Add clock nodes for zynqmp based on CCF.
>>>>>>
>>>>>> Signed-off-by: Rajan Vaja <[email protected]>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>> new file mode 100644
>>>>>> index 0000000..9868ca1
>>>>>> --- /dev/null
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>> @@ -0,0 +1,222 @@
>>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>>> +/*
>>>>>> + * Clock specification for Xilinx ZynqMP
>>>>>> + *
>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>> + *
>>>>>> + * Michal Simek <[email protected]>
>>>>>> + */
>>>>>> +
>>>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>>>> +/ {
>>>>>> + pss_ref_clk: pss_ref_clk {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <33333333>;
>>>>>> + };
>>>>>> +
>>>>>> + video_clk: video_clk {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <27000000>;
>>>>>> + };
>>>>>> +
>>>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <0>;
>>>>>> + };
>>>>>> +
>>>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <108000000>;
>>>>>> + };
>>>>>> +
>>>>>> + aux_ref_clk: aux_ref_clk {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + compatible = "fixed-clock";
>>>>>> + #clock-cells = <0>;
>>>>>> + clock-frequency = <27000000>;
>>>>>> + };
>>>>>> +};
>>>>>> +
>>>>>> +&can0 {
>>>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&can1 {
>>>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&cpu0 {
>>>>>> + clocks = <&zynqmp_clk ACPU>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan1 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan2 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan3 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan4 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan5 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan6 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan7 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&fpd_dma_chan8 {
>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan1 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan2 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan3 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan4 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan5 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan6 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan7 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&lpd_dma_chan8 {
>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&gem0 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>> +};
>>>>>> +
>>>>>> +&gem1 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>> +};
>>>>>> +
>>>>>> +&gem2 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>> +};
>>>>>> +
>>>>>> +&gem3 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>> +};
>>>>>> +
>>>>>> +&gpio {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&i2c0 {
>>>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&i2c1 {
>>>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&pcie {
>>>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&sata {
>>>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&sdhci0 {
>>>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&sdhci1 {
>>>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&spi0 {
>>>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&spi1 {
>>>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&ttc0 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&ttc1 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&ttc2 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&ttc3 {
>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&uart0 {
>>>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&uart1 {
>>>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>> +};
>>>>>> +
>>>>>> +&usb0 {
>>>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&usb1 {
>>>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>> +};
>>>>>> +
>>>>>> +&watchdog0 {
>>>>>> + clocks = <&zynqmp_clk WDT>;
>>>>>> +};
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>> index 0f7b4cf..2e05fa4 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZC1232
>>>>>> *
>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>
>>>>>> / {
>>>>>> model = "ZynqMP ZC1232 RevA";
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>> index 9092828..3d0aaa0 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZC1254
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> * Siva Durga Prasad Paladugu <[email protected]>
>>>>>> @@ -11,7 +11,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>
>>>>>> / {
>>>>>> model = "ZynqMP ZC1254 RevA";
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>> index 4f404c5..1a8127d4 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>> @@ -11,7 +11,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>
>>>>>> / {
>>>>>> model = "ZynqMP ZC1275 RevA";
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>> index 9a3e39d..fa7eb1b 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> / {
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>> index 2421ec7..4191dfa 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> / {
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>> index 7a49dee..3750690 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>>>> *
>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>
>>>>>> / {
>>>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>> index 54c7b4f..2366cd9 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>
>>>>>> / {
>>>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>> index b8b5ff1..9a894e6 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Siva Durga Prasad <[email protected]>
>>>>>> * Michal Simek <[email protected]>
>>>>>> @@ -11,7 +11,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> / {
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>> index e5699d0..3e39454 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>>>> *
>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> * Nathalie Chan King Choy
>>>>>> @@ -11,7 +11,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/input/input.h>
>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>> index 2a3b665..f6e9558 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>>>> *
>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/input/input.h>
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>> index 8f45614..f457f8a 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZCU104
>>>>>> *
>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> / {
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>> index 93ce7eb..f15b99a 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZCU106
>>>>>> *
>>>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/input/input.h>
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>> index 8bb0001..e27cd60 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP ZCU111
>>>>>> *
>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> */
>>>>>> @@ -10,7 +10,7 @@
>>>>>> /dts-v1/;
>>>>>>
>>>>>> #include "zynqmp.dtsi"
>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>> #include <dt-bindings/input/input.h>
>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>> index 9aa6734..59a547b 100644
>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>> @@ -2,7 +2,7 @@
>>>>>> /*
>>>>>> * dts file for Xilinx ZynqMP
>>>>>> *
>>>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>>>> *
>>>>>> * Michal Simek <[email protected]>
>>>>>> *
>>>>>> @@ -124,6 +124,28 @@
>>>>>> <1 10 0xf08>;
>>>>>> };
>>>>>>
>>>>>> + firmware {
>>>>>> + zynqmp_firmware: zynqmp-firmware {
>>>>>> + compatible = "xlnx,zynqmp-firmware";
>>>>>> + method = "smc";
>>>>>> + zynqmp_clk: clock-controller {
>>>>>> + u-boot,dm-pre-reloc;
>>>>>> + #clock-cells = <1>;
>>>>>> + compatible = "xlnx,zynqmp-clk";
>>>>>> + clocks = <&pss_ref_clk>,
>>>>>> + <&video_clk>,
>>>>>> + <&pss_alt_ref_clk>,
>>>>>> + <&aux_ref_clk>,
>>>>>> + <>_crx_ref_clk>;
>>>>>> + clock-names = "pss_ref_clk",
>>>>>> + "video_clk",
>>>>>> + "pss_alt_ref_clk",
>>>>>> + "aux_ref_clk",
>>>>>> + "gt_crx_ref_clk";
>>>>>> + };
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> amba_apu: amba-apu@0 {
>>>>>> compatible = "simple-bus";
>>>>>> #address-cells = <2>;
>>>>>>
>>>>>
>>>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>>>
>>>>> Further versions of potential relevance:
>>>>> - PMUFW 2019.1 and 2020.2
>>>>> - TF-A 2.3
>>>>> - U-Boot 2020.10
>>>>>
>>>>> What's missing? I suspect someone forgot to document a subtle dependency
>>>>> of this change.
>>>>
>>>> Does this fix your issue?
>>>> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>>>>
>>>
>>> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
>>> missing even more. If you have some reference, I'm happy to try. I
>>> suspect that earlyprintk will also not reveal more without clocks (but I
>>> didn't play with that yet).
>>>
>>> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
>>> That helps for now.
>>>
>>
>> OK, dependencies resolved (unfortunately the hard way): It either
>> requires TF-A master or latest release v2.4 + [1] and [2].
>>
>> Those TF-A commits were upstream about a year after the firmware-based
>> clock control hit the kernel. A note would have been nice - or better
>> sychronization between both upstreaming efforts.
>
> I wasn't responsible for TFA but I found this last year in Nov timeframe
> that none really upstream this. Right now that development is working
> like that. I am asking everybody to contribute upstream to have all the
> time upstream heads to work together.
> I haven't had a time to dig into this but unfortunatelly there is no
> feature checking mechanism on zynqmp TFA side to check if this is there
> or not but we are trying our best to check as much as possible but bugs
> happen.
OK, I understand. Reminding of "upstream first" is part of my daily
business as well. :)
And integration is generally more and more complicated with the growing
number of firmware services and interfaces, not only on this SOC...
> And we are lacking space in OCM to be able to add more features to TFA
> anyway.
Yeah, I know - I'm also overflowing it via the SDEI patch [1].
Jan
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9673
Hi Jan,
On 4/18/21 2:12 PM, Jan Kiszka wrote:
> On 01.04.21 16:52, Jan Kiszka wrote:
>> On 01.04.21 13:42, Michal Simek wrote:
>>> Hi Jan,
>>>
>>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>>> Add clock nodes for zynqmp based on CCF.
>>>>>
>>>>> Signed-off-by: Rajan Vaja <[email protected]>
>>>>> ---
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>> new file mode 100644
>>>>> index 0000000..9868ca1
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>> @@ -0,0 +1,222 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>> +/*
>>>>> + * Clock specification for Xilinx ZynqMP
>>>>> + *
>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>> + *
>>>>> + * Michal Simek <[email protected]>
>>>>> + */
>>>>> +
>>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>>> +/ {
>>>>> + pss_ref_clk: pss_ref_clk {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <33333333>;
>>>>> + };
>>>>> +
>>>>> + video_clk: video_clk {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <27000000>;
>>>>> + };
>>>>> +
>>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <0>;
>>>>> + };
>>>>> +
>>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <108000000>;
>>>>> + };
>>>>> +
>>>>> + aux_ref_clk: aux_ref_clk {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <27000000>;
>>>>> + };
>>>>> +};
>>>>> +
>>>>> +&can0 {
>>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&can1 {
>>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&cpu0 {
>>>>> + clocks = <&zynqmp_clk ACPU>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan1 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan2 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan3 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan4 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan5 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan6 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan7 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&fpd_dma_chan8 {
>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan1 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan2 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan3 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan4 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan5 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan6 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan7 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&lpd_dma_chan8 {
>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&gem0 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>> +};
>>>>> +
>>>>> +&gem1 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>> +};
>>>>> +
>>>>> +&gem2 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>> +};
>>>>> +
>>>>> +&gem3 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>> +};
>>>>> +
>>>>> +&gpio {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&i2c0 {
>>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>>> +};
>>>>> +
>>>>> +&i2c1 {
>>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>>> +};
>>>>> +
>>>>> +&pcie {
>>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>>> +};
>>>>> +
>>>>> +&sata {
>>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>>> +};
>>>>> +
>>>>> +&sdhci0 {
>>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&sdhci1 {
>>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&spi0 {
>>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&spi1 {
>>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&ttc0 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&ttc1 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&ttc2 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&ttc3 {
>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&uart0 {
>>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&uart1 {
>>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>> +};
>>>>> +
>>>>> +&usb0 {
>>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>> +};
>>>>> +
>>>>> +&usb1 {
>>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>> +};
>>>>> +
>>>>> +&watchdog0 {
>>>>> + clocks = <&zynqmp_clk WDT>;
>>>>> +};
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>> index 0f7b4cf..2e05fa4 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZC1232
>>>>> *
>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>
>>>>> / {
>>>>> model = "ZynqMP ZC1232 RevA";
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>> index 9092828..3d0aaa0 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZC1254
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> * Siva Durga Prasad Paladugu <[email protected]>
>>>>> @@ -11,7 +11,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>
>>>>> / {
>>>>> model = "ZynqMP ZC1254 RevA";
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>> index 4f404c5..1a8127d4 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>> @@ -11,7 +11,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>
>>>>> / {
>>>>> model = "ZynqMP ZC1275 RevA";
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>> index 9a3e39d..fa7eb1b 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> / {
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>> index 2421ec7..4191dfa 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> / {
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>> index 7a49dee..3750690 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>>> *
>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>
>>>>> / {
>>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>> index 54c7b4f..2366cd9 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>
>>>>> / {
>>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>> index b8b5ff1..9a894e6 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Siva Durga Prasad <[email protected]>
>>>>> * Michal Simek <[email protected]>
>>>>> @@ -11,7 +11,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> / {
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>> index e5699d0..3e39454 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>>> *
>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> * Nathalie Chan King Choy
>>>>> @@ -11,7 +11,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/input/input.h>
>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>> index 2a3b665..f6e9558 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>>> *
>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/input/input.h>
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>> index 8f45614..f457f8a 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZCU104
>>>>> *
>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> / {
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>> index 93ce7eb..f15b99a 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZCU106
>>>>> *
>>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/input/input.h>
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>> index 8bb0001..e27cd60 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP ZCU111
>>>>> *
>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> */
>>>>> @@ -10,7 +10,7 @@
>>>>> /dts-v1/;
>>>>>
>>>>> #include "zynqmp.dtsi"
>>>>> -#include "zynqmp-clk.dtsi"
>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>> #include <dt-bindings/input/input.h>
>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>> index 9aa6734..59a547b 100644
>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>> @@ -2,7 +2,7 @@
>>>>> /*
>>>>> * dts file for Xilinx ZynqMP
>>>>> *
>>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>>> *
>>>>> * Michal Simek <[email protected]>
>>>>> *
>>>>> @@ -124,6 +124,28 @@
>>>>> <1 10 0xf08>;
>>>>> };
>>>>>
>>>>> + firmware {
>>>>> + zynqmp_firmware: zynqmp-firmware {
>>>>> + compatible = "xlnx,zynqmp-firmware";
>>>>> + method = "smc";
>>>>> + zynqmp_clk: clock-controller {
>>>>> + u-boot,dm-pre-reloc;
>>>>> + #clock-cells = <1>;
>>>>> + compatible = "xlnx,zynqmp-clk";
>>>>> + clocks = <&pss_ref_clk>,
>>>>> + <&video_clk>,
>>>>> + <&pss_alt_ref_clk>,
>>>>> + <&aux_ref_clk>,
>>>>> + <>_crx_ref_clk>;
>>>>> + clock-names = "pss_ref_clk",
>>>>> + "video_clk",
>>>>> + "pss_alt_ref_clk",
>>>>> + "aux_ref_clk",
>>>>> + "gt_crx_ref_clk";
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> amba_apu: amba-apu@0 {
>>>>> compatible = "simple-bus";
>>>>> #address-cells = <2>;
>>>>>
>>>>
>>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>>
>>>> Further versions of potential relevance:
>>>> - PMUFW 2019.1 and 2020.2
>>>> - TF-A 2.3
>>>> - U-Boot 2020.10
>>>>
>>>> What's missing? I suspect someone forgot to document a subtle dependency
>>>> of this change.
>>>
>>> Does this fix your issue?
>>> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>>>
>>
>> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
>> missing even more. If you have some reference, I'm happy to try. I
>> suspect that earlyprintk will also not reveal more without clocks (but I
>> didn't play with that yet).
>>
>> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
>> That helps for now.
>>
>
> OK, dependencies resolved (unfortunately the hard way): It either
> requires TF-A master or latest release v2.4 + [1] and [2].
>
> Those TF-A commits were upstream about a year after the firmware-based
> clock control hit the kernel. A note would have been nice - or better
> sychronization between both upstreaming efforts.
I wasn't responsible for TFA but I found this last year in Nov timeframe
that none really upstream this. Right now that development is working
like that. I am asking everybody to contribute upstream to have all the
time upstream heads to work together.
I haven't had a time to dig into this but unfortunatelly there is no
feature checking mechanism on zynqmp TFA side to check if this is there
or not but we are trying our best to check as much as possible but bugs
happen.
And we are lacking space in OCM to be able to add more features to TFA
anyway.
Thanks,
Michal
On 4/19/21 1:48 PM, Jan Kiszka wrote:
> On 19.04.21 12:52, Michal Simek wrote:
>> Hi Jan,
>>
>> On 4/18/21 2:12 PM, Jan Kiszka wrote:
>>> On 01.04.21 16:52, Jan Kiszka wrote:
>>>> On 01.04.21 13:42, Michal Simek wrote:
>>>>> Hi Jan,
>>>>>
>>>>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>>>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>>>>> Add clock nodes for zynqmp based on CCF.
>>>>>>>
>>>>>>> Signed-off-by: Rajan Vaja <[email protected]>
>>>>>>> ---
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>> new file mode 100644
>>>>>>> index 0000000..9868ca1
>>>>>>> --- /dev/null
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>> @@ -0,0 +1,222 @@
>>>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>>>> +/*
>>>>>>> + * Clock specification for Xilinx ZynqMP
>>>>>>> + *
>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>> + *
>>>>>>> + * Michal Simek <[email protected]>
>>>>>>> + */
>>>>>>> +
>>>>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>>>>> +/ {
>>>>>>> + pss_ref_clk: pss_ref_clk {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + #clock-cells = <0>;
>>>>>>> + clock-frequency = <33333333>;
>>>>>>> + };
>>>>>>> +
>>>>>>> + video_clk: video_clk {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + #clock-cells = <0>;
>>>>>>> + clock-frequency = <27000000>;
>>>>>>> + };
>>>>>>> +
>>>>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + #clock-cells = <0>;
>>>>>>> + clock-frequency = <0>;
>>>>>>> + };
>>>>>>> +
>>>>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + #clock-cells = <0>;
>>>>>>> + clock-frequency = <108000000>;
>>>>>>> + };
>>>>>>> +
>>>>>>> + aux_ref_clk: aux_ref_clk {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + #clock-cells = <0>;
>>>>>>> + clock-frequency = <27000000>;
>>>>>>> + };
>>>>>>> +};
>>>>>>> +
>>>>>>> +&can0 {
>>>>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&can1 {
>>>>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&cpu0 {
>>>>>>> + clocks = <&zynqmp_clk ACPU>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan1 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan2 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan3 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan4 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan5 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan6 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan7 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&fpd_dma_chan8 {
>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan1 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan2 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan3 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan4 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan5 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan6 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan7 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&lpd_dma_chan8 {
>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&gem0 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>> +};
>>>>>>> +
>>>>>>> +&gem1 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>> +};
>>>>>>> +
>>>>>>> +&gem2 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>> +};
>>>>>>> +
>>>>>>> +&gem3 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>> +};
>>>>>>> +
>>>>>>> +&gpio {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&i2c0 {
>>>>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&i2c1 {
>>>>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&pcie {
>>>>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&sata {
>>>>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&sdhci0 {
>>>>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&sdhci1 {
>>>>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&spi0 {
>>>>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&spi1 {
>>>>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&ttc0 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&ttc1 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&ttc2 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&ttc3 {
>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&uart0 {
>>>>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&uart1 {
>>>>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&usb0 {
>>>>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&usb1 {
>>>>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>> +};
>>>>>>> +
>>>>>>> +&watchdog0 {
>>>>>>> + clocks = <&zynqmp_clk WDT>;
>>>>>>> +};
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>> index 0f7b4cf..2e05fa4 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZC1232
>>>>>>> *
>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>
>>>>>>> / {
>>>>>>> model = "ZynqMP ZC1232 RevA";
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>> index 9092828..3d0aaa0 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZC1254
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> * Siva Durga Prasad Paladugu <[email protected]>
>>>>>>> @@ -11,7 +11,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>
>>>>>>> / {
>>>>>>> model = "ZynqMP ZC1254 RevA";
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>> index 4f404c5..1a8127d4 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>> @@ -11,7 +11,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>
>>>>>>> / {
>>>>>>> model = "ZynqMP ZC1275 RevA";
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>> index 9a3e39d..fa7eb1b 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> / {
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>> index 2421ec7..4191dfa 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> / {
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>> index 7a49dee..3750690 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>>>>> *
>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>
>>>>>>> / {
>>>>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>> index 54c7b4f..2366cd9 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>
>>>>>>> / {
>>>>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>> index b8b5ff1..9a894e6 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Siva Durga Prasad <[email protected]>
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> @@ -11,7 +11,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> / {
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>> index e5699d0..3e39454 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>>>>> *
>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> * Nathalie Chan King Choy
>>>>>>> @@ -11,7 +11,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>> index 2a3b665..f6e9558 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>>>>> *
>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>> index 8f45614..f457f8a 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZCU104
>>>>>>> *
>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> / {
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>> index 93ce7eb..f15b99a 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZCU106
>>>>>>> *
>>>>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>> index 8bb0001..e27cd60 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP ZCU111
>>>>>>> *
>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> */
>>>>>>> @@ -10,7 +10,7 @@
>>>>>>> /dts-v1/;
>>>>>>>
>>>>>>> #include "zynqmp.dtsi"
>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>> index 9aa6734..59a547b 100644
>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>> @@ -2,7 +2,7 @@
>>>>>>> /*
>>>>>>> * dts file for Xilinx ZynqMP
>>>>>>> *
>>>>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>>>>> *
>>>>>>> * Michal Simek <[email protected]>
>>>>>>> *
>>>>>>> @@ -124,6 +124,28 @@
>>>>>>> <1 10 0xf08>;
>>>>>>> };
>>>>>>>
>>>>>>> + firmware {
>>>>>>> + zynqmp_firmware: zynqmp-firmware {
>>>>>>> + compatible = "xlnx,zynqmp-firmware";
>>>>>>> + method = "smc";
>>>>>>> + zynqmp_clk: clock-controller {
>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>> + #clock-cells = <1>;
>>>>>>> + compatible = "xlnx,zynqmp-clk";
>>>>>>> + clocks = <&pss_ref_clk>,
>>>>>>> + <&video_clk>,
>>>>>>> + <&pss_alt_ref_clk>,
>>>>>>> + <&aux_ref_clk>,
>>>>>>> + <>_crx_ref_clk>;
>>>>>>> + clock-names = "pss_ref_clk",
>>>>>>> + "video_clk",
>>>>>>> + "pss_alt_ref_clk",
>>>>>>> + "aux_ref_clk",
>>>>>>> + "gt_crx_ref_clk";
>>>>>>> + };
>>>>>>> + };
>>>>>>> + };
>>>>>>> +
>>>>>>> amba_apu: amba-apu@0 {
>>>>>>> compatible = "simple-bus";
>>>>>>> #address-cells = <2>;
>>>>>>>
>>>>>>
>>>>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>>>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>>>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>>>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>>>>
>>>>>> Further versions of potential relevance:
>>>>>> - PMUFW 2019.1 and 2020.2
>>>>>> - TF-A 2.3
>>>>>> - U-Boot 2020.10
>>>>>>
>>>>>> What's missing? I suspect someone forgot to document a subtle dependency
>>>>>> of this change.
>>>>>
>>>>> Does this fix your issue?
>>>>> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>>>>>
>>>>
>>>> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
>>>> missing even more. If you have some reference, I'm happy to try. I
>>>> suspect that earlyprintk will also not reveal more without clocks (but I
>>>> didn't play with that yet).
>>>>
>>>> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
>>>> That helps for now.
>>>>
>>>
>>> OK, dependencies resolved (unfortunately the hard way): It either
>>> requires TF-A master or latest release v2.4 + [1] and [2].
>>>
>>> Those TF-A commits were upstream about a year after the firmware-based
>>> clock control hit the kernel. A note would have been nice - or better
>>> sychronization between both upstreaming efforts.
>>
>> I wasn't responsible for TFA but I found this last year in Nov timeframe
>> that none really upstream this. Right now that development is working
>> like that. I am asking everybody to contribute upstream to have all the
>> time upstream heads to work together.
>> I haven't had a time to dig into this but unfortunatelly there is no
>> feature checking mechanism on zynqmp TFA side to check if this is there
>> or not but we are trying our best to check as much as possible but bugs
>> happen.
>
> OK, I understand. Reminding of "upstream first" is part of my daily
> business as well. :)
>
> And integration is generally more and more complicated with the growing
> number of firmware services and interfaces, not only on this SOC...
>
>> And we are lacking space in OCM to be able to add more features to TFA
>> anyway.
>
> Yeah, I know - I'm also overflowing it via the SDEI patch [1].
I have looked at this. How are you using it now? I haven't had a chance
to take a look at it. How do you use it and test it?
We should try to minimalize amount of code and try to fit to OCM.
Thanks,
Michal
On 19.04.21 17:14, Michal Simek wrote:
>
>
> On 4/19/21 1:48 PM, Jan Kiszka wrote:
>> On 19.04.21 12:52, Michal Simek wrote:
>>> Hi Jan,
>>>
>>> On 4/18/21 2:12 PM, Jan Kiszka wrote:
>>>> On 01.04.21 16:52, Jan Kiszka wrote:
>>>>> On 01.04.21 13:42, Michal Simek wrote:
>>>>>> Hi Jan,
>>>>>>
>>>>>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>>>>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>>>>>> Add clock nodes for zynqmp based on CCF.
>>>>>>>>
>>>>>>>> Signed-off-by: Rajan Vaja <[email protected]>
>>>>>>>> ---
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>>>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>>>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>> new file mode 100644
>>>>>>>> index 0000000..9868ca1
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>> @@ -0,0 +1,222 @@
>>>>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>>>>> +/*
>>>>>>>> + * Clock specification for Xilinx ZynqMP
>>>>>>>> + *
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> + *
>>>>>>>> + * Michal Simek <[email protected]>
>>>>>>>> + */
>>>>>>>> +
>>>>>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>>>>>> +/ {
>>>>>>>> + pss_ref_clk: pss_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <33333333>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + video_clk: video_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <27000000>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <0>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <108000000>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + aux_ref_clk: aux_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <27000000>;
>>>>>>>> + };
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&can0 {
>>>>>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&can1 {
>>>>>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&cpu0 {
>>>>>>>> + clocks = <&zynqmp_clk ACPU>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan1 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan2 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan3 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan4 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan5 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan6 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan7 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan8 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan1 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan2 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan3 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan4 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan5 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan6 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan7 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan8 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem0 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>>>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem1 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>>>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem2 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>>>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem3 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>>>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gpio {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&i2c0 {
>>>>>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&i2c1 {
>>>>>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&pcie {
>>>>>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sata {
>>>>>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sdhci0 {
>>>>>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sdhci1 {
>>>>>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&spi0 {
>>>>>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&spi1 {
>>>>>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc0 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc1 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc2 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc3 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&uart0 {
>>>>>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&uart1 {
>>>>>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&usb0 {
>>>>>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&usb1 {
>>>>>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&watchdog0 {
>>>>>>>> + clocks = <&zynqmp_clk WDT>;
>>>>>>>> +};
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> index 0f7b4cf..2e05fa4 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZC1232
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1232 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> index 9092828..3d0aaa0 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZC1254
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> * Siva Durga Prasad Paladugu <[email protected]>
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1254 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> index 4f404c5..1a8127d4 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1275 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> index 9a3e39d..fa7eb1b 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> index 2421ec7..4191dfa 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> index 7a49dee..3750690 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> index 54c7b4f..2366cd9 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> index b8b5ff1..9a894e6 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Siva Durga Prasad <[email protected]>
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> index e5699d0..3e39454 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> * Nathalie Chan King Choy
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> index 2a3b665..f6e9558 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> index 8f45614..f457f8a 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU104
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> index 93ce7eb..f15b99a 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU106
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> index 8bb0001..e27cd60 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU111
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> index 9aa6734..59a547b 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <[email protected]>
>>>>>>>> *
>>>>>>>> @@ -124,6 +124,28 @@
>>>>>>>> <1 10 0xf08>;
>>>>>>>> };
>>>>>>>>
>>>>>>>> + firmware {
>>>>>>>> + zynqmp_firmware: zynqmp-firmware {
>>>>>>>> + compatible = "xlnx,zynqmp-firmware";
>>>>>>>> + method = "smc";
>>>>>>>> + zynqmp_clk: clock-controller {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + #clock-cells = <1>;
>>>>>>>> + compatible = "xlnx,zynqmp-clk";
>>>>>>>> + clocks = <&pss_ref_clk>,
>>>>>>>> + <&video_clk>,
>>>>>>>> + <&pss_alt_ref_clk>,
>>>>>>>> + <&aux_ref_clk>,
>>>>>>>> + <>_crx_ref_clk>;
>>>>>>>> + clock-names = "pss_ref_clk",
>>>>>>>> + "video_clk",
>>>>>>>> + "pss_alt_ref_clk",
>>>>>>>> + "aux_ref_clk",
>>>>>>>> + "gt_crx_ref_clk";
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> amba_apu: amba-apu@0 {
>>>>>>>> compatible = "simple-bus";
>>>>>>>> #address-cells = <2>;
>>>>>>>>
>>>>>>>
>>>>>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>>>>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>>>>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>>>>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>>>>>
>>>>>>> Further versions of potential relevance:
>>>>>>> - PMUFW 2019.1 and 2020.2
>>>>>>> - TF-A 2.3
>>>>>>> - U-Boot 2020.10
>>>>>>>
>>>>>>> What's missing? I suspect someone forgot to document a subtle dependency
>>>>>>> of this change.
>>>>>>
>>>>>> Does this fix your issue?
>>>>>> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>>>>>>
>>>>>
>>>>> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
>>>>> missing even more. If you have some reference, I'm happy to try. I
>>>>> suspect that earlyprintk will also not reveal more without clocks (but I
>>>>> didn't play with that yet).
>>>>>
>>>>> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
>>>>> That helps for now.
>>>>>
>>>>
>>>> OK, dependencies resolved (unfortunately the hard way): It either
>>>> requires TF-A master or latest release v2.4 + [1] and [2].
>>>>
>>>> Those TF-A commits were upstream about a year after the firmware-based
>>>> clock control hit the kernel. A note would have been nice - or better
>>>> sychronization between both upstreaming efforts.
>>>
>>> I wasn't responsible for TFA but I found this last year in Nov timeframe
>>> that none really upstream this. Right now that development is working
>>> like that. I am asking everybody to contribute upstream to have all the
>>> time upstream heads to work together.
>>> I haven't had a time to dig into this but unfortunatelly there is no
>>> feature checking mechanism on zynqmp TFA side to check if this is there
>>> or not but we are trying our best to check as much as possible but bugs
>>> happen.
>>
>> OK, I understand. Reminding of "upstream first" is part of my daily
>> business as well. :)
>>
>> And integration is generally more and more complicated with the growing
>> number of firmware services and interfaces, not only on this SOC...
>>
>>> And we are lacking space in OCM to be able to add more features to TFA
>>> anyway.
>>
>> Yeah, I know - I'm also overflowing it via the SDEI patch [1].
>
>
> I have looked at this. How are you using it now? I haven't had a chance
> to take a look at it. How do you use it and test it?
>
> We should try to minimalize amount of code and try to fit to OCM.
>
Sure - but I think this is getting too much off-topic for this thread.
Should we move the SDEI discussion to the TF-A list?
Jan