This patch set includes various updates for mach-lpc32xx, including DT binding
for serial and dts updates. A new reference board is supported (EA3250). The
board support file phy3250.c is updated to become more general, useable for
other boards also. There is still board specific stuff in it, though (some
devicetree auxdata).
Further, clock updates, DMA support, MMC support and a defconfig update for
LPC32xx is included.
Signed-off-by: Roland Stigge <[email protected]>
--
Applies to v3.5-rc2
You can also pull from
git://git.antcom.de/linux-2.6.git lpc32xx-next
Roland Stigge (14):
ARM: LPC32xx: Add NAND flash timing to PHY3250 board dts
ARM: LPC32xx: Clock initialization for NAND controllers
ARM: LPC32xx: Remove SLC controller initialization from platform init
ARM: LPC32xx: Add DMA configuration to platform data
ARM: LPC32xx: Adjust dtsi file for MLC controller configuration
ARM: LPC32xx: Add dts for EA3250 reference board
ARM: LPC32xx: DTS adjustment for key matrix controller
ARM: LPC32xx: Clock adjustment for key matrix controller
ARM: LPC32xx: Defconfig update
ARM: LPC32xx: Add MMC controller support
ARM: LPC32xx: DTS adjustment for using pl18x primecell
ARM: LPC32xx: DT conversion of Standard UARTs
ARM: LPC32xx: High Speed UART configuration via DT
ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default
arch/arm/Kconfig | 2
arch/arm/boot/dts/ea3250.dts | 157 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/lpc32xx.dtsi | 60 ++++++++---
arch/arm/boot/dts/phy3250.dts | 40 +++++++
arch/arm/configs/lpc32xx_defconfig | 22 +++-
arch/arm/mach-lpc32xx/Kconfig | 32 ------
arch/arm/mach-lpc32xx/clock.c | 18 ++-
arch/arm/mach-lpc32xx/include/mach/gpio.h | 2
arch/arm/mach-lpc32xx/phy3250.c | 77 +++++++++++++-
arch/arm/mach-lpc32xx/serial.c | 85 ----------------
10 files changed, 343 insertions(+), 152 deletions(-)
The clock.c file needs to be changed to match the automatic device name to its
clock.
Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
arch/arm/mach-lpc32xx/clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -1131,7 +1131,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
- CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
+ CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
This patch adds support for the MMC controller of the LPC32xx SoC to the
platform initialization via the pl08x primecell driver. Lacking more complete
DT support, done via DT auxdata.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/mach-lpc32xx/phy3250.c | 43 ++++++++++++++++++++++++++++++++++++----
1 file changed, 39 insertions(+), 4 deletions(-)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/mmci.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
-#include <linux/amba/pl08x.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@@ -50,9 +51,12 @@
/*
* Mapped GPIOLIB GPIOs
*/
-#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
-#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
-#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
+#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
+#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
/*
* AMBA LCD controller
@@ -259,11 +263,32 @@ static struct pl08x_platform_data pl08x_
.mem_buses = PL08X_AHB1,
};
+static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
+{
+ /* Only on and off are supported */
+ if (ios->power_mode == MMC_POWER_OFF)
+ gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
+ else
+ gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
+ return 0;
+}
+
+static struct mmci_platform_data lpc32xx_mmci_data = {
+ .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
+ MMC_VDD_32_33 | MMC_VDD_33_34,
+ .ios_handler = mmc_handle_ios,
+ .dma_filter = NULL,
+ /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
+ * gather, and the MMCI driver doesn't do it this way */
+};
+
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
+ OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
+ &lpc32xx_mmci_data),
{ }
};
@@ -307,6 +332,11 @@ static void __init lpc3250_machine_init(
* detection or a data fault will occur, so enable the clocks
* here.
*/
+ tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+ tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+ LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
+ __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
__raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
LPC32XX_CLKPWR_LCDCLK_CTRL);
@@ -334,6 +364,11 @@ static void __init lpc3250_machine_init(
else if (gpio_direction_output(SPI0_CS_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
SPI0_CS_GPIO);
+
+ if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
+ pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
+ else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
+ pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
}
static char const *lpc32xx_dt_compat[] __initdata = {
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/boot/dts/lpc32xx.dtsi | 16 +++++++++++-----
arch/arm/boot/dts/phy3250.dts | 4 ++++
2 files changed, 15 insertions(+), 5 deletions(-)
--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -212,18 +212,24 @@
};
uart1: serial@40014000 {
- compatible = "nxp,serial";
+ compatible = "nxp,lpc3220-hsuart";
reg = <0x40014000 0x1000>;
+ interrupts = <26 0>;
+ status = "disable";
};
uart2: serial@40018000 {
- compatible = "nxp,serial";
+ compatible = "nxp,lpc3220-hsuart";
reg = <0x40018000 0x1000>;
+ interrupts = <25 0>;
+ status = "disable";
};
- uart7: serial@4001C000 {
- compatible = "nxp,serial";
- reg = <0x4001C000 0x1000>;
+ uart7: serial@4001c000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x4001c000 0x1000>;
+ interrupts = <24 0>;
+ status = "disable";
};
rtc@40024000 {
--- linux-2.6.orig/arch/arm/boot/dts/phy3250.dts
+++ linux-2.6/arch/arm/boot/dts/phy3250.dts
@@ -148,6 +148,10 @@
};
fab {
+ uart2: serial@40018000 {
+ status = "okay";
+ };
+
tsc@40048000 {
status = "okay";
};
This patch switches from static serial driver initialization to devicetree
configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
individually via DT.
E.g., instead of Kconfig configuration, the phy3250.dts activates
UARTs 3 and 5.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/Kconfig | 2
arch/arm/boot/dts/lpc32xx.dtsi | 34 ++++++++++++----
arch/arm/boot/dts/phy3250.dts | 8 +++
arch/arm/mach-lpc32xx/Kconfig | 32 ---------------
arch/arm/mach-lpc32xx/serial.c | 85 -----------------------------------------
5 files changed, 35 insertions(+), 126 deletions(-)
--- linux-2.6.orig/arch/arm/Kconfig
+++ linux-2.6/arch/arm/Kconfig
@@ -1019,8 +1019,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
-source "arch/arm/mach-lpc32xx/Kconfig"
-
source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -126,24 +126,42 @@
reg = <0x2009C000 0x1000>;
};
+ /* UART5 first since it is the default console, ttyS0 */
+ uart5: serial@40090000 {
+ /* actually, ns16550a w/ 64 byte fifos! */
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40090000 0x1000>;
+ interrupts = <9 0>;
+ clock-frequency = <13000000>;
+ reg-shift = <2>;
+ status = "disable";
+ };
+
uart3: serial@40080000 {
- compatible = "nxp,serial";
+ compatible = "nxp,lpc3220-uart";
reg = <0x40080000 0x1000>;
+ interrupts = <7 0>;
+ clock-frequency = <13000000>;
+ reg-shift = <2>;
+ status = "disable";
};
uart4: serial@40088000 {
- compatible = "nxp,serial";
+ compatible = "nxp,lpc3220-uart";
reg = <0x40088000 0x1000>;
- };
-
- uart5: serial@40090000 {
- compatible = "nxp,serial";
- reg = <0x40090000 0x1000>;
+ interrupts = <8 0>;
+ clock-frequency = <13000000>;
+ reg-shift = <2>;
+ status = "disable";
};
uart6: serial@40098000 {
- compatible = "nxp,serial";
+ compatible = "nxp,lpc3220-uart";
reg = <0x40098000 0x1000>;
+ interrupts = <10 0>;
+ clock-frequency = <13000000>;
+ reg-shift = <2>;
+ status = "disable";
};
i2c1: i2c@400A0000 {
--- linux-2.6.orig/arch/arm/boot/dts/phy3250.dts
+++ linux-2.6/arch/arm/boot/dts/phy3250.dts
@@ -94,6 +94,14 @@
};
apb {
+ uart5: serial@40090000 {
+ status = "okay";
+ };
+
+ uart3: serial@40080000 {
+ status = "okay";
+ };
+
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
--- linux-2.6.orig/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if ARCH_LPC32XX
-
-menu "Individual UART enable selections"
-
-config ARCH_LPC32XX_UART3_SELECT
- bool "Add support for standard UART3"
- help
- Adds support for standard UART 3 when the 8250 serial support
- is enabled.
-
-config ARCH_LPC32XX_UART4_SELECT
- bool "Add support for standard UART4"
- help
- Adds support for standard UART 4 when the 8250 serial support
- is enabled.
-
-config ARCH_LPC32XX_UART5_SELECT
- bool "Add support for standard UART5"
- default y
- help
- Adds support for standard UART 5 when the 8250 serial support
- is enabled.
-
-config ARCH_LPC32XX_UART6_SELECT
- bool "Add support for standard UART6"
- help
- Adds support for standard UART 6 when the 8250 serial support
- is enabled.
-
-endmenu
-
-endif
--- linux-2.6.orig/arch/arm/mach-lpc32xx/serial.c
+++ linux-2.6/arch/arm/mach-lpc32xx/serial.c
@@ -31,59 +31,6 @@
#define LPC32XX_SUART_FIFO_SIZE 64
-/* Standard 8250/16550 compatible serial ports */
-static struct plat_serial8250_port serial_std_platform_data[] = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
- {
- .membase = io_p2v(LPC32XX_UART5_BASE),
- .mapbase = LPC32XX_UART5_BASE,
- .irq = IRQ_LPC32XX_UART_IIR5,
- .uartclk = LPC32XX_MAIN_OSC_FREQ,
- .regshift = 2,
- .iotype = UPIO_MEM32,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
- UPF_SKIP_TEST,
- },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
- {
- .membase = io_p2v(LPC32XX_UART3_BASE),
- .mapbase = LPC32XX_UART3_BASE,
- .irq = IRQ_LPC32XX_UART_IIR3,
- .uartclk = LPC32XX_MAIN_OSC_FREQ,
- .regshift = 2,
- .iotype = UPIO_MEM32,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
- UPF_SKIP_TEST,
- },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
- {
- .membase = io_p2v(LPC32XX_UART4_BASE),
- .mapbase = LPC32XX_UART4_BASE,
- .irq = IRQ_LPC32XX_UART_IIR4,
- .uartclk = LPC32XX_MAIN_OSC_FREQ,
- .regshift = 2,
- .iotype = UPIO_MEM32,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
- UPF_SKIP_TEST,
- },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
- {
- .membase = io_p2v(LPC32XX_UART6_BASE),
- .mapbase = LPC32XX_UART6_BASE,
- .irq = IRQ_LPC32XX_UART_IIR6,
- .uartclk = LPC32XX_MAIN_OSC_FREQ,
- .regshift = 2,
- .iotype = UPIO_MEM32,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
- UPF_SKIP_TEST,
- },
-#endif
- { },
-};
-
struct uartinit {
char *uart_ck_name;
u32 ck_mode_mask;
@@ -92,7 +39,6 @@ struct uartinit {
};
static struct uartinit uartinit_data[] __initdata = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
{
.uart_ck_name = "uart5_ck",
.ck_mode_mask =
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] _
.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
.mapbase = LPC32XX_UART5_BASE,
},
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
{
.uart_ck_name = "uart3_ck",
.ck_mode_mask =
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] _
.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
.mapbase = LPC32XX_UART3_BASE,
},
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
{
.uart_ck_name = "uart4_ck",
.ck_mode_mask =
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] _
.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
.mapbase = LPC32XX_UART4_BASE,
},
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
{
.uart_ck_name = "uart6_ck",
.ck_mode_mask =
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] _
.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
.mapbase = LPC32XX_UART6_BASE,
},
-#endif
-};
-
-static struct platform_device serial_std_platform_device = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = serial_std_platform_data,
- },
-};
-
-static struct platform_device *lpc32xx_serial_devs[] __initdata = {
- &serial_std_platform_device,
};
void __init lpc32xx_serial_init(void)
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
if (!IS_ERR(clk)) {
clk_enable(clk);
- serial_std_platform_data[i].uartclk =
- clk_get_rate(clk);
}
- /* Fall back on main osc rate if clock rate return fails */
- if (serial_std_platform_data[i].uartclk == 0)
- serial_std_platform_data[i].uartclk =
- LPC32XX_MAIN_OSC_FREQ;
-
/* Setup UART clock modes for all UARTs, disable autoclock */
clkmodes |= uartinit_data[i].ck_mode_mask;
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
/* Force a flush of the RX FIFOs to work around a HW bug */
- puart = serial_std_platform_data[i].mapbase;
+ puart = uartinit_data[i].mapbase;
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
j = LPC32XX_SUART_FIFO_SIZE;
@@ -202,7 +122,4 @@ void __init lpc32xx_serial_init(void)
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
- platform_add_devices(lpc32xx_serial_devs,
- ARRAY_SIZE(lpc32xx_serial_devs));
}
ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs.
Now if additional GPIOs need to be added dynamically, e.g. via DT, none are
available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the
default of 256 (currently in include/asm-generic/gpio.h).
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/mach-lpc32xx/include/mach/gpio.h | 2 --
1 file changed, 2 deletions(-)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -3,6 +3,4 @@
#include "gpio-lpc32xx.h"
-#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
-
#endif /* __MACH_GPIO_H */
This patch adjusts the dts files to reference the pl18x primecell driver
correctly.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/boot/dts/lpc32xx.dtsi | 3 ++-
arch/arm/boot/dts/phy3250.dts | 8 ++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -115,9 +115,10 @@
};
sd@20098000 {
- compatible = "arm,pl180", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
reg = <0x20098000 0x1000>;
interrupts = <0x0f 0>, <0x0d 0>;
+ status = "disable";
};
i2s1: i2s@2009C000 {
--- linux-2.6.orig/arch/arm/boot/dts/phy3250.dts
+++ linux-2.6/arch/arm/boot/dts/phy3250.dts
@@ -129,6 +129,14 @@
compatible = "atmel,at25";
};
};
+
+ sd@20098000 {
+ wp-gpios = <&gpio 3 0 0>;
+ cd-gpios = <&gpio 3 1 0>;
+ cd-inverted;
+ bus-width = <4>;
+ status = "okay";
+ };
};
fab {
This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5
and drivers typically used in systems with the LPC32xx chip.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/configs/lpc32xx_defconfig | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
--- linux-2.6.orig/arch/arm/configs/lpc32xx_defconfig
+++ linux-2.6/arch/arm/configs/lpc32xx_defconfig
@@ -1,5 +1,7 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
@@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_LPC32XX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -54,11 +54,14 @@ CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_MTD_NAND_SLC_LPC32XX=y
+CONFIG_MTD_NAND_MLC_LPC32XX=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
@@ -79,16 +82,22 @@ CONFIG_LPC_ENET=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
+CONFIG_INPUT_MATRIXKMAP=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_LPC32XX=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_LPC32XX=y
+CONFIG_SERIO_LIBPS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_HS_LPC32XX=y
+CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -96,7 +105,8 @@ CONFIG_I2C_PNX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_DS620=y
+CONFIG_SENSORS_MAX6639=y
CONFIG_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
CONFIG_FB=y
@@ -133,6 +143,8 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_PCA9532=y
+CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
@@ -148,8 +160,9 @@ CONFIG_RTC_DRV_LPC32XX=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_STAGING=y
-CONFIG_IIO=y
CONFIG_LPC32XX_ADC=y
+CONFIG_MAX517=y
+CONFIG_IIO=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
@@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
There is another reference/development board for the LPC32xx SoC (besides the
Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts
file for it.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/boot/dts/ea3250.dts | 157 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 157 insertions(+)
--- /dev/null
+++ linux-2.6/arch/arm/boot/dts/ea3250.dts
@@ -0,0 +1,157 @@
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+
+/ {
+ model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+ compatible = "ea,ea3250", "nxp,lpc3250";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x4000000>;
+ };
+
+ ahb {
+ mac: ethernet@31060000 {
+ phy-mode = "rmii";
+ use-iram;
+ };
+
+ /* Here, choose exactly one from: ohci, usbd */
+ ohci@31020000 {
+ transceiver = <&isp1301>;
+ status = "okay";
+ };
+
+/*
+ usbd@31020000 {
+ transceiver = <&isp1301>;
+ status = "okay";
+ };
+*/
+
+ /* 128MB Flash via SLC NAND controller */
+ slc: flash@20020000 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nxp,wdr-clks = <14>;
+ nxp,wwidth = <260000000>;
+ nxp,whold = <104000000>;
+ nxp,wsetup = <200000000>;
+ nxp,rdr-clks = <14>;
+ nxp,rwidth = <34666666>;
+ nxp,rhold = <104000000>;
+ nxp,rsetup = <200000000>;
+ nand-on-flash-bbt;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+ mtd0@00000000 {
+ label = "ea3250-boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ mtd1@00080000 {
+ label = "ea3250-uboot";
+ reg = <0x00080000 0x000c0000>;
+ read-only;
+ };
+
+ mtd2@00140000 {
+ label = "ea3250-kernel";
+ reg = <0x00140000 0x00400000>;
+ };
+
+ mtd3@00540000 {
+ label = "ea3250-rootfs";
+ reg = <0x00540000 0x07ac0000>;
+ };
+ };
+
+ apb {
+ uart5: serial@40090000 {
+ status = "okay";
+ };
+
+ uart3: serial@40080000 {
+ status = "okay";
+ };
+
+ uart6: serial@40098000 {
+ status = "okay";
+ };
+
+ i2c1: i2c@400A0000 {
+ clock-frequency = <100000>;
+
+ eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+ };
+
+ eeprom@57 {
+ compatible = "at,24c64";
+ reg = <0x57>;
+ };
+
+ uda1380: uda1380@18 {
+ compatible = "nxp,uda1380";
+ reg = <0x18>;
+ power-gpio = <&gpio 0x59 0>;
+ reset-gpio = <&gpio 0x51 0>;
+ dac-clk = "wspll";
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x60>;
+ };
+ };
+
+ i2c2: i2c@400A8000 {
+ clock-frequency = <100000>;
+ };
+
+ i2cusb: i2c@31020300 {
+ clock-frequency = <100000>;
+
+ isp1301: usb-transceiver@2c {
+ compatible = "nxp,isp1301";
+ reg = <0x2c>;
+ };
+ };
+
+ sd@20098000 {
+ wp-gpios = <&pca9532 5 0>;
+ cd-gpios = <&pca9532 4 0>;
+ cd-inverted;
+ bus-width = <4>;
+ status = "okay";
+ };
+ };
+
+ fab {
+ uart1: serial@40014000 {
+ status = "okay";
+ };
+ };
+ };
+};
This patch takes into account that the MTD NAND MLC controller needs more
registers, located actually before the previously allocated memory range,
already starting at 200a8000 instead of 200b0000.
Further, the interrupt for the controller is configured.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/boot/dts/lpc32xx.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -38,9 +38,10 @@
status = "disable";
};
- mlc: flash@200B0000 {
+ mlc: flash@200a8000 {
compatible = "nxp,lpc3220-mlc";
- reg = <0x200B0000 0x1000>;
+ reg = <0x200a8000 0x11000>;
+ interrupts = <11 0>;
status = "disable";
};
This patch connects the lpc32xx-key driver to the LPC32xx platform (via
lpc32xx.dtsi), and more specifically to the reference board via its dts file.
Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
arch/arm/boot/dts/lpc32xx.dtsi | 2 ++
arch/arm/boot/dts/phy3250.dts | 9 +++++++++
2 files changed, 11 insertions(+)
--- linux-2.6.orig/arch/arm/boot/dts/lpc32xx.dtsi
+++ linux-2.6/arch/arm/boot/dts/lpc32xx.dtsi
@@ -249,6 +249,8 @@
key@40050000 {
compatible = "nxp,lpc3220-key";
reg = <0x40050000 0x1000>;
+ interrupts = <54 0>;
+ status = "disable";
};
};
--- linux-2.6.orig/arch/arm/boot/dts/phy3250.dts
+++ linux-2.6/arch/arm/boot/dts/phy3250.dts
@@ -135,6 +135,15 @@
tsc@40048000 {
status = "okay";
};
+
+ key@40050000 {
+ status = "okay";
+ keypad,num-rows = <1>;
+ keypad,num-columns = <1>;
+ nxp,debounce-delay-ms = <3>;
+ nxp,scan-delay-ms = <34>;
+ linux,keymap = <0x00000002>;
+ };
};
};
This patch adds DMA channel configuration to the LPC32xx platform file. The
configured DMA signalling is generic for LPC32xx SoC and is not board specific.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/mach-lpc32xx/phy3250.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -226,7 +226,37 @@ static int __init phy3250_spi_board_regi
}
arch_initcall(phy3250_spi_board_register);
+static struct pl08x_channel_data pl08x_slave_channels[] = {
+ {
+ .bus_id = "nand-slc",
+ .min_signal = 1, /* SLC NAND Flash */
+ .max_signal = 1,
+ .periph_buses = PL08X_AHB1,
+ },
+ {
+ .bus_id = "nand-mlc",
+ .min_signal = 12, /* MLC NAND Flash */
+ .max_signal = 12,
+ .periph_buses = PL08X_AHB1,
+ },
+};
+
+static int pl08x_get_signal(struct pl08x_dma_chan *ch)
+{
+ return ch->cd->min_signal;
+}
+
+static void pl08x_put_signal(struct pl08x_dma_chan *ch)
+{
+}
+
static struct pl08x_platform_data pl08x_pd = {
+ .slave_channels = &pl08x_slave_channels[0],
+ .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
+ .get_signal = &pl08x_get_signal,
+ .put_signal = &pl08x_put_signal,
+ .lli_buses = PL08X_AHB1,
+ .mem_buses = PL08X_AHB1,
};
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
This patch adds clock initialization for the MLC NAND controller of the LPC32xx
SoC and adjusts it for the SLC controller.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/mach-lpc32xx/clock.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -691,10 +691,21 @@ static struct clk clk_nand = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
- .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+ .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
+ LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
.get_rate = local_return_parent_rate,
};
+static struct clk clk_nand_mlc = {
+ .parent = &clk_hclk,
+ .enable = local_onoff_enable,
+ .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+ .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
+ LPC32XX_CLKPWR_NANDCLK_DMA_INT |
+ LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
+ .get_rate = local_return_parent_rate,
+};
+
static struct clk clk_i2s0 = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
@@ -1121,7 +1132,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
- CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
+ CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
+ CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
This patch adds necessary NAND flash timings to the board specific dts file of
the PHY3250 reference board of the LPC32xx SoC.
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/boot/dts/phy3250.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
--- linux-2.6.orig/arch/arm/boot/dts/phy3250.dts
+++ linux-2.6/arch/arm/boot/dts/phy3250.dts
@@ -54,6 +54,17 @@
#address-cells = <1>;
#size-cells = <1>;
+ nxp,wdr-clks = <14>;
+ nxp,wwidth = <40000000>;
+ nxp,whold = <100000000>;
+ nxp,wsetup = <100000000>;
+ nxp,rdr-clks = <14>;
+ nxp,rwidth = <40000000>;
+ nxp,rhold = <66666666>;
+ nxp,rsetup = <100000000>;
+ nand-on-flash-bbt;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT,
we don't initialize the SLC controller statically anymore, but do it via the
clock setup (see previous patch).
Signed-off-by: Roland Stigge <[email protected]>
---
arch/arm/mach-lpc32xx/phy3250.c | 4 ----
1 file changed, 4 deletions(-)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -241,10 +241,6 @@ static void __init lpc3250_machine_init(
{
u32 tmp;
- /* Setup SLC NAND controller muxing */
- __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
- LPC32XX_CLKPWR_NAND_CLK_CTRL);
-
/* Setup LCD muxing to RGB565 */
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
On Mon, Jun 11, 2012 at 01:02:07PM +0200, Roland Stigge wrote:
> +static int pl08x_get_signal(struct pl08x_dma_chan *ch)
> +{
> + return ch->cd->min_signal;
> +}
> +
> +static void pl08x_put_signal(struct pl08x_dma_chan *ch)
> +{
> +}
These change in my unstable/dma-pl08x branch, patches have been posted
already, but I don't deem them to be totally stable yet. Waiting on
OMAP people to get their mainline kernel restored to a buildable state
so I can continue my DMA engine work.
> +
> static struct pl08x_platform_data pl08x_pd = {
> + .slave_channels = &pl08x_slave_channels[0],
> + .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
> + .get_signal = &pl08x_get_signal,
> + .put_signal = &pl08x_put_signal,
No need to take the address of a function here.
On Monday 11 June 2012, Roland Stigge wrote:
> sd@20098000 {
> - compatible = "arm,pl180", "arm,primecell";
> + compatible = "arm,pl18x", "arm,primecell";
> reg = <0x20098000 0x1000>;
> interrupts = <0x0f 0>, <0x0d 0>;
> + status = "disable";
> };
>
The proper way to write this is 'status = "disabled";', with a 'd' at
the end.
Arnd
On Monday 11 June 2012, Roland Stigge wrote:
> The clock.c file needs to be changed to match the automatic device name to its
> clock.
>
> Signed-off-by: Roland Stigge <[email protected]>
> Acked-by: Rob Herring <[email protected]>
>
Should this not be in the same patch as the one that moves the device over
to DT probing? Otherwise you have a non-working setup if only one patch
is applied.
Arnd
On 06/11/2012 04:14 PM, Arnd Bergmann wrote:
> On Monday 11 June 2012, Roland Stigge wrote:
>> sd@20098000 {
>> - compatible = "arm,pl180", "arm,primecell";
>> + compatible = "arm,pl18x", "arm,primecell";
>> reg = <0x20098000 0x1000>;
>> interrupts = <0x0f 0>, <0x0d 0>;
>> + status = "disable";
>> };
>>
>
> The proper way to write this is 'status = "disabled";', with a 'd' at
> the end.
Thanks for the note!
Funnily, I always did it this way. Looks like initially, I copied from
somewhere else (wrongly). Indeed, we have lots of "disable", see also:
omap3-beagle.dts
omap4-panda.dts
omap4-sdp.dts
tegra20.dtsi
tegra30.dtsi
Roland
Hi,
On 06/11/2012 04:16 PM, Arnd Bergmann wrote:
> On Monday 11 June 2012, Roland Stigge wrote:
>> The clock.c file needs to be changed to match the automatic device name to its
>> clock.
>>
>> Signed-off-by: Roland Stigge <[email protected]>
>> Acked-by: Rob Herring <[email protected]>
>>
>
> Should this not be in the same patch as the one that moves the device over
> to DT probing? Otherwise you have a non-working setup if only one patch
> is applied.
The actual driver is new for v3.6 (hopefully), DT-only.
Rather than merging the patches, I'd let the key driver go in via input,
and the clock.c adjustment via arm-soc.
Roland
On Monday 11 June 2012, Roland Stigge wrote:
> Thanks for the note!
>
> Funnily, I always did it this way. Looks like initially, I copied from
> somewhere else (wrongly). Indeed, we have lots of "disable", see also:
>
> omap3-beagle.dts
> omap4-panda.dts
> omap4-sdp.dts
> tegra20.dtsi
> tegra30.dtsi
Ah, right. Note that the kernel checks only for "ok" and "okay" strings,
anything else is interpreted as "disabled". We should use the correct
string anyway of course.
Arnd
On Monday 11 June 2012, Roland Stigge wrote:
> On 06/11/2012 04:16 PM, Arnd Bergmann wrote:
> > On Monday 11 June 2012, Roland Stigge wrote:
> >> The clock.c file needs to be changed to match the automatic device name to its
> >> clock.
> >>
> >> Signed-off-by: Roland Stigge <[email protected]>
> >> Acked-by: Rob Herring <[email protected]>
> >>
> >
> > Should this not be in the same patch as the one that moves the device over
> > to DT probing? Otherwise you have a non-working setup if only one patch
> > is applied.
>
> The actual driver is new for v3.6 (hopefully), DT-only.
>
> Rather than merging the patches, I'd let the key driver go in via input,
> and the clock.c adjustment via arm-soc.
Ok, makes sense.
Arnd
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch adds necessary NAND flash timings to the board specific dts file of
> the PHY3250 reference board of the LPC32xx SoC.
>
> Signed-off-by: Roland Stigge <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT,
> we don't initialize the SLC controller statically anymore, but do it via the
> clock setup (see previous patch).
>
> Signed-off-by: Roland Stigge <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch takes into account that the MTD NAND MLC controller needs more
> registers, located actually before the previously allocated memory range,
> already starting at 200a8000 instead of 200b0000.
>
> Further, the interrupt for the controller is configured.
>
> Signed-off-by: Roland Stigge <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> There is another reference/development board for the LPC32xx SoC (besides the
> Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts
> file for it.
>
> Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch connects the lpc32xx-key driver to the LPC32xx platform (via
> lpc32xx.dtsi), and more specifically to the reference board via its dts file.
>
> Signed-off-by: Roland Stigge <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5
> and drivers typically used in systems with the LPC32xx chip.
>
> Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch adds support for the MMC controller of the LPC32xx SoC to the
> platform initialization via the pl08x primecell driver. Lacking more complete
> DT support, done via DT auxdata.
>
> Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch switches from static serial driver initialization to devicetree
> configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
> individually via DT.
>
> E.g., instead of Kconfig configuration, the phy3250.dts activates
> UARTs 3 and 5.
>
> Signed-off-by: Roland Stigge <[email protected]>
Tested-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs.
> Now if additional GPIOs need to be added dynamically, e.g. via DT, none are
> available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the
> default of 256 (currently in include/asm-generic/gpio.h).
>
> Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
On Mon, Jun 11, 2012 at 8:02 AM, Roland Stigge <[email protected]> wrote:
> This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
> LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
> configuration. On the PHY3250 reference board, UART2 is enabled.
>
> Signed-off-by: Roland Stigge <[email protected]>
Acked-by: Alexandre Pereira da Silva <[email protected]>
Hi Russell,
thanks for your note!
On 11/06/12 13:10, Russell King - ARM Linux wrote:
> On Mon, Jun 11, 2012 at 01:02:07PM +0200, Roland Stigge wrote:
>> +static int pl08x_get_signal(struct pl08x_dma_chan *ch)
>> +{
>> + return ch->cd->min_signal;
>> +}
>> +
>> +static void pl08x_put_signal(struct pl08x_dma_chan *ch)
>> +{
>> +}
>
> These change in my unstable/dma-pl08x branch, patches have been posted
> already, but I don't deem them to be totally stable yet. Waiting on
> OMAP people to get their mainline kernel restored to a buildable state
> so I can continue my DMA engine work.
We have a few options here:
1) Take the patch as I posted it (needs adjustments as soon as the API
changed and becomes stable)
2) Remove the DMA related patches from the LPC32xx series for now (which
would be unfortunate)
3) Let me build upon some tree that already looks worthwhile to play
with already (which one?)
What would you suggest?
Thanks in advance,
Roland