Hello,
Sorry for the noise, the first submission has been filtered.
This patch series is a proposal to move at91 clock implementation
to common clk framework.
Most of the clock provided by the PMC (Power Management Controller) are
implemented :
- main clock (main oscillator)
- pll clocks
- master clock
- programmable clocks
- utmi clock
- peripheral clocks
- system clocks
This implementation is compatible with device tree: the goal is
to define the whole clock tree in the device tree (all currently
available dt SoCs and boards are patched to support dt clocks).
Please feel free to comment the dt bindinds (I'm not sure about the
name I choose or the position of clock nodes: children of pmc node).
I removed the register_clocks function in SoC supporting dt boards only:
- at91sam9x5 SoCs
- at91sam9n12 SoC
- sama5d3 SoCs
This patch series also update at91 drivers calling clk_enable/disable
instead of the preferred clk_prepare_enable/disable_unprepare functions.
I know there are a lot of cleanup in progress for at91 arch, so please tell
me if you think this transition to common clk framework should wait.
This patch series has been tested on Kizbox (sam9g20 SoC) board using device
tree. It compiles for other SoCs and both with and without dt support, but it
has not been tested.
The clocks rate/parent change has not been tested.
Best Regards,
Boris
Boris BREZILLON (50):
ARM: at91: move at91_pmc.h to include/linux/clk/at91.h
ARM: at91: add PMC main clock
ARM: at91: add PMC pll clocks
ARM: at91: add PMC master clock
ARM: at91: add PMC system clocks
ARM: at91: add PMC peripheral clocks
ARM: at91: add PMC programmable clocks
ARM: at91: add PMC utmi clock support
ARM: at91: add PMC usb clock support
ARM: at91: add PMC smd clock support
ARM: at91: add PMC clk device tree binding doc
ARM: at91: move to common clk framework
ARM: at91: move at91rm9200 SoC to new at91 clk implem
ARM: at91: move at91sam9260 SoC to new at91 clk implem
ARM: at91: move at91sam9263 SoC to new at91 clk implem
ARM: at91: move at91sam9263 SoC to new at91 clk implem
ARM: at91: move at91sam9g45 SoC to new at91 clk implem
ARM: at91: move at91sam9n12 SoC to new at91 clk implem
ARM: at91: move at91sam9rl SoC to new at91 clk implem
ARM: at91: move at91sam9x5 SoCs to new at91 clk implem
ARM: at91: move at91sam9 SoCs to new at91 clk implem
ARM: at91: move sama5d3 SoCs to new at91 clk implem
ARM: at91: move at91rm9200 boards to new at91 clk implem
ARM: at91: move at91sam9 boards to new at91 clk implem
ARM: at91: move pit timer to common clk framework
ARM: at91/tc/clocksource: prepare clk before calling enable
at_hdmac: prepare clk before calling enable
ASoC: atmel-ssc: prepare clk before calling enable
mmc: atmel-mci: prepare clk before calling enable
pwm: atmel-tcb: prepare clk before calling enable
tty: atmel_serial: prepare clk before calling enable
usb: gadget: at91_udc: prepare clk before calling enable
ehci-atmel.c: prepare clk before calling enable
USB: ohci-at91: prepare clk before calling enable
at91/avr32/atmel_lcdfb: prepare clk before calling enable
ARM: at91/dt: move at91rm9200 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9260 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9263 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9g45 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9n12 SoC to new at91 clk implem
ARM: at91/dt: move at91sam9x5 SoCs to new at91 clk implem
ARM: at91/dt: move at91sam9g20 SoC to new at91 clk implem
ARM: at91/dt: move sama5d3 SoCs to to new at91 clk implem
ARM: at91/dt: move sam9260/sam9g20 boards to new at91 clk implem
ARM: at91/dt: move rm9200 boards to new at91 clk implem
ARM: at91/dt: move sam9263 boards to new at91 clk implem
ARM: at91/dt: move sam9g45 boards to new at91 clk implem
ARM: at91/dt: move sam9n12 boards to new at91 clk implem
ARM: at91/dt: move sam9x5 boards to new at91 clk implem
ARM: at91/dt: move sama5d3 boards to new at91 clk implem
.../devicetree/bindings/clock/at91-clock.txt | 247 +++++
arch/arm/boot/dts/animeo_ip.dts | 17 +-
arch/arm/boot/dts/at91-ariag25.dts | 17 +-
arch/arm/boot/dts/at91rm9200.dtsi | 133 +++
arch/arm/boot/dts/at91rm9200ek.dts | 17 +-
arch/arm/boot/dts/at91sam9260.dtsi | 144 ++-
arch/arm/boot/dts/at91sam9263.dtsi | 135 +++
arch/arm/boot/dts/at91sam9263ek.dts | 17 +-
arch/arm/boot/dts/at91sam9g15.dtsi | 11 +
arch/arm/boot/dts/at91sam9g20.dtsi | 37 +
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 +-
arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
arch/arm/boot/dts/at91sam9g35.dtsi | 23 +
arch/arm/boot/dts/at91sam9g45.dtsi | 157 ++++
arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 153 ++++
arch/arm/boot/dts/at91sam9n12ek.dts | 17 +-
arch/arm/boot/dts/at91sam9x25.dtsi | 25 +-
arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
arch/arm/boot/dts/at91sam9x5.dtsi | 226 +++--
arch/arm/boot/dts/at91sam9x5_can.dtsi | 24 +
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 24 +
arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 32 +
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 68 ++
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 56 ++
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 60 ++
arch/arm/boot/dts/ge863-pro3.dtsi | 16 +-
arch/arm/boot/dts/kizbox.dts | 5 +
arch/arm/boot/dts/mpa1600.dts | 16 +-
arch/arm/boot/dts/pm9g45.dts | 16 +-
arch/arm/boot/dts/sama5d3.dtsi | 358 ++++----
arch/arm/boot/dts/sama5d31ek.dts | 4 +
arch/arm/boot/dts/sama5d33ek.dts | 2 +
arch/arm/boot/dts/sama5d34ek.dts | 4 +
arch/arm/boot/dts/sama5d35ek.dts | 6 +
arch/arm/boot/dts/sama5d3_can.dtsi | 67 ++
arch/arm/boot/dts/sama5d3_emac.dtsi | 56 ++
arch/arm/boot/dts/sama5d3_gmac.dtsi | 89 ++
arch/arm/boot/dts/sama5d3_lcd.dtsi | 73 ++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 59 ++
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 39 +
arch/arm/boot/dts/sama5d3_uart.dtsi | 42 +
arch/arm/boot/dts/sama5d3xcm.dtsi | 17 +-
arch/arm/boot/dts/tny_a9260_common.dtsi | 17 +-
arch/arm/boot/dts/tny_a9263.dts | 17 +-
arch/arm/boot/dts/usb_a9260_common.dtsi | 17 +-
arch/arm/boot/dts/usb_a9263.dts | 17 +-
arch/arm/mach-at91/Kconfig | 26 +
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/at91rm9200.c | 578 +++++++-----
arch/arm/mach-at91/at91sam9260.c | 694 +++++++++-----
arch/arm/mach-at91/at91sam9261.c | 581 ++++++++----
arch/arm/mach-at91/at91sam9263.c | 599 +++++++-----
arch/arm/mach-at91/at91sam926x_time.c | 21 +-
arch/arm/mach-at91/at91sam9g45.c | 705 ++++++++------
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
arch/arm/mach-at91/at91sam9n12.c | 196 +---
arch/arm/mach-at91/at91sam9rl.c | 514 +++++++----
arch/arm/mach-at91/at91sam9x5.c | 291 +-----
arch/arm/mach-at91/board-1arm.c | 12 +-
arch/arm/mach-at91/board-afeb-9260v1.c | 11 +-
arch/arm/mach-at91/board-cam60.c | 13 +-
arch/arm/mach-at91/board-carmeva.c | 13 +-
arch/arm/mach-at91/board-cpu9krea.c | 12 +-
arch/arm/mach-at91/board-cpuat91.c | 12 +-
arch/arm/mach-at91/board-csb337.c | 11 +-
arch/arm/mach-at91/board-csb637.c | 11 +-
arch/arm/mach-at91/board-dt-rm9200.c | 9 +-
arch/arm/mach-at91/board-dt-sam9.c | 9 +-
arch/arm/mach-at91/board-dt-sama5.c | 9 +-
arch/arm/mach-at91/board-eb9200.c | 11 +-
arch/arm/mach-at91/board-ecbat91.c | 12 +-
arch/arm/mach-at91/board-eco920.c | 13 +-
arch/arm/mach-at91/board-flexibity.c | 12 +-
arch/arm/mach-at91/board-foxg20.c | 12 +-
arch/arm/mach-at91/board-gsia18s.c | 8 +-
arch/arm/mach-at91/board-kafa.c | 12 +-
arch/arm/mach-at91/board-kb9202.c | 12 +-
arch/arm/mach-at91/board-pcontrol-g20.c | 9 +-
arch/arm/mach-at91/board-picotux200.c | 11 +-
arch/arm/mach-at91/board-qil-a9260.c | 11 +-
arch/arm/mach-at91/board-rm9200dk.c | 11 +-
arch/arm/mach-at91/board-rm9200ek.c | 11 +-
arch/arm/mach-at91/board-rsi-ews.c | 12 +-
arch/arm/mach-at91/board-sam9-l9260.c | 11 +-
arch/arm/mach-at91/board-sam9260ek.c | 11 +-
arch/arm/mach-at91/board-sam9261ek.c | 15 +-
arch/arm/mach-at91/board-sam9263ek.c | 11 +-
arch/arm/mach-at91/board-sam9g20ek.c | 15 +-
arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +-
arch/arm/mach-at91/board-sam9rlek.c | 11 +-
arch/arm/mach-at91/board-snapper9260.c | 12 +-
arch/arm/mach-at91/board-stamp9g20.c | 15 +-
arch/arm/mach-at91/board-yl-9200.c | 12 +-
arch/arm/mach-at91/clock.c | 961 --------------------
arch/arm/mach-at91/clock.h | 49 -
arch/arm/mach-at91/generic.h | 10 +-
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/pmc.c | 58 ++
arch/arm/mach-at91/sama5d3.c | 344 +------
arch/arm/mach-at91/setup.c | 38 +-
arch/arm/mach-at91/stamp9g20.h | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/at91/Makefile | 11 +
drivers/clk/at91/clk-main.c | 106 +++
drivers/clk/at91/clk-master.c | 317 +++++++
drivers/clk/at91/clk-peripheral.c | 376 ++++++++
drivers/clk/at91/clk-pll.c | 438 +++++++++
drivers/clk/at91/clk-plldiv.c | 125 +++
drivers/clk/at91/clk-programmable.c | 370 ++++++++
drivers/clk/at91/clk-smd.c | 157 ++++
drivers/clk/at91/clk-system.c | 189 ++++
drivers/clk/at91/clk-usb.c | 303 ++++++
drivers/clk/at91/clk-utmi.c | 114 +++
drivers/clocksource/tcb_clksrc.c | 10 +-
drivers/dma/at_hdmac.c | 12 +-
drivers/misc/atmel-ssc.c | 8 +-
drivers/mmc/host/atmel-mci.c | 16 +-
drivers/pwm/pwm-atmel-tcb.c | 4 +-
drivers/tty/serial/atmel_serial.c | 35 +-
drivers/usb/gadget/at91_udc.c | 12 +-
drivers/usb/gadget/atmel_usba_udc.c | 2 +-
drivers/usb/host/ehci-atmel.c | 8 +-
drivers/usb/host/ohci-at91.c | 12 +-
drivers/video/atmel_lcdfb.c | 8 +-
.../mach/at91_pmc.h => include/linux/clk/at91.h | 122 ++-
127 files changed, 7588 insertions(+), 3862 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
create mode 100644 arch/arm/boot/dts/at91sam9x5_can.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_isi.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb0.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_macb1.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9x5_usart3.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_can.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_emac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_gmac.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_lcd.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_mci2.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_tcb1.dtsi
create mode 100644 arch/arm/boot/dts/sama5d3_uart.dtsi
delete mode 100644 arch/arm/mach-at91/clock.c
delete mode 100644 arch/arm/mach-at91/clock.h
create mode 100644 arch/arm/mach-at91/pmc.c
create mode 100644 drivers/clk/at91/Makefile
create mode 100644 drivers/clk/at91/clk-main.c
create mode 100644 drivers/clk/at91/clk-master.c
create mode 100644 drivers/clk/at91/clk-peripheral.c
create mode 100644 drivers/clk/at91/clk-pll.c
create mode 100644 drivers/clk/at91/clk-plldiv.c
create mode 100644 drivers/clk/at91/clk-programmable.c
create mode 100644 drivers/clk/at91/clk-smd.c
create mode 100644 drivers/clk/at91/clk-system.c
create mode 100644 drivers/clk/at91/clk-usb.c
create mode 100644 drivers/clk/at91/clk-utmi.c
rename arch/arm/mach-at91/include/mach/at91_pmc.h => include/linux/clk/at91.h (76%)
--
1.7.9.5
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91rm9200.c | 2 +-
arch/arm/mach-at91/at91sam9260.c | 2 +-
arch/arm/mach-at91/at91sam9261.c | 2 +-
arch/arm/mach-at91/at91sam9263.c | 2 +-
arch/arm/mach-at91/at91sam9g45.c | 2 +-
arch/arm/mach-at91/at91sam9n12.c | 2 +-
arch/arm/mach-at91/at91sam9rl.c | 2 +-
arch/arm/mach-at91/at91sam9x5.c | 2 +-
arch/arm/mach-at91/clock.c | 2 +-
arch/arm/mach-at91/pm.c | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 2 +-
arch/arm/mach-at91/sama5d3.c | 2 +-
arch/arm/mach-at91/setup.c | 2 +-
drivers/usb/gadget/atmel_usba_udc.c | 2 +-
.../mach/at91_pmc.h => include/linux/clk/at91.h | 2 +-
15 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a40..6ea6de7 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,13 +11,13 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91rm9200.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_st.h>
#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce245..df32768 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -20,7 +21,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5a..8a63b81 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91sam9261.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2..77b3c24 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -18,7 +19,6 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9263.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce0..31a1304 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 13cdbcd..f9ff4d2 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9n12.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5..6fbda1a 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
*/
#include <linux/module.h>
+#include <linux/clk/at91.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
@@ -19,7 +20,6 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
-#include <mach/at91_pmc.h>
#include "at91_aic.h"
#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec..83fc6b3 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index da84188..191e9e4 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_address.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include <asm/proc-fns.h>
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db30..d29702f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28d..76387e0 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
*/
#include <linux/linkage.h>
+#include <linux/clk/at91.h>
#include <mach/hardware.h>
-#include <mach/at91_pmc.h>
#include <mach/at91_ramc.h>
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 4012797..32e0522 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,12 +9,12 @@
#include <linux/module.h>
#include <linux/dma-mapping.h>
+#include <linux/clk/at91.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d3.h>
-#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "soc.h"
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index e2f4bdd..7af1bbf 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
#include <linux/pm.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
+#include <linux/clk/at91.h>
#include <asm/system_misc.h>
#include <asm/mach/map.h>
@@ -18,7 +19,6 @@
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
#include "at91_shdwc.h"
#include "soc.h"
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f2a970f..846a363 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -328,7 +328,7 @@ static int vbus_is_present(struct usba_udc *udc)
#if defined(CONFIG_ARCH_AT91SAM9RL)
-#include <mach/at91_pmc.h>
+#include <linux/clk/at91.h>
static void toggle_bias(int is_on)
{
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91.h
similarity index 99%
rename from arch/arm/mach-at91/include/mach/at91_pmc.h
rename to include/linux/clk/at91.h
index 31df120..58b1eba 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/include/linux/clk/at91.h
@@ -1,5 +1,5 @@
/*
- * arch/arm/mach-at91/include/mach/at91_pmc.h
+ * include/linux/clk/at91.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
--
1.7.9.5
This is the at91 main oscillator clock implementation using common
clk framework.
If rate is not provided during clock registraction it is computed using
the slow clock (main clk parent in this case) rate and the MCFR register.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 5 ++
drivers/clk/at91/clk-main.c | 106 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 10 ++++
3 files changed, 121 insertions(+)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 0000000..42c084e
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for at91 specific clk
+#
+
+obj-y += clk-main.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 0000000..738fa39
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,106 @@
+/*
+ * drivers/clk/at91/clk-main.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This mainram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
+struct clk_main {
+ struct clk_hw hw;
+ unsigned long rate;
+};
+
+static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_main *clkmain = to_clk_main(hw);
+ if (clkmain->rate)
+ return clkmain->rate;
+ while ((tmp = at91_pmc_read(AT91_CKGR_MCFR)) & AT91_PMC_MAINRDY)
+ ;
+ tmp &= AT91_PMC_MAINF;
+ clkmain->rate = (tmp * parent_rate) / 16;
+ return clkmain->rate;
+}
+
+static const struct clk_ops main_ops = {
+ .recalc_rate = clk_main_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate)
+{
+ struct clk_main *clkmain;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ if (!rate && !parent_name)
+ return ERR_PTR(-EINVAL);
+
+ clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
+ if (!clkmain)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &main_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = parent_name ? 0 : CLK_IS_ROOT;
+
+ clkmain->hw.init = &init;
+ clkmain->rate = rate;
+
+ clk = clk_register(NULL, &clkmain->hw);
+
+ if (IS_ERR(clk))
+ kfree(clkmain);
+
+ return clk;
+}
+
+
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_main_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 rate = 0;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ of_property_read_string(np, "clock-output-names", &name);
+ of_property_read_u32(np, "clock-frequency", &rate);
+
+ clk = at91_clk_register_main(name, parent_name, rate);
+
+ if (!IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
+{
+ of_at91_clk_main_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
+ of_at91rm9200_clk_main_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 58b1eba..c0801e7 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -16,6 +16,8 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
+#include <linux/clk-provider.h>
+
#ifndef __ASSEMBLY__
extern void __iomem *at91_pmc_base;
@@ -184,4 +186,12 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+
+
+
+struct clk * __init
+at91_clk_register_main(const char *name,
+ const char *parent_name,
+ unsigned long rate);
+
#endif
--
1.7.9.5
This is the at91 pll clock implementation using common clk framework.
The pll clock layout describe the PLLX register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3
PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-pll.c | 438 +++++++++++++++++++++++++++++++++++++++++
drivers/clk/at91/clk-plldiv.c | 125 ++++++++++++
include/linux/clk/at91.h | 39 ++++
4 files changed, 603 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 42c084e..564076f 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 0000000..d5dc0ac
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,438 @@
+/*
+ * drivers/clk/at91/clk-pll.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This pllram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
+
+struct clk_pll {
+ struct clk_hw hw;
+ u8 id;
+ u8 div;
+ u8 range;
+ u16 mul;
+ struct clk_pll_layout *layout;
+ struct clk_pll_characteristics *characteristics;
+};
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (AT91_PMC_LOCKA + pll->id))))
+ ;
+ return 0;
+}
+
+static int clk_pll_is_prepared(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (AT91_PMC_LOCKA + pll->id)));
+}
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+ return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ at91_pmc_write(offset, tmp);
+}
+
+static int clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) &
+ (1 << (AT91_PMC_LOCKA + pll->id)));
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ u32 tmp = at91_pmc_read(offset) & layout->pllr_mask;
+ u8 div = tmp & 0xFF;
+ u16 mul = (tmp >> layout->mul_shift) & layout->mul_mask;
+ if (!div || !mul)
+ return 0;
+
+ return (parent_rate * (mul + 1)) / div;
+}
+
+static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
+ unsigned long parent_rate,
+ u32 *div, u32 *mul,
+ u32 *index) {
+ unsigned long maxrate;
+ unsigned long minrate;
+ unsigned long divrate;
+ unsigned long bestdiv = 1;
+ unsigned long bestmul;
+ unsigned long tmpdiv;
+ unsigned long roundup;
+ unsigned long rounddown;
+ unsigned long remainder;
+ unsigned long bestremainder;
+ unsigned long maxmul;
+ unsigned long maxdiv;
+ unsigned long mindiv;
+ int i = 0;
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+
+ /* Minimum divider = 1 */
+ /* Maximum multiplier = max_mul */
+ maxmul = layout->mul_mask + 1;
+ maxrate = (parent_rate * maxmul) / 1;
+
+ /* Maximum divider = max_div */
+ /* Minimum multiplier = 2 */
+ maxdiv = 0xFF;
+ minrate = (parent_rate * 2) / maxdiv;
+
+ if (parent_rate < characteristics->input.min ||
+ parent_rate < characteristics->input.max)
+ return -ERANGE;
+
+ if (parent_rate < minrate || parent_rate > maxrate)
+ return -ERANGE;
+
+ for (i = 0; i < characteristics->num_output; ++i) {
+ if (parent_rate >= characteristics->output[i].min &&
+ parent_rate <= characteristics->output[i].max)
+ break;
+ ++i;
+ }
+
+ if (i >= characteristics->num_output)
+ return -ERANGE;
+
+ bestmul = rate / parent_rate;
+ rounddown = parent_rate % rate;
+ roundup = rate - rounddown;
+ bestremainder = roundup < rounddown ? roundup : rounddown;
+
+ if (!bestremainder) {
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+ return rate;
+ }
+
+ maxdiv = 255 / (bestmul + 1);
+ if (parent_rate / maxdiv < characteristics->input.min)
+ maxdiv = parent_rate / characteristics->input.min;
+ mindiv = parent_rate / characteristics->input.max;
+ if (parent_rate % characteristics->input.max)
+ mindiv++;
+
+ for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
+ divrate = parent_rate / tmpdiv;
+
+ rounddown = rate % divrate;
+ roundup = divrate - rounddown;
+ remainder = roundup < rounddown ? roundup : rounddown;
+
+ if (remainder < bestremainder) {
+ bestremainder = remainder;
+ bestmul = rate / divrate;
+ bestdiv = tmpdiv;
+ }
+
+ if (!remainder)
+ break;
+ }
+
+ rate = (parent_rate / bestdiv) * bestmul;
+
+ if (div)
+ *div = bestdiv;
+ if (mul)
+ *mul = bestmul;
+ if (index)
+ *index = i;
+
+ return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
+ NULL, NULL, NULL);
+
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = to_clk_pll(hw);
+ struct clk_pll_layout *layout = pll->layout;
+ struct clk_pll_characteristics *characteristics = pll->characteristics;
+ int offset = AT91_CKGR_PLLAR + (pll->id * 4);
+ long ret;
+ u32 div;
+ u32 mul;
+ u32 index;
+ u32 tmp;
+ u8 out = 0;
+ ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
+ &div, &mul, &index);
+
+ if (ret < 0)
+ return ret;
+
+ if (characteristics->out)
+ out = characteristics->out[pll->range];
+ if (characteristics->icpll) {
+ tmp = at91_pmc_read(AT91_PMC_PLLICPR) &
+ ~(0xFFFF << (16 * pll->id));
+ tmp |= characteristics->icpll[pll->range] << (16 * pll->id);
+ at91_pmc_write(AT91_PMC_PLLICPR, tmp);
+ }
+ tmp = at91_pmc_read(offset) & ~(layout->pllr_mask);
+ tmp |= layout->pllr_mask & (div | 0x3F << 8 | out << 14 |
+ (mul & layout->mul_mask) <<
+ layout->mul_shift);
+ at91_pmc_write(offset, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops pll_ops = {
+ .prepare = clk_pll_prepare,
+ .is_prepared = clk_pll_is_prepared,
+ .enable = clk_pll_enable,
+ .disable = clk_pll_disable,
+ .is_enabled = clk_pll_is_enabled,
+ .recalc_rate = clk_pll_recalc_rate,
+ .round_rate = clk_pll_round_rate,
+ .set_rate = clk_pll_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics)
+{
+ struct clk_pll *pll;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 3;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &pll_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ pll->id = id;
+ pll->hw.init = &init;
+ pll->layout = layout;
+ pll->characteristics = characteristics;
+
+ clk = clk_register(NULL, &pll->hw);
+
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+
+struct clk_pll_layout at91rm9200_pll_layout = {
+ .pllr_mask = 0x7FFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x7FF,
+};
+
+struct clk_pll_layout at91sam9g45_pll_layout = {
+ .pllr_mask = 0xFFFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0xFF,
+};
+
+struct clk_pll_layout at91sam9g20_pllb_layout = {
+ .pllr_mask = 0x3FFFFF,
+ .mul_shift = 16,
+ .mul_mask = 0x3F,
+};
+
+struct clk_pll_layout sama5d3_pll_layout = {
+ .pllr_mask = 0x1FFFFFF,
+ .mul_shift = 18,
+ .mul_mask = 0x7F,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_pll_characteristics * __init
+of_at91_clk_pll_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ int num_output;
+ struct clk_range *output = NULL;
+ u8 *out = NULL;
+ u16 *icpll = NULL;
+ struct clk_pll_characteristics *characteristics = NULL;
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "input", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.min = tmp;
+
+ if (of_property_read_u32_index(np, "input", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->input.max = tmp;
+
+ if (!of_get_property(np, "output", &num_output))
+ goto out_free_characteristics;
+ num_output /= (sizeof(u32) * 2);
+
+ output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "output", i * 2, &tmp))
+ goto out_free_output;
+ output[i].min = tmp;
+ if (of_property_read_u32_index(np, "output", (i * 2) + 1, &tmp))
+ goto out_free_output;
+ output[i].max = tmp;
+ }
+
+ if (of_get_property(np, "out", NULL)) {
+ out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
+ if (!out)
+ goto out_free_output;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "out", i, &tmp))
+ goto out_free_out;
+ out[i] = tmp;
+ }
+ }
+
+ if (of_get_property(np, "icpll", NULL)) {
+ icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
+ if (!icpll)
+ goto out_free_out;
+ for (i = 0; i < num_output; i++) {
+ if (of_property_read_u32_index(np, "icpll", i, &tmp))
+ goto out_free_icpll;
+ icpll[i] = tmp;
+ }
+ }
+
+ characteristics->num_output = num_output;
+ characteristics->output = output;
+ characteristics->out = out;
+ characteristics->icpll = icpll;
+ return characteristics;
+
+out_free_icpll:
+ kfree(icpll);
+out_free_out:
+ kfree(out);
+out_free_output:
+ kfree(output);
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_pll_setup(struct device_node *np,
+ struct clk_pll_layout *layout)
+{
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ struct clk_pll_characteristics *characteristics;
+
+ if (of_property_read_u32(np, "id", &id))
+ return;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_pll_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_pll(name, parent_name, id, layout,
+ characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
+ of_at91rm9200_clk_pll_setup);
+
+static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
+ of_at91sam9g45_clk_pll_setup);
+
+static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
+}
+CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
+ of_at91sam9g20_clk_pllb_setup);
+
+static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
+{
+ of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
+}
+CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
+ of_sama5d3_clk_pll_setup);
+#endif
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 0000000..430de9b
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,125 @@
+/*
+ * drivers/clk/at91/clk-plldiv.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This plldivram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
+
+struct clk_plldiv {
+ struct clk_hw hw;
+};
+
+static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
+ return parent_rate / 2;
+ return parent_rate;
+}
+
+static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ if (rate > *parent_rate)
+ return *parent_rate;
+ div = *parent_rate / 2;
+ if (rate < div)
+ return div;
+
+ if (rate - div < *parent_rate - rate)
+ return div;
+
+ return *parent_rate;
+}
+
+static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ if (parent_rate != rate && (parent_rate / 2) != rate)
+ return -EINVAL;
+
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
+ if ((parent_rate / 2) == rate)
+ tmp |= AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops plldiv_ops = {
+ .recalc_rate = clk_plldiv_recalc_rate,
+ .round_rate = clk_plldiv_round_rate,
+ .set_rate = clk_plldiv_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name)
+{
+ struct clk_plldiv *plldiv;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
+ if (!plldiv)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &plldiv_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ plldiv->hw.init = &init;
+
+ clk = clk_register(NULL, &plldiv->hw);
+
+ if (IS_ERR(clk))
+ kfree(plldiv);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_plldiv_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_plldiv(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
+{
+ of_at91_clk_plldiv_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
+ of_at91sam9x5_clk_plldiv_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index c0801e7..7ba038f 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -163,6 +163,8 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
@@ -187,6 +189,26 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
+struct clk_range {
+ unsigned long min;
+ unsigned long max;
+};
+
+#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
+
+struct clk_pll_characteristics {
+ struct clk_range input;
+ int num_output;
+ struct clk_range *output;
+ u16 *icpll;
+ u8 *out;
+};
+
+struct clk_pll_layout {
+ u32 pllr_mask;
+ u16 mul_mask;
+ u8 mul_shift;
+};
struct clk * __init
@@ -194,4 +216,21 @@ at91_clk_register_main(const char *name,
const char *parent_name,
unsigned long rate);
+
+extern struct clk_pll_layout at91rm9200_pll_layout;
+
+extern struct clk_pll_layout at91sam9g45_pll_layout;
+
+extern struct clk_pll_layout at91sam9g20_pllb_layout;
+
+extern struct clk_pll_layout sama5d3_pll_layout;
+
+struct clk * __init
+at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
+ struct clk_pll_layout *layout,
+ struct clk_pll_characteristics *characteristics);
+
+struct clk * __init
+at91_clk_register_plldiv(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
This is the at91 system clock implementation using common clk framework.
Some peripheral needs to enable a "system" clock in order to work properly.
Each system clock is given an id which is the bit offset used in SCER/SCDR
registers.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-system.c | 189 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 3 +
3 files changed, 193 insertions(+)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index d41f616..13e5714 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,3 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
+obj-y += clk-system.o
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 0000000..21af468
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,189 @@
+/*
+ * drivers/clk/at91/clk-system.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SYSTEM_MAX 32
+
+#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
+struct clk_system {
+ struct clk_hw hw;
+ u8 id;
+};
+
+static int clk_system_enable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCER, sys->id);
+ return 0;
+}
+
+static void clk_system_disable(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ at91_pmc_write(AT91_PMC_SCDR, 1 << sys->id);
+}
+
+static int clk_system_is_enabled(struct clk_hw *hw)
+{
+ struct clk_system *sys = to_clk_system(hw);
+ return !!(at91_pmc_read(AT91_PMC_SCSR) & (sys->id));
+}
+
+static const struct clk_ops system_ops = {
+ .enable = clk_system_enable,
+ .disable = clk_system_disable,
+ .is_enabled = clk_system_is_enabled,
+};
+
+struct clk * __init
+at91_clk_register_system(const char *name, const char *parent_name, u8 id)
+{
+ struct clk_system *sys;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+
+ sys = kzalloc(sizeof(*sys), GFP_KERNEL);
+ if (!sys)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &system_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = 0;
+
+ sys->id = id;
+ sys->hw.init = &init;
+
+ clk = clk_register(NULL, &sys->hw);
+
+ if (IS_ERR(clk))
+ kfree(sys);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_system_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_system_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_system_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= SYSTEM_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_sys_setup(struct device_node *np)
+{
+ int i;
+ int num;
+ u32 id;
+ struct clk *clk;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_system_data *clktab;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ if (!of_get_property(np, "ids", &num))
+ return;
+ num /= 4;
+ if (num > SYSTEM_MAX)
+ return;
+
+ if (of_count_phandle_with_args(np, "clocks", "#clock-cells") != num)
+ return;
+
+ if (of_property_count_strings(np, "clock-output-names") != num)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ for (i = 0; i < num; i++) {
+ of_property_read_u32_index(np, "ids", i, &id);
+ if (id >= SYSTEM_MAX)
+ goto out_free_clks;
+ of_property_read_string_index(np, "clock-output-names",
+ i, &name);
+ parent_name = of_clk_get_parent_name(np, i);
+ if (!parent_name)
+ goto out_free_clks;
+
+ clk = at91_clk_register_system(name, parent_name, id);
+ if (IS_ERR(clk))
+ goto out_free_clks;
+
+ clks[i] = clk;
+ ids[i] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_system_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
+{
+ of_at91_clk_sys_setup(np);
+}
+CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
+ of_at91rm9200_clk_sys_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index a960e2f..c886226 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -256,4 +256,7 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk_master_characteristics *characteristics);
+struct clk * __init
+at91_clk_register_system(const char *name, const char *parent_name, u8 id);
+
#endif
--
1.7.9.5
This is the at91 programmable clocks implementation using common clk
framework.
A programmable clock is a clock which can be exported on a given pin to clock
external devices.
Each programmable clock is given an id (from 0 to 8).
The number of available programmable clocks depends on the SoC you're using.
Programmable clock driver only implements the clock setting (clock rate and
parent setting). It must be chained to a system clock in order to
enable/disable the generated clock.
The PCKX pins used to output the clock signals must be assigned to the
appropriate peripheral (see atmel's datasheets).
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-programmable.c | 370 +++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 18 ++
3 files changed, 390 insertions(+)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 3e2a670..2d7c119 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -4,3 +4,5 @@
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
+
+obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 0000000..e4b1fb0
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,370 @@
+/*
+ * drivers/clk/at91/clk-programmable.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PROG_SOURCE_MAX 5
+#define PROG_MAX 8
+
+#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
+struct clk_programmable {
+ struct clk_hw hw;
+ u8 id;
+ u8 css;
+ u8 pres;
+ u8 slckmck;
+ struct clk_programmable_layout *layout;
+};
+
+static int clk_programmable_prepare(struct clk_hw *hw)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = prog->css | (prog->pres << layout->pres_shift);
+ if (layout->have_slck_mck && prog->slckmck)
+ tmp |= 1 << 8;
+ at91_pmc_write(AT91_PMC_PCKR(prog->id), tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & (AT91_PMC_PCK0RDY << prog->id)))
+ ;
+ return 0;
+}
+
+static int clk_programmable_is_prepared(struct clk_hw *hw)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ return !!(at91_pmc_read(AT91_PMC_SR) & (AT91_PMC_PCK0RDY << prog->id));
+}
+
+static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->pres = (tmp >> layout->pres_shift) & 0x7;
+ return parent_rate >> prog->pres;
+}
+
+static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long best_rate = *parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = shift;
+
+ if (rate > *parent_rate)
+ return *parent_rate;
+ else
+ best_diff = *parent_rate - rate;
+
+ if (!best_diff)
+ return best_rate;
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = *parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ return cur_rate;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ return best_rate;
+}
+
+static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ if (index > layout->css_mask) {
+ if (index == 4 && layout->have_slck_mck) {
+ prog->css = 0;
+ prog->slckmck = 1;
+ return 0;
+ } else
+ return -EINVAL;
+ }
+
+ prog->css = index;
+ return 0;
+}
+
+static u8 clk_programmable_get_parent(struct clk_hw *hw)
+{
+ u32 tmp;
+ u8 ret;
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ struct clk_programmable_layout *layout = prog->layout;
+ tmp = at91_pmc_read(AT91_PMC_PCKR(prog->id));
+ prog->css = tmp & layout->css_mask;
+ ret = prog->css;
+ if (layout->have_slck_mck) {
+ prog->slckmck = !!(tmp & (1 << 8));
+ if (prog->slckmck && !ret)
+ ret = 4;
+ }
+
+ return ret;
+}
+
+static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_programmable *prog = to_clk_programmable(hw);
+ unsigned long best_rate = parent_rate;
+ unsigned long best_diff;
+ unsigned long new_diff;
+ unsigned long cur_rate;
+ int shift = 0;
+
+ if (rate > parent_rate)
+ return parent_rate;
+ else
+ best_diff = parent_rate - rate;
+
+ if (!best_diff) {
+ prog->pres = shift;
+ return 0;
+ }
+
+ for (shift = 1; shift < 7; shift++) {
+ cur_rate = parent_rate >> shift;
+
+ if (cur_rate > rate)
+ new_diff = cur_rate - rate;
+ else
+ new_diff = rate - cur_rate;
+
+ if (!new_diff)
+ break;
+
+ if (new_diff < best_diff) {
+ best_diff = new_diff;
+ best_rate = cur_rate;
+ }
+
+ if (rate > cur_rate)
+ break;
+
+ }
+
+ prog->pres = shift;
+ return 0;
+}
+
+static const struct clk_ops programmable_ops = {
+ .prepare = clk_programmable_prepare,
+ .is_prepared = clk_programmable_is_prepared,
+ .recalc_rate = clk_programmable_recalc_rate,
+ .round_rate = clk_programmable_round_rate,
+ .get_parent = clk_programmable_get_parent,
+ .set_parent = clk_programmable_set_parent,
+ .set_rate = clk_programmable_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout)
+{
+ struct clk_programmable *prog;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 7;
+
+ prog = kzalloc(sizeof(*prog), GFP_KERNEL);
+ if (!prog)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &programmable_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ prog->id = id;
+ prog->layout = layout;
+ prog->hw.init = &init;
+
+ clk = clk_register(NULL, &prog->hw);
+
+ if (IS_ERR(clk))
+ kfree(prog);
+
+ return clk;
+}
+
+struct clk_programmable_layout at91rm9200_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 0,
+};
+
+struct clk_programmable_layout at91sam9g45_programmable_layout = {
+ .pres_shift = 2,
+ .css_mask = 0x3,
+ .have_slck_mck = 1,
+};
+
+struct clk_programmable_layout at91sam9x5_programmable_layout = {
+ .pres_shift = 4,
+ .css_mask = 0x7,
+ .have_slck_mck = 0,
+};
+
+#if defined(CONFIG_OF)
+struct clk_prog_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_prog_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PROG_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_prog_setup(struct device_node *np,
+ struct clk_programmable_layout *layout)
+{
+ int num;
+ u32 id;
+ int i;
+ struct clk *clk;
+ int num_parents;
+ u8 *ids;
+ struct clk **clks;
+ struct clk_prog_data *clktab;
+ const char *parent_names[PROG_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ if (!of_get_property(np, "ids", &num))
+ return;
+
+ num /= 4;
+ if (num > PROG_MAX)
+ return;
+
+ if (of_property_count_strings(np, "clock-output-names") != num)
+ return;
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ for (i = 0; i < num; i++) {
+ of_property_read_u32_index(np, "ids", i, &id);
+ if (id >= PROG_MAX)
+ goto out_free_clks;
+ of_property_read_string_index(np, "clock-output-names",
+ i, &name);
+ clk = at91_clk_register_programmable(name, parent_names,
+ num_parents, id, layout);
+
+ if (IS_ERR(clk))
+ goto out_free_clks;
+ clks[i] = clk;
+ ids[i] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+
+static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
+ of_at91rm9200_clk_prog_setup);
+
+static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
+ of_at91sam9g45_clk_prog_setup);
+
+static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
+{
+ of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
+ of_at91sam9x5_clk_prog_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 4addfd6..eccdf74 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -221,6 +221,12 @@ struct clk_master_layout {
u8 pres_shift;
};
+struct clk_programmable_layout {
+ u8 pres_shift;
+ u8 css_mask;
+ u8 have_slck_mck;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -267,4 +273,16 @@ struct clk * __init
at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
u32 id, u32 default_div);
+
+extern struct clk_programmable_layout at91rm9200_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9g45_programmable_layout;
+
+extern struct clk_programmable_layout at91sam9x5_programmable_layout;
+
+struct clk * __init
+at91_clk_register_programmable(const char *name, const char **parent_names,
+ u8 num_parents, u8 id,
+ struct clk_programmable_layout *layout);
+
#endif
--
1.7.9.5
This is the at91 peripheral clock implementation using common clk framework.
Almost all peripherals provided by an at91 SoC need a clock to work properly.
This clock is enabled/disabled using PCER/PCDR resgisters.
Each peripheral is given an id (see atmel's datasheets) which is used as bit
position in SCER/SCDR registers.
Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you
can configure the peripheral clock as a division of the master clock.
This will help reducing the peripherals power comsumption.
This patch fixes erronous AT91_PMC_PCR_DIV values.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-peripheral.c | 376 +++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 14 +-
3 files changed, 388 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 13e5714..3e2a670 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -3,4 +3,4 @@
#
obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
-obj-y += clk-system.o
+obj-y += clk-system.o clk-peripheral.o
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 0000000..2fc66b9
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,376 @@
+/*
+ * drivers/clk/at91/clk-peripheral.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define PERIPHERAL_MAX 64
+
+#define PERIPHERAL_AT91RM9200 0
+#define PERIPHERAL_AT91SAM9X5 1
+
+#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
+struct clk_peripheral {
+ struct clk_hw hw;
+ u32 id;
+};
+
+#define to_clk_sam9x5_peripheral(hw) \
+ container_of(hw, struct clk_sam9x5_peripheral, hw)
+struct clk_sam9x5_peripheral {
+ struct clk_hw hw;
+ u32 id;
+ u8 div;
+ u8 have_div_support;
+};
+
+static int clk_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCER;
+ if (periph->id < 2)
+ return 0;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCER1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+ return 0;
+}
+
+static void clk_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCDR;
+ if (periph->id < 2)
+ return;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCDR1;
+ at91_pmc_write(offset, 1 << (periph->id & 31));
+}
+
+static int clk_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_peripheral *periph = to_clk_peripheral(hw);
+ int offset = AT91_PMC_PCSR;
+ if (periph->id < 2)
+ return 1;
+ if (periph->id > 31)
+ offset = AT91_PMC_PCSR1;
+ return !!(at91_pmc_read(offset) & (1 << (periph->id & 31)));
+}
+
+static const struct clk_ops peripheral_ops = {
+ .enable = clk_peripheral_enable,
+ .disable = clk_peripheral_disable,
+ .is_enabled = clk_peripheral_is_enabled,
+};
+
+struct clk * __init at91_clk_register_peripheral(const char *name,
+ const char *parent_name,
+ u32 id)
+{
+ struct clk_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ id &= 31;
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = 0;
+
+ periph->id = id;
+ periph->hw.init = &init;
+
+ clk = clk_register(NULL, &periph->hw);
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 0;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD |
+ AT91_PMC_PCR_DIV(periph->div) |
+ AT91_PMC_PCR_EN);
+ return 0;
+}
+
+static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return;
+
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID) |
+ AT91_PMC_PCR_CMD);
+}
+
+static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2)
+ return 1;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ return !!(at91_pmc_read(AT91_PMC_PCR) & AT91_PMC_PCR_EN);
+}
+
+static unsigned long
+clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ u32 shift;
+ if (periph->id < 2 || !periph->have_div_support)
+ return parent_rate;
+ at91_pmc_write(AT91_PMC_PCR,
+ (periph->id & AT91_PMC_PCR_PID));
+ shift = (at91_pmc_read(AT91_PMC_PCR) >> 16) & 0x3;
+ return parent_rate >> shift;
+}
+
+static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int shift;
+ unsigned long best_rate;
+ unsigned long best_diff;
+ unsigned long cur_rate;
+ unsigned long cur_diff;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support)
+ return *parent_rate;
+ if (rate >= *parent_rate)
+ return rate;
+ best_diff = *parent_rate - rate;
+ best_rate = *parent_rate;
+ for (shift = 1; shift < 4; shift++) {
+ cur_rate = *parent_rate >> shift;
+ if (cur_rate < rate)
+ cur_diff = rate - cur_rate;
+ else
+ cur_diff = cur_rate - rate;
+ if (cur_diff < best_diff) {
+ best_diff = cur_diff;
+ best_rate = cur_rate;
+ }
+ if (!best_diff || cur_rate < rate)
+ break;
+ }
+ return best_rate;
+}
+
+static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ int shift;
+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
+ if (periph->id < 2 || !periph->have_div_support) {
+ if (parent_rate == rate)
+ return 0;
+ else
+ return -EINVAL;
+ }
+
+ for (shift = 0; shift < 4; shift++) {
+ if (parent_rate >> shift == rate) {
+ periph->div = shift;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops sam9x5_peripheral_ops = {
+ .enable = clk_sam9x5_peripheral_enable,
+ .disable = clk_sam9x5_peripheral_disable,
+ .is_enabled = clk_sam9x5_peripheral_is_enabled,
+ .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
+ .round_rate = clk_sam9x5_peripheral_round_rate,
+ .set_rate = clk_sam9x5_peripheral_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name,
+ const char *parent_name,
+ u32 id, u32 default_div)
+{
+ struct clk_sam9x5_peripheral *periph;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ periph = kzalloc(sizeof(*periph), GFP_KERNEL);
+ if (!periph)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &sam9x5_peripheral_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = CLK_SET_RATE_GATE;
+
+ periph->id = id;
+ periph->hw.init = &init;
+ periph->div = default_div;
+
+ clk = clk_register(NULL, &periph->hw);
+
+ if (IS_ERR(clk))
+ kfree(periph);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+struct clk_periph_data {
+ struct clk **clks;
+ u8 *ids;
+ unsigned int clk_num;
+};
+
+static struct clk * __init
+of_clk_src_periph_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct clk_periph_data *clk_data = data;
+ unsigned int id = clkspec->args[0];
+ int i;
+
+ if (id >= PERIPHERAL_MAX)
+ goto err;
+
+ for (i = 0; i < clk_data->clk_num; i++) {
+ if (clk_data->ids[i] == id)
+ return clk_data->clks[i];
+ }
+
+err:
+ pr_err("%s: invalid clock id %d\n", __func__, id);
+ return ERR_PTR(-EINVAL);
+}
+
+static void __init
+of_at91_clk_periph_setup(struct device_node *np, u8 type)
+{
+ int num;
+ int tmp;
+ int i;
+ u32 id;
+ struct clk *clk;
+ const char *parent_name;
+ const char *name;
+ u32 divisor;
+ struct clk **clks;
+ u8 *ids;
+ struct clk_periph_data *clktab;
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ if (!of_get_property(np, "ids", &num))
+ return;
+
+ num /= 4;
+ if (num > PERIPHERAL_MAX)
+ return;
+
+ if (of_property_count_strings(np, "clock-output-names") != num)
+ return;
+
+ if (type == PERIPHERAL_AT91SAM9X5) {
+ if (of_get_property(np, "default-divisors", &tmp) &&
+ (tmp / 4) != num)
+ return;
+ }
+
+ clktab = kzalloc(sizeof(*clktab), GFP_KERNEL);
+ if (!clktab)
+ return;
+
+ ids = kzalloc(num * sizeof(*ids), GFP_KERNEL);
+ if (!ids)
+ goto out_free_clktab;
+
+ clks = kzalloc(num * sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ goto out_free_ids;
+
+ for (i = 0; i < num; i++) {
+ of_property_read_u32_index(np, "ids", i, &id);
+ of_property_read_string_index(np, "clock-output-names",
+ i, &name);
+ if (type == PERIPHERAL_AT91RM9200) {
+ clk = at91_clk_register_peripheral(name,
+ parent_name, id);
+ } else {
+ if (of_property_read_u32_index(np, "default-divisors",
+ i,
+ &divisor))
+ divisor = 0;
+
+ clk = at91_clk_register_sam9x5_peripheral(name,
+ parent_name,
+ id,
+ divisor);
+ }
+ if (IS_ERR(clk))
+ goto out_free_clks;
+ clks[i] = clk;
+ ids[i] = id;
+ }
+
+ clktab->clk_num = num;
+ clktab->clks = clks;
+ clktab->ids = ids;
+ of_clk_add_provider(np, of_clk_src_periph_get, clktab);
+ return;
+
+out_free_clks:
+ kfree(clks);
+out_free_ids:
+ kfree(ids);
+out_free_clktab:
+ kfree(clktab);
+}
+
+static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
+}
+CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
+ of_at91rm9200_clk_periph_setup);
+
+static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
+{
+ of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
+ of_at91sam9x5_clk_periph_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index c886226..4addfd6 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -183,9 +183,9 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */
#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */
-#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */
-#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */
-#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */
+#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */
+#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */
+#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
@@ -259,4 +259,12 @@ at91_clk_register_master(const char *name, int num_parents,
struct clk * __init
at91_clk_register_system(const char *name, const char *parent_name, u8 id);
+struct clk * __init
+at91_clk_register_peripheral(const char *name, const char *parent_name,
+ u32 id);
+
+struct clk * __init
+at91_clk_register_sam9x5_peripheral(const char *name, const char *parent_name,
+ u32 id, u32 default_div);
+
#endif
--
1.7.9.5
This is the at91 utmi clock implementation using common clk framework.
This clock is a pll with a fixed factor (x40).
It is used as a source for usb clock.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 7 +++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-utmi.c | 114 +++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 4 ++
4 files changed, 126 insertions(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0280238..a4d442d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,8 @@
if ARCH_AT91
+config HAVE_AT91_UTMI
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -65,6 +68,7 @@ config SOC_SAMA5D3
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -106,12 +110,14 @@ config SOC_AT91SAM9RL
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
config SOC_AT91SAM9G45
bool "AT91SAM9G45 or AT91SAM9M10 families"
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +127,7 @@ config SOC_AT91SAM9X5
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_UTMI
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 2d7c119..76d09f0 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 0000000..c0dd596
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,114 @@
+/*
+ * drivers/clk/at91/clk-utmi.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This utmiram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
+
+struct clk_utmi {
+ struct clk_hw hw;
+};
+
+static int clk_utmi_prepare(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
+ AT91_PMC_UPLLCOUNT;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU))
+ ;
+ return 0;
+}
+
+static int clk_utmi_is_prepared(struct clk_hw *hw)
+{
+ return !!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU);
+}
+
+static void clk_utmi_disable(struct clk_hw *hw)
+{
+ u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
+ at91_pmc_write(AT91_CKGR_UCKR, tmp);
+}
+
+static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return parent_rate * 40;
+}
+
+static const struct clk_ops utmi_ops = {
+ .prepare = clk_utmi_prepare,
+ .is_prepared = clk_utmi_is_prepared,
+ .disable = clk_utmi_disable,
+ .recalc_rate = clk_utmi_recalc_rate,
+};
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name)
+{
+ struct clk_utmi *utmi;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
+ if (!utmi)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &utmi_ops;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+ init.flags = CLK_SET_RATE_GATE;
+
+ utmi->hw.init = &init;
+
+ clk = clk_register(NULL, &utmi->hw);
+
+ if (IS_ERR(clk))
+ kfree(utmi);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init
+of_at91_clk_utmi_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91_clk_register_utmi(name, parent_name);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+}
+
+static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
+{
+ of_at91_clk_utmi_setup(np);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
+ of_at91sam9x5_clk_utmi_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index eccdf74..18c89c2 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -285,4 +285,8 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
u8 num_parents, u8 id,
struct clk_programmable_layout *layout);
+
+struct clk * __init
+at91_clk_register_utmi(const char *name, const char *parent_name);
+
#endif
--
1.7.9.5
This is the at91 usb clock implementation using common clk framework.
This clock is used to clock usb ports (ohci, ehci and udc).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 11 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-usb.c | 303 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 9 ++
4 files changed, 324 insertions(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a4d442d..ce4851d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,9 @@ if ARCH_AT91
config HAVE_AT91_UTMI
bool
+config HAVE_AT91_USB_CLK
+ bool
+
config HAVE_AT91_DBGU0
bool
@@ -69,6 +72,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -82,11 +86,13 @@ config SOC_AT91RM9200
select HAVE_AT91_DBGU0
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
select HAVE_AT91_DBGU0
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@@ -96,6 +102,7 @@ config SOC_AT91SAM9261
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -104,6 +111,7 @@ config SOC_AT91SAM9263
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
config SOC_AT91SAM9RL
bool "AT91SAM9RL"
@@ -118,6 +126,7 @@ config SOC_AT91SAM9G45
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -128,6 +137,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
@@ -140,6 +150,7 @@ config SOC_AT91SAM9N12
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
+ select HAVE_AT91_USB_CLK
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 76d09f0..bbfd245 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
+obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 0000000..008372e
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,303 @@
+/*
+ * drivers/clk/at91/clk-usb.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This usbram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define USB_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_usb(hw) \
+ container_of(hw, struct at91sam9x5_clk_usb, hw)
+struct at91sam9x5_clk_usb {
+ struct clk_hw hw;
+ u8 usbs0_unused; /* sam9n12 uses usbs0 to disable usb clock */
+};
+
+#define to_at91rm9200_clk_usb(hw) \
+ container_of(hw, struct at91rm9200_clk_usb, hw)
+struct at91rm9200_clk_usb {
+ struct clk_hw hw;
+ u32 divisors[4];
+};
+
+static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_PMC_USB);
+ usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> 8;
+ return parent_rate / (usbdiv + 1);
+}
+
+static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ index++;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_USBS;
+ if (index)
+ tmp |= AT91_PMC_USBS;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
+{
+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
+ if (usb->usbs0_unused)
+ return 0;
+ return at91_pmc_read(AT91_PMC_USB) & AT91_PMC_USBS;
+}
+
+static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_usb_ops = {
+ .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
+ .round_rate = at91sam9x5_clk_usb_round_rate,
+ .get_parent = at91sam9x5_clk_usb_get_parent,
+ .set_parent = at91sam9x5_clk_usb_set_parent,
+ .set_rate = at91sam9x5_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused)
+{
+ struct at91sam9x5_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_usb_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ usb->usbs0_unused = usbs0_unused;
+ usb->hw.init = &init;
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ u32 tmp;
+ u8 usbdiv;
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR);
+ usbdiv = (tmp & AT91_PMC_USBDIV) >> 28;
+ if (usb->divisors[usbdiv])
+ return parent_rate / usb->divisors[usbdiv];
+ return 0;
+}
+
+static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long bestrate = 0;
+ int bestdiff = -1;
+ unsigned long tmprate;
+ int tmpdiff;
+ int i = 0;
+
+ for (i = 0; i < 4; i++) {
+ if (!usb->divisors[i])
+ continue;
+ tmprate = *parent_rate / usb->divisors[i];
+ if (tmprate < rate)
+ tmpdiff = rate - tmprate;
+ else
+ tmpdiff = tmprate - rate;
+
+ if (bestdiff < 0 || bestdiff > tmpdiff) {
+ bestrate = tmprate;
+ bestdiff = tmpdiff;
+ }
+
+ if (!bestdiff)
+ break;
+ }
+
+ return bestrate;
+}
+
+static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ int i;
+ struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate)
+ return -EINVAL;
+ for (i = 0; i < 4; i++) {
+ if (usb->divisors[i] == div) {
+ tmp = at91_pmc_read(AT91_CKGR_PLLBR) &
+ ~AT91_PMC_USBDIV;
+ tmp |= i << 8;
+ at91_pmc_write(AT91_PMC_USB, tmp);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops at91rm9200_usb_ops = {
+ .recalc_rate = at91rm9200_clk_usb_recalc_rate,
+ .round_rate = at91rm9200_clk_usb_round_rate,
+ .set_rate = at91rm9200_clk_usb_set_rate,
+};
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors)
+{
+ struct at91rm9200_clk_usb *usb;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ usb = kzalloc(sizeof(*usb), GFP_KERNEL);
+ if (!usb)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91rm9200_usb_ops;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ usb->hw.init = &init;
+ memcpy(usb->divisors, divisors, sizeof(usb->divisors));
+
+ clk = clk_register(NULL, &usb->hw);
+
+ if (IS_ERR(clk))
+ kfree(usb);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ u8 usbs0_unused;
+ const char *parent_names[USB_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents >= USB_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ usbs0_unused = of_property_read_bool(np, "usbs0-unused");
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_usb(name, parent_names, num_parents,
+ usbs0_unused);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
+ of_at91sam9x5_clk_usb_setup);
+
+static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *parent_name;
+ const char *name = np->name;
+ u32 divisors[4] = {0, 0, 0, 0};
+
+ parent_name = of_clk_get_parent_name(np, 0);
+ if (!parent_name)
+ return;
+
+ of_property_read_u32_array(np, "divisors", divisors, 4);
+ if (!divisors[0])
+ return;
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91rm9200_clk_register_usb(name, parent_name, divisors);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
+ of_at91rm9200_clk_usb_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 18c89c2..8a88b38 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -289,4 +289,13 @@ at91_clk_register_programmable(const char *name, const char **parent_names,
struct clk * __init
at91_clk_register_utmi(const char *name, const char *parent_name);
+
+struct clk * __init
+at91rm9200_clk_register_usb(const char *name, const char *parent_name,
+ const u32 *divisors);
+
+struct clk * __init
+at91sam9x5_clk_register_usb(const char *name, const char **parent_names,
+ u8 num_parents, u8 usbs0_unused);
+
#endif
--
1.7.9.5
This is the documentation of the dt bindings used by at91 clks.
Signed-off-by: Boris BREZILLON <[email protected]>
---
.../devicetree/bindings/clock/at91-clock.txt | 247 ++++++++++++++++++++
1 file changed, 247 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
new file mode 100644
index 0000000..63c5d16
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -0,0 +1,247 @@
+Device Tree Clock bindings for arch-at91
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "atmel,at91rm9200-clk-main":
+ at91 main oscillator
+
+ "atmel,at91rm9200-clk-master" or
+ "atmel,at91sam9x5-clk-master":
+ at91 master clock
+
+ "atmel,at91sam9x5-clk-peripheral" or
+ "atmel,at91rm9200-clk-peripheral":
+ at91 peripheral clocks
+
+ "atmel,at91rm9200-clk-pll" or
+ "atmel,at91sam9g45-clk-pll" or
+ "atmel,at91sam9g20-clk-pllb" or
+ "atmel,sama5d3-clk-pll":
+ at91 pll clocks
+
+ "atmel,at91sam9x5-clk-plldiv":
+ at91 plla divisor
+
+ "atmel,at91rm9200-clk-programmable" or
+ "atmel,at91sam9g45-clk-programmable" or
+ "atmel,at91sam9x5-clk-programmable":
+ at91 programmable clocks
+
+ "atmel,at91sam9x5-clk-smd":
+ at91 SMD (Soft Modem) clock
+
+ "atmel,at91rm9200-clk-system":
+ at91 system clocks
+
+ "atmel,at91rm9200-clk-usb" or
+ "atmel,at91sam9x5-clk-usb":
+ at91 usb clock
+
+ "atmel,at91sam9x5-clk-utmi":
+ at91 utmi clock
+
+
+Required properties for main clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks (optional if clock-frequency is provided) : shall be the slow clock
+ phandle. This clock is used to compute the main clock rate if
+ "clock-frequency" is not provided.
+- clock-frequency: the main oscillator frequency.Prefer the use of
+ "clock-frequency" over automatic clock rate computation.
+
+For example:
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&ck32k>;
+ clock-frequency = <18432000>;
+ };
+
+Required properties for master clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock sources (see atmel datasheet) phandles.
+ e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
+- characteristics : device tree node describing master clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * output : minimum and maximum clock frequency (two u32 fields).
+ e.g. output = <0 133000000>; <=> 0 to 133MHz.
+ * divisors : master clock divisors table (four u32 fields).
+ 0 <=> reserved value.
+ e.g. divisors = <1 2 4 6>;
+ * have-div3-pres : some SoC use the reserved value 7 in the PRES field
+ as CLOCK_DIV3 (e.g sam9x5).
+
+For example:
+ mck: mck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ characteristics = {
+ output = <0 133000000>;
+ divisors = <1 2 4 0>;
+ };
+ };
+
+Required properties for peripheral clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the peripheral id. Peripheral ids are defined in
+ atmel's SoC datasheets.
+- clocks : shall be the master clock phandle.
+ e.g. clocks = <&mck>;
+- ids : peripheral ids (u32 array).
+- clock-output-names : name of clocks. These are the name used during clock
+ registration.
+- "default-divisors" (optional, only available for
+ "atmel,at91sam9x5-clk-peripheral") : sam9x5 and sama5d3 SoC provides
+ configurable peripheral clock divisors. If you define this property
+ (u32 array), the default divisor will be applied when enabling
+ peripheral clock. If not provided the peripheral clock is not divided.
+
+For example:
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 6 7>;
+ clock-output-names = "pioA_clk", "pioB_clk", "pioB_clk";
+ default-divisors = <1 2 2>;
+ };
+
+
+Required properties for pll clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock phandle.
+- id : pll id
+ * 0 <=> plla
+ * 1 <=> pllb
+- characteristics : device tree node describing pll clock characteristics.
+ You can find these characteristics in atmel's SoC datasheets.
+ * input : minimum and maximum source clock frequency (two u32 fields).
+ e.g. input = <1 32000000>; <=> 1 to 32MHz.
+ * output : output frequency ranges.
+ * out: out field value for output frequency ranges.
+ * icpll (not available on some SoC): icpll field value for output
+ frequency ranges.
+
+For example:
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+Required properties for plldiv clocks:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the plla clock phandle.
+
+For example:
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+Required properties for programmable clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the programmable clock id.
+ Peripheral ids are in atmel's SoC
+ datasheets.
+- clocks : shall be the programmable clock source phandles.
+ e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+- ids : programmable clock ids (u32 array).
+- clock-output-names : name of clocks. These names are used during clock
+ registration.
+
+For example:
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+
+Required properties for smd clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&plladiv>, <&utmi>;
+
+For example:
+ smd: smdck {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+Required properties for system clocks:
+- #clock-cells : from common clock binding; shall be set to 1. The second cell
+ is used to encode the system clock id (bit used in SCER/SCDR register).
+- clocks : shall be the system clock source phandle.
+ e.g. clocks = <&usb>;
+- ids : peripheral ids (u32 array).
+- clock-output-names : name of clocks. These names are used during clock
+ registration.
+
+For example:
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <2 4 6 7 8 9 10>;
+ clocks = <&mck>, <&smd>, <&usb>, <&usb>,
+ <&prog 0>, <&prog 1>, <&prog 2>;
+ clock-output-names = "ddrck", "smdck", "uhpck", "udpck",
+ "pck0", "pck1", "pck2";
+ };
+
+
+Required properties for usb clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the smd clock source phandles.
+ e.g. clocks = <&pllb>;
+- divisors (only available for "atmel,at91rm9200-clk-usb"):
+ usb clock divisor table.
+ e.g. divisors = <1 2 4 0>;
+- usbs0-unused (only available for "atmel,at91sam9x5-clk-usb"):
+ Some SoC (sam9n12) use usb source 0 to disable the usb clock.
+
+For example:
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+
+Required properties for utmi clock:
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the main clock source phandle.
+
+For example:
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
--
1.7.9.5
This is the at91 smd (Soft Modem) clock implementation using common clk
framework.
Not used by any driver right now.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 5 ++
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-smd.c | 157 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index ce4851d..8032871 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -27,6 +27,9 @@ config AT91_SAM9G45_RESET
config AT91_SAM9_TIME
bool
+config HAVE_AT91_SMD
+ bool
+
config SOC_AT91SAM9
bool
select AT91_SAM9_TIME
@@ -72,6 +75,7 @@ config SOC_SAMA5D3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's SAMA5D3 family SoC.
@@ -137,6 +141,7 @@ config SOC_AT91SAM9X5
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
+ select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index bbfd245..7206f4c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -8,3 +8,4 @@ obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
+obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 0000000..61bd8a5
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,157 @@
+/*
+ * drivers/clk/at91/clk-smd.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This smdram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define SMD_SOURCE_MAX 2
+
+#define to_at91sam9x5_clk_smd(hw) \
+ container_of(hw, struct at91sam9x5_clk_smd, hw)
+struct at91sam9x5_clk_smd {
+ struct clk_hw hw;
+};
+
+static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ u8 smddiv;
+ tmp = at91_pmc_read(AT91_PMC_SMD);
+ smddiv = (tmp & AT91_PMC_SMD_DIV) >> 8;
+ return parent_rate / (smddiv + 1);
+}
+
+static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long div;
+ unsigned long bestrate;
+ unsigned long tmp;
+
+ if (rate >= *parent_rate)
+ return *parent_rate;
+
+ div = *parent_rate / rate;
+ if (div > 15)
+ return *parent_rate / 16;
+
+ bestrate = *parent_rate / div;
+ tmp = *parent_rate / (div + 1);
+ if (bestrate - rate > rate - tmp)
+ bestrate = tmp;
+
+ return bestrate;
+}
+
+static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > 1)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMDS;
+ if (index)
+ tmp |= AT91_PMC_SMDS;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+ return 0;
+}
+
+static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_SMD) & AT91_PMC_SMDS;
+}
+
+static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 tmp;
+ unsigned long div = parent_rate / rate;
+ if (parent_rate % rate || div < 1 || div > 16)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
+ tmp |= (div - 1) << 8;
+ at91_pmc_write(AT91_PMC_SMD, tmp);
+
+ return 0;
+}
+
+static const struct clk_ops at91sam9x5_smd_ops = {
+ .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
+ .round_rate = at91sam9x5_clk_smd_round_rate,
+ .get_parent = at91sam9x5_clk_smd_get_parent,
+ .set_parent = at91sam9x5_clk_smd_set_parent,
+ .set_rate = at91sam9x5_clk_smd_set_rate,
+};
+
+struct clk * __init
+at91sam9x5_clk_register_smd(const char *name, const char **parent_names,
+ u8 num_parents)
+{
+ struct at91sam9x5_clk_smd *smd;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ smd = kzalloc(sizeof(*smd), GFP_KERNEL);
+ if (!smd)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &at91sam9x5_smd_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ smd->hw.init = &init;
+
+ clk = clk_register(NULL, &smd->hw);
+
+ if (IS_ERR(clk))
+ kfree(smd);
+
+ return clk;
+}
+
+#if defined(CONFIG_OF)
+static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
+{
+ struct clk *clk;
+ int i;
+ int num_parents;
+ const char *parent_names[SMD_SOURCE_MAX];
+ const char *name = np->name;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents >= SMD_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; i++) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ clk = at91sam9x5_clk_register_smd(name, parent_names, num_parents);
+
+ if (IS_ERR(clk))
+ return;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
+ of_at91sam9x5_clk_smd_setup);
+#endif
--
1.7.9.5
This is the at91 master clock implementation using common clk framework.
The pll clock layout describe the MCKR register layout.
There's four pll clock layouts:
- at91rm9200
- at91sam9x5
Master clocks are given characteristics:
- min/max clock output rate
These characteristics are checked during rate change to avoid
over/underclocking.
These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/at91/Makefile | 2 +-
drivers/clk/at91/clk-master.c | 317 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/at91.h | 23 +++
3 files changed, 341 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 564076f..d41f616 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -2,4 +2,4 @@
# Makefile for at91 specific clk
#
-obj-y += clk-main.o clk-pll.o clk-plldiv.o
+obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 0000000..71ade7d
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,317 @@
+/*
+ * drivers/clk/at91/clk-master.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * This masterram is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/at91.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+#define MASTER_SOURCE_MAX 4
+
+#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
+
+struct clk_master {
+ struct clk_hw hw;
+ struct clk_master_layout *layout;
+ struct clk_master_characteristics *characteristics;
+};
+
+static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u8 pres;
+ u8 div;
+ unsigned long rate = parent_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ u32 tmp = at91_pmc_read(AT91_PMC_MCKR) & layout->mask;
+
+ pres = (tmp >> layout->pres_shift) & 0x7;
+ div = (tmp >> 8) & 0x3;
+
+ if (characteristics->have_div3_pres && pres == 7)
+ rate /= 3;
+ else
+ rate >>= pres;
+
+ rate /= characteristics->divisors[div];
+
+ /* print overclocking or underclocking error */
+ /*
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max) {
+ }
+ */
+ return rate;
+}
+
+static long clk_master_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ long best_rate = -EINVAL;
+ unsigned long best_diff = 0;
+ unsigned long cur_diff;
+ unsigned long pres_rate;
+ unsigned long cur_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+
+ if (rate < characteristics->output.min ||
+ rate > characteristics->output.max)
+ return -EINVAL;
+
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = *parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = *parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (rate < cur_rate)
+ cur_diff = cur_rate - rate;
+ else
+ cur_diff = rate - cur_rate;
+
+ if (best_rate < 0 || cur_diff < best_diff) {
+ best_rate = cur_rate;
+ best_diff = cur_diff;
+ if (!best_diff)
+ return best_rate;
+ }
+ }
+ }
+
+ return best_rate;
+}
+
+static int clk_master_set_parent(struct clk_hw *hw, u8 index)
+{
+ u32 tmp;
+ if (index > AT91_PMC_CSS)
+ return -EINVAL;
+ tmp = at91_pmc_read(AT91_PMC_MCKR) & ~AT91_PMC_CSS;
+ tmp |= index;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+ return 0;
+}
+
+static u8 clk_master_get_parent(struct clk_hw *hw)
+{
+ return at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_CSS;
+}
+
+static int clk_master_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int mdiv;
+ int pres;
+ u32 div;
+ u32 tmp;
+ unsigned long cur_rate;
+ unsigned long pres_rate;
+ struct clk_master *master = to_clk_master(hw);
+ struct clk_master_layout *layout = master->layout;
+ struct clk_master_characteristics *characteristics =
+ master->characteristics;
+ for (pres = 0; pres < 7; pres++) {
+ if (pres < 7)
+ pres_rate = parent_rate >> pres;
+ else {
+ if (!characteristics->have_div3_pres)
+ break;
+ pres_rate = parent_rate / 3;
+ }
+ for (mdiv = 0; mdiv < 4; mdiv++) {
+ div = characteristics->divisors[mdiv];
+ if (!div)
+ continue;
+ cur_rate = pres_rate / div;
+ if (cur_rate == rate) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= layout->mask;
+ tmp &= ~AT91_PMC_CSS;
+ tmp |= pres << layout->pres_shift | mdiv << 8;
+
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+ while (!(at91_pmc_read(AT91_PMC_SR) &
+ AT91_PMC_MCKRDY))
+ ;
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct clk_ops master_ops = {
+ .recalc_rate = clk_master_recalc_rate,
+ .round_rate = clk_master_round_rate,
+ .get_parent = clk_master_get_parent,
+ .set_parent = clk_master_set_parent,
+ .set_rate = clk_master_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_master(const char *name,
+ int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics)
+{
+ struct clk_master *master;
+ struct clk *clk = NULL;
+ struct clk_init_data init;
+
+ master = kzalloc(sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &master_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+
+ master->hw.init = &init;
+ master->layout = layout;
+ master->characteristics = characteristics;
+
+ clk = clk_register(NULL, &master->hw);
+
+ if (IS_ERR(clk))
+ kfree(master);
+
+ return clk;
+}
+
+
+struct clk_master_layout at91rm9200_master_layout = {
+ .mask = 0x31F,
+ .pres_shift = 2,
+};
+
+struct clk_master_layout at91sam9x5_master_layout = {
+ .mask = 0x373,
+ .pres_shift = 4,
+};
+
+
+#if defined(CONFIG_OF)
+static struct clk_master_characteristics * __init
+of_at91_clk_master_get_characteristics(struct device_node *np)
+{
+ int i;
+ u32 tmp;
+ struct clk_master_characteristics *characteristics = NULL;
+
+ characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
+ if (!characteristics)
+ return NULL;
+
+ if (of_property_read_u32_index(np, "output", 0, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.min = tmp;
+
+ if (of_property_read_u32_index(np, "output", 1, &tmp))
+ goto out_free_characteristics;
+
+ characteristics->output.max = tmp;
+
+ for (i = 0; i < 4; i++) {
+ tmp = 0;
+ of_property_read_u32_index(np, "divisors", i, &tmp);
+ characteristics->divisors[i] = tmp;
+ }
+
+ characteristics->have_div3_pres =
+ of_property_read_bool(np, "have-div3-pres");
+
+ return characteristics;
+
+out_free_characteristics:
+ kfree(characteristics);
+ return NULL;
+}
+
+static void __init
+of_at91_clk_master_setup(struct device_node *np,
+ struct clk_master_layout *layout)
+{
+ struct clk *clk;
+ int num_parents;
+ int i;
+ const char *parent_names[MASTER_SOURCE_MAX];
+ const char *name = np->name;
+ struct clk_master_characteristics *characteristics;
+
+ num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
+ return;
+
+ for (i = 0; i < num_parents; ++i) {
+ parent_names[i] = of_clk_get_parent_name(np, i);
+ if (!parent_names[i])
+ return;
+ }
+
+ of_property_read_string(np, "clock-output-names", &name);
+
+ characteristics = of_at91_clk_master_get_characteristics(np);
+ if (!characteristics)
+ return;
+
+ clk = at91_clk_register_master(name, num_parents, parent_names,
+ layout, characteristics);
+
+ if (IS_ERR(clk))
+ goto out_free_characteristics;
+
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+
+out_free_characteristics:
+ kfree(characteristics);
+}
+
+static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91rm9200_master_layout);
+}
+CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
+ of_at91rm9200_clk_master_setup);
+
+static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
+{
+ of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
+ of_at91sam9x5_clk_master_setup);
+#endif
diff --git a/include/linux/clk/at91.h b/include/linux/clk/at91.h
index 7ba038f..a960e2f 100644
--- a/include/linux/clk/at91.h
+++ b/include/linux/clk/at91.h
@@ -210,6 +210,17 @@ struct clk_pll_layout {
u8 mul_shift;
};
+struct clk_master_characteristics {
+ struct clk_range output;
+ u32 divisors[4];
+ u8 have_div3_pres;
+};
+
+struct clk_master_layout {
+ u32 mask;
+ u8 pres_shift;
+};
+
struct clk * __init
at91_clk_register_main(const char *name,
@@ -233,4 +244,16 @@ at91_clk_register_pll(const char *name, const char *parent_name, u8 id,
struct clk * __init
at91_clk_register_plldiv(const char *name, const char *parent_name);
+
+extern struct clk_master_layout at91rm9200_master_layout;
+
+extern struct clk_master_layout at91sam9x5_master_layout;
+
+struct clk * __init
+at91_clk_register_master(const char *name, int num_parents,
+ const char **parent_names,
+ struct clk_master_layout *layout,
+ struct clk_master_characteristics *characteristics);
+
+
#endif
--
1.7.9.5
This patch removes the old at91 clk implementation, and keep the
PMC initialization and sam9idle functions in pmc.c.
The at91_initialize function no longer initiliaze at91 clks: the new clk
registration process requires kzalloc which is not available when early_init
is called.
The clk registration is moved to at91_clk_init function which should be called
before timer_init (pit timer request at91 master clock).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/clock.c | 961 ------------------------------------------
arch/arm/mach-at91/clock.h | 49 ---
arch/arm/mach-at91/generic.h | 10 +-
arch/arm/mach-at91/pmc.c | 58 +++
arch/arm/mach-at91/setup.c | 36 +-
drivers/clk/Makefile | 1 +
7 files changed, 86 insertions(+), 1031 deletions(-)
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d07bcfa..c9813f8 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m :=
obj-n :=
obj- :=
-obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
+obj-$(CONFIG_AT91_PMC_UNIT) += pmc.o
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index 191e9e4..0000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,961 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.c
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/clk/at91.h>
-
-#include <mach/hardware.h>
-#include <mach/cpu.h>
-
-#include <asm/proc-fns.h>
-
-#include "clock.h"
-#include "generic.h"
-
-void __iomem *at91_pmc_base;
-EXPORT_SYMBOL_GPL(at91_pmc_base);
-
-/*
- * There's a lot more which can be done with clocks, including cpufreq
- * integration, slow clock mode support (for system suspend), letting
- * PLLB be used at other rates (on boards that don't need USB), etc.
- */
-
-#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
-#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
-
-
-/*
- * Chips have some kind of clocks : group them by functionality
- */
-#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-#define cpu_has_1056M_plla() (cpu_is_sama5d3())
-
-#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12())
-
-#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
-
-#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
- || cpu_is_at91sam9263() \
- || cpu_is_at91sam9rl())
-
-#define cpu_has_210M_plla() (cpu_is_at91sam9260())
-
-#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12()))
-
-#define cpu_has_upll() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3())
-
-/* USB host HS & FS */
-#define cpu_has_uhp() (!cpu_is_at91sam9rl())
-
-/* USB device FS only */
-#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
- || cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_sama5d3()))
-
-#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
- || cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
- || cpu_is_at91sam9n12() \
- || cpu_is_sama5d3())
-
-static LIST_HEAD(clocks);
-static DEFINE_SPINLOCK(clk_lock);
-
-static u32 at91_pllb_usb_init;
-
-/*
- * Four primary clock sources: two crystal oscillators (32K, main), and
- * two PLLs. PLLA usually runs the master clock; and PLLB must run at
- * 48 MHz (unless no USB function clocks are needed). The main clock and
- * both PLLs are turned off to run in "slow clock mode" (system suspend).
- */
-static struct clk clk32k = {
- .name = "clk32k",
- .rate_hz = AT91_SLOW_CLOCK,
- .users = 1, /* always on */
- .id = 0,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk main_clk = {
- .name = "main",
- .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
- .id = 1,
- .type = CLK_TYPE_PRIMARY,
-};
-static struct clk plla = {
- .name = "plla",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
- .id = 2,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pllb_mode(struct clk *clk, int is_on)
-{
- u32 value;
-
- if (is_on) {
- is_on = AT91_PMC_LOCKB;
- value = at91_pllb_usb_init;
- } else
- value = 0;
-
- // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
- at91_pmc_write(AT91_CKGR_PLLBR, value);
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
-}
-
-static struct clk pllb = {
- .name = "pllb",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
- .mode = pllb_mode,
- .id = 3,
- .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
-};
-
-static void pmc_sys_mode(struct clk *clk, int is_on)
-{
- if (is_on)
- at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
-}
-
-static void pmc_uckr_mode(struct clk *clk, int is_on)
-{
- unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
-
- if (is_on) {
- is_on = AT91_PMC_LOCKU;
- at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
- } else
- at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
-
- do {
- cpu_relax();
- } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
-}
-
-/* USB function clocks (PLLB must be 48 MHz) */
-static struct clk udpck = {
- .name = "udpck",
- .parent = &pllb,
- .mode = pmc_sys_mode,
-};
-struct clk utmi_clk = {
- .name = "utmi_clk",
- .parent = &main_clk,
- .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
- .mode = pmc_uckr_mode,
- .type = CLK_TYPE_PLL,
-};
-static struct clk uhpck = {
- .name = "uhpck",
- /*.parent = ... we choose parent at runtime */
- .mode = pmc_sys_mode,
-};
-
-
-/*
- * The master clock is divided from the CPU clock (by 1-4). It's used for
- * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
- * (e.g baud rate generation). It's sourced from one of the primary clocks.
- */
-struct clk mck = {
- .name = "mck",
- .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
-};
-
-static void pmc_periph_mode(struct clk *clk, int is_on)
-{
- u32 regval = 0;
-
- /*
- * With sama5d3 devices, we are managing clock division so we have to
- * use the Peripheral Control Register introduced from at91sam9x5
- * devices.
- */
- if (cpu_is_sama5d3()) {
- regval |= AT91_PMC_PCR_CMD; /* write command */
- regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
- regval |= AT91_PMC_PCR_DIV(clk->div);
- if (is_on)
- regval |= AT91_PMC_PCR_EN; /* enable clock */
- at91_pmc_write(AT91_PMC_PCR, regval);
- } else {
- if (is_on)
- at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
- else
- at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
- }
-}
-
-static struct clk __init *at91_css_to_clk(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_CSS_SLOW:
- return &clk32k;
- case AT91_PMC_CSS_MAIN:
- return &main_clk;
- case AT91_PMC_CSS_PLLA:
- return &plla;
- case AT91_PMC_CSS_PLLB:
- if (cpu_has_upll())
- /* CSS_PLLB == CSS_UPLL */
- return &utmi_clk;
- else if (cpu_has_pllb())
- return &pllb;
- break;
- /* alternate PMC: can use master clock */
- case AT91_PMC_CSS_MASTER:
- return &mck;
- }
-
- return NULL;
-}
-
-static int pmc_prescaler_divider(u32 reg)
-{
- if (cpu_has_alt_prescaler()) {
- return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
- } else {
- return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
- }
-}
-
-static void __clk_enable(struct clk *clk)
-{
- if (clk->parent)
- __clk_enable(clk->parent);
- if (clk->users++ == 0 && clk->mode)
- clk->mode(clk, 1);
-}
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_enable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
- BUG_ON(clk->users == 0);
- if (--clk->users == 0 && clk->mode)
- clk->mode(clk, 0);
- if (clk->parent)
- __clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_disable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long flags;
- unsigned long rate;
-
- spin_lock_irqsave(&clk_lock, flags);
- for (;;) {
- rate = clk->rate_hz;
- if (rate || !clk->parent)
- break;
- clk = clk->parent;
- }
- spin_unlock_irqrestore(&clk_lock, flags);
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
-
-/*
- * For now, only the programmable clocks support reparenting (MCK could
- * do this too, with care) or rate changing (the PLLs could do this too,
- * ditto MCK but that's more for cpufreq). Drivers may reparent to get
- * a better rate match; we don't.
- */
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long actual;
- unsigned long prev = ULONG_MAX;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual > rate)
- prev = actual;
-
- if (actual && actual <= rate) {
- if ((prev - rate) < (rate - actual)) {
- actual = prev;
- prescale--;
- }
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- unsigned prescale;
- unsigned long prescale_offset, css_mask;
- unsigned long actual;
-
- if (!clk_is_programmable(clk))
- return -EINVAL;
- if (clk->users)
- return -EBUSY;
-
- if (cpu_has_alt_prescaler()) {
- prescale_offset = PMC_ALT_PRES_OFFSET;
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- } else {
- prescale_offset = PMC_PRES_OFFSET;
- css_mask = AT91_PMC_CSS;
- }
-
- spin_lock_irqsave(&clk_lock, flags);
-
- actual = clk->parent->rate_hz;
- for (prescale = 0; prescale < 7; prescale++) {
- if (actual && actual <= rate) {
- u32 pckr;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- pckr &= css_mask; /* keep clock selection */
- pckr |= prescale << prescale_offset;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
- clk->rate_hz = actual;
- break;
- }
- actual >>= 1;
- }
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return (prescale < 7) ? actual : -ENOENT;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- unsigned long flags;
-
- if (clk->users)
- return -EBUSY;
- if (!clk_is_primary(parent) || !clk_is_programmable(clk))
- return -EINVAL;
-
- if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
- return -EINVAL;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- clk->rate_hz = parent->rate_hz;
- clk->parent = parent;
- at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
-
- spin_unlock_irqrestore(&clk_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* establish PCK0..PCKN parentage and rate */
-static void __init init_programmable_clock(struct clk *clk)
-{
- struct clk *parent;
- u32 pckr;
- unsigned int css_mask;
-
- if (cpu_has_alt_prescaler())
- css_mask = AT91_PMC_ALT_PCKR_CSS;
- else
- css_mask = AT91_PMC_CSS;
-
- pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
- parent = at91_css_to_clk(pckr & css_mask);
- clk->parent = parent;
- clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
-}
-
-#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
-
-/*------------------------------------------------------------------------*/
-
-#ifdef CONFIG_DEBUG_FS
-
-static int at91_clk_show(struct seq_file *s, void *unused)
-{
- u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
- struct clk *clk;
-
- scsr = at91_pmc_read(AT91_PMC_SCSR);
- pcsr = at91_pmc_read(AT91_PMC_PCSR);
- if (cpu_is_sama5d3())
- pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
- sr = at91_pmc_read(AT91_PMC_SR);
- seq_printf(s, "SCSR = %8x\n", scsr);
- seq_printf(s, "PCSR = %8x\n", pcsr);
- if (cpu_is_sama5d3())
- seq_printf(s, "PCSR1 = %8x\n", pcsr1);
- seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
- seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
- seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_pllb())
- seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
- if (cpu_has_utmi()) {
- uckr = at91_pmc_read(AT91_CKGR_UCKR);
- seq_printf(s, "UCKR = %8x\n", uckr);
- }
- seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
- if (cpu_has_upll())
- seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
- seq_printf(s, "SR = %8x\n", sr);
-
- seq_printf(s, "\n");
-
- list_for_each_entry(clk, &clocks, node) {
- char *state;
-
- if (clk->mode == pmc_sys_mode) {
- state = (scsr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- state = (pcsr1 & pmc_mask) ? "on" : "off";
- else
- state = (pcsr & pmc_mask) ? "on" : "off";
- } else {
- state = (pcsr & clk->pmc_mask) ? "on" : "off";
- }
- } else if (clk->mode == pmc_uckr_mode) {
- state = (uckr & clk->pmc_mask) ? "on" : "off";
- } else if (clk->pmc_mask) {
- state = (sr & clk->pmc_mask) ? "on" : "off";
- } else if (clk == &clk32k || clk == &main_clk) {
- state = "on";
- } else {
- state = "";
- }
-
- seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
- clk->name, clk->users, state, clk_get_rate(clk),
- clk->parent ? clk->parent->name : "");
- }
- return 0;
-}
-
-static int at91_clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, at91_clk_show, NULL);
-}
-
-static const struct file_operations at91_clk_operations = {
- .open = at91_clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init at91_clk_debugfs_init(void)
-{
- /* /sys/kernel/debug/at91_clk */
- (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
-
- return 0;
-}
-postcore_initcall(at91_clk_debugfs_init);
-
-#endif
-
-/*------------------------------------------------------------------------*/
-
-/* Register a new clock */
-static void __init at91_clk_add(struct clk *clk)
-{
- list_add_tail(&clk->node, &clocks);
-
- clk->cl.con_id = clk->name;
- clk->cl.clk = clk;
- clkdev_add(&clk->cl);
-}
-
-int __init clk_register(struct clk *clk)
-{
- if (clk_is_peripheral(clk)) {
- if (!clk->parent)
- clk->parent = &mck;
- if (cpu_is_sama5d3())
- clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
- 1 << clk->div);
- clk->mode = pmc_periph_mode;
- }
- else if (clk_is_sys(clk)) {
- clk->parent = &mck;
- clk->mode = pmc_sys_mode;
- }
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
- else if (clk_is_programmable(clk)) {
- clk->mode = pmc_sys_mode;
- init_programmable_clock(clk);
- }
-#endif
-
- at91_clk_add(clk);
-
- return 0;
-}
-
-/*------------------------------------------------------------------------*/
-
-static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- if (cpu_is_sama5d3())
- mul = AT91_PMC3_MUL_GET(reg);
- else
- mul = AT91_PMC_MUL_GET(reg);
-
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
-{
- if (pll == &pllb && (reg & AT91_PMC_USB96M))
- return freq / 2;
- else
- return freq;
-}
-
-static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (cpu_is_at91sam9g20() && input < 2000000)
- continue;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (cpu_is_at91sam9g20() && mul > 63)
- continue;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-
-static struct clk *const standard_pmc_clocks[] __initconst = {
- /* four primary clocks */
- &clk32k,
- &main_clk,
- &plla,
-
- /* MCK */
- &mck
-};
-
-/* PLLB generated USB full speed clock init */
-static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
-{
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- uhpck.parent = &pllb;
-
- at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
- pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
- if (cpu_is_at91rm9200()) {
- uhpck.pmc_mask = AT91RM9200_PMC_UHP;
- udpck.pmc_mask = AT91RM9200_PMC_UDP;
- at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
- } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
- cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
- cpu_is_at91sam9g10()) {
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- udpck.pmc_mask = AT91SAM926x_PMC_UDP;
- }
- at91_pmc_write(AT91_CKGR_PLLBR, 0);
-
- udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
- uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-}
-
-/* UPLL generated USB full speed clock init */
-static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
-{
- /*
- * USB clock init: choose 480 MHz from UPLL,
- */
- unsigned int usbr = AT91_PMC_USBS_UPLL;
-
- /* Setup divider by 10 to reach 48 MHz */
- usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
-
- at91_pmc_write(AT91_PMC_USB, usbr);
-
- /* Now set uhpck values */
- uhpck.parent = &utmi_clk;
- uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
- uhpck.rate_hz = utmi_clk.rate_hz;
- uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
-}
-
-static int __init at91_pmc_init(unsigned long main_clock)
-{
- unsigned tmp, freq, mckr;
- int i;
- int pll_overclock = false;
-
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = at91_pmc_read(AT91_CKGR_MCFR);
- } while (!(tmp & AT91_PMC_MAINRDY));
- main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
- }
- main_clk.rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
- if (cpu_has_1056M_plla()) {
- if (plla.rate_hz > 1056000000)
- pll_overclock = true;
- } else if (cpu_has_800M_plla()) {
- if (plla.rate_hz > 800000000)
- pll_overclock = true;
- } else if (cpu_has_300M_plla()) {
- if (plla.rate_hz > 300000000)
- pll_overclock = true;
- } else if (cpu_has_240M_plla()) {
- if (plla.rate_hz > 240000000)
- pll_overclock = true;
- } else if (cpu_has_210M_plla()) {
- if (plla.rate_hz > 210000000)
- pll_overclock = true;
- } else {
- if (plla.rate_hz > 209000000)
- pll_overclock = true;
- }
- if (pll_overclock)
- pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
- if (cpu_has_plladiv2()) {
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
- }
-
- if (!cpu_has_pllb() && cpu_has_upll()) {
- /* setup UTMI clock as the fourth primary clock
- * (instead of pllb) */
- utmi_clk.type |= CLK_TYPE_PRIMARY;
- utmi_clk.id = 3;
- }
-
-
- /*
- * USB HS clock init
- */
- if (cpu_has_utmi()) {
- /*
- * multiplier is hard-wired to 40
- * (obtain the USB High Speed 480 MHz when input is 12 MHz)
- */
- utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
-
- /* UTMI bias and PLL are managed at the same time */
- if (cpu_has_upll())
- utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
- }
-
- /*
- * USB FS clock init
- */
- if (cpu_has_pllb())
- at91_pllb_usbfs_clock_init(main_clock);
- if (cpu_has_upll())
- /* assumes that we choose UPLL for USB and not PLLA */
- at91_upll_usbfs_clock_init(main_clock);
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = at91_pmc_read(AT91_PMC_MCKR);
- mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
- freq = mck.parent->rate_hz;
- freq /= pmc_prescaler_divider(mckr); /* prescale */
- if (cpu_is_at91rm9200()) {
- mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else if (cpu_is_at91sam9g20()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
- freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- if (mckr & AT91_PMC_PDIV)
- freq /= 2; /* processor clock division */
- } else if (cpu_has_mdiv3()) {
- mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
- freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- } else {
- mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
- }
-
- if (cpu_has_alt_prescaler()) {
- /* Programmable clocks can use MCK */
- mck.type |= CLK_TYPE_PRIMARY;
- mck.id = 4;
- }
-
- /* Register the PMC's standard clocks */
- for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
- at91_clk_add(standard_pmc_clocks[i]);
-
- if (cpu_has_pllb())
- at91_clk_add(&pllb);
-
- if (cpu_has_uhp())
- at91_clk_add(&uhpck);
-
- if (cpu_has_udpfs())
- at91_clk_add(&udpck);
-
- if (cpu_has_utmi())
- at91_clk_add(&utmi_clk);
-
- /* MCK and CPU clock are "always on" */
- clk_enable(&mck);
-
- printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
- freq / 1000000, (unsigned) mck.rate_hz / 1000000,
- (unsigned) main_clock / 1000000,
- ((unsigned) main_clock % 1000000) / 1000);
-
- return 0;
-}
-
-#if defined(CONFIG_OF)
-static struct of_device_id pmc_ids[] = {
- { .compatible = "atmel,at91rm9200-pmc" },
- { /*sentinel*/ }
-};
-
-static struct of_device_id osc_ids[] = {
- { .compatible = "atmel,osc" },
- { /*sentinel*/ }
-};
-
-int __init at91_dt_clock_init(void)
-{
- struct device_node *np;
- u32 main_clock = 0;
-
- np = of_find_matching_node(NULL, pmc_ids);
- if (!np)
- panic("unable to find compatible pmc node in dtb\n");
-
- at91_pmc_base = of_iomap(np, 0);
- if (!at91_pmc_base)
- panic("unable to map pmc cpu registers\n");
-
- of_node_put(np);
-
- /* retrieve the freqency of fixed clocks from device tree */
- np = of_find_matching_node(NULL, osc_ids);
- if (np) {
- u32 rate;
- if (!of_property_read_u32(np, "clock-frequency", &rate))
- main_clock = rate;
- }
-
- of_node_put(np);
-
- return at91_pmc_init(main_clock);
-}
-#endif
-
-int __init at91_clock_init(unsigned long main_clock)
-{
- at91_pmc_base = ioremap(AT91_PMC, 256);
- if (!at91_pmc_base)
- panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
- return at91_pmc_init(main_clock);
-}
-
-/*
- * Several unused clocks may be active. Turn them off.
- */
-static int __init at91_clock_reset(void)
-{
- unsigned long pcdr = 0;
- unsigned long pcdr1 = 0;
- unsigned long scdr = 0;
- struct clk *clk;
-
- list_for_each_entry(clk, &clocks, node) {
- if (clk->users > 0)
- continue;
-
- if (clk->mode == pmc_periph_mode) {
- if (cpu_is_sama5d3()) {
- u32 pmc_mask = 1 << (clk->pid % 32);
-
- if (clk->pid > 31)
- pcdr1 |= pmc_mask;
- else
- pcdr |= pmc_mask;
- } else
- pcdr |= clk->pmc_mask;
- }
-
- if (clk->mode == pmc_sys_mode)
- scdr |= clk->pmc_mask;
-
- pr_debug("Clocks: disable unused %s\n", clk->name);
- }
-
- at91_pmc_write(AT91_PMC_SCDR, scdr);
- if (cpu_is_sama5d3())
- at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
-
- return 0;
-}
-late_initcall(at91_clock_reset);
-
-void at91sam9_idle(void)
-{
- at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
- cpu_do_idle();
-}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39b..0000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/clock.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clkdev.h>
-
-#define CLK_TYPE_PRIMARY 0x1
-#define CLK_TYPE_PLL 0x2
-#define CLK_TYPE_PROGRAMMABLE 0x4
-#define CLK_TYPE_PERIPHERAL 0x8
-#define CLK_TYPE_SYSTEM 0x10
-
-
-struct clk {
- struct list_head node;
- const char *name; /* unique clock name */
- struct clk_lookup cl;
- unsigned long rate_hz;
- unsigned div; /* parent clock divider */
- struct clk *parent;
- unsigned pid; /* peripheral ID */
- u32 pmc_mask;
- void (*mode)(struct clk *, int);
- unsigned id:3; /* PCK0..4, or 32k/main/a/b */
- unsigned type; /* clock type */
- u16 users;
-};
-
-
-extern int __init clk_register(struct clk *clk);
-extern struct clk mck;
-extern struct clk utmi_clk;
-
-#define CLKDEV_CON_ID(_id, _clk) \
- { \
- .con_id = _id, \
- .clk = _clk, \
- }
-
-#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
- { \
- .con_id = _con_id, \
- .dev_id = _dev_id, \
- .clk = _clk, \
- }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab065..ecd4eb0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -18,10 +18,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
/* Processors */
extern void __init at91rm9200_set_type(int type);
-extern void __init at91_initialize(unsigned long main_clock);
+extern void __init at91_initialize(void);
+extern void __init at91_clk_init(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void);
+extern void __init at91_dt_clk_init(void);
/* Interrupts */
extern void __init at91_init_irq_default(void);
@@ -44,10 +46,10 @@ extern void at91x40_timer_init(void);
/* Clocks */
#ifdef CONFIG_AT91_PMC_UNIT
-extern int __init at91_clock_init(unsigned long main_clock);
-extern int __init at91_dt_clock_init(void);
+extern int __init at91_pmc_init(void);
+extern int __init at91_dt_pmc_init(void);
#else
-static int inline at91_clock_init(unsigned long main_clock) { return 0; }
+static int inline at91_pmc_init() { return 0; }
#endif
struct device;
diff --git a/arch/arm/mach-at91/pmc.c b/arch/arm/mach-at91/pmc.c
new file mode 100644
index 0000000..2a8a6cf
--- /dev/null
+++ b/arch/arm/mach-at91/pmc.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/mach-at91/pmc.c
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/at91.h>
+
+#include <asm/io.h>
+#include <asm/proc-fns.h>
+
+void __iomem *at91_pmc_base;
+EXPORT_SYMBOL_GPL(at91_pmc_base);
+
+void at91sam9_idle(void)
+{
+ at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+ cpu_do_idle();
+}
+
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+ { .compatible = "atmel,at91rm9200-pmc" },
+ { /*sentinel*/ }
+};
+
+int __init at91_dt_pmc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, pmc_ids);
+ if (!np)
+ panic("unable to find compatible pmc node in dtb\n");
+
+ at91_pmc_base = of_iomap(np, 0);
+ if (!at91_pmc_base)
+ panic("unable to map pmc cpu registers\n");
+
+ of_node_put(np);
+
+ return 0;
+}
+#endif
+
+int __init at91_pmc_init(void)
+{
+ at91_pmc_base = ioremap(AT91_PMC, 256);
+ if (!at91_pmc_base)
+ panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 7af1bbf..750eade 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -479,41 +479,45 @@ void __init at91rm9200_dt_initialize(void)
{
at91_dt_ramc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
at91_boot_soc.init();
}
-void __init at91_dt_initialize(void)
+void __init at91_dt_initialize()
{
at91_dt_rstc();
at91_dt_ramc();
at91_dt_shdwc();
- /* Init clock subsystem */
- at91_dt_clock_init();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
+ at91_dt_pmc_init();
if (at91_boot_soc.init)
at91_boot_soc.init();
}
-#endif
-void __init at91_initialize(unsigned long main_clock)
+void __init at91_dt_clk_init(void)
{
- at91_boot_soc.ioremap_registers();
+ of_clk_init(NULL);
+}
+#endif
- /* Init clock subsystem */
- at91_clock_init(main_clock);
+void __init at91_clk_init(unsigned long main_clock)
+{
+ clk_register_fixed_rate(NULL, "clk32k", NULL, CLK_IS_ROOT,
+ AT91_SLOW_CLOCK);
+ at91_clk_register_main("main", "clk32k", main_clock);
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();
+}
+
+void __init at91_initialize(void)
+{
+ at91_boot_soc.ioremap_registers();
+
+ /* Init clock subsystem */
+ at91_pmc_init();
at91_boot_soc.init();
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e7..b0125b2 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
+obj-$(CONFIG_ARCH_AT91) += at91/
obj-$(CONFIG_X86) += x86/
--
1.7.9.5
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9260 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9260.c | 692 +++++++++++++++++++++++++-------------
1 file changed, 457 insertions(+), 235 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index df32768..45a8169c 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -26,7 +26,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -36,255 +35,478 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart4_clk = {
- .name = "usart4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart5_clk = {
- .name = "usart5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_US5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91SAM9260_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &adc_clk,
- &adc_op_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &macb_clk,
- &isi_clk,
- &usart3_clk,
- &usart4_clk,
- &usart5_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup adc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "adc_clk", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup usart4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart4_clk", NULL),
+ CLKDEV_INIT("atmel_usart.5", "usart", NULL),
+};
+
+static struct clk_lookup usart5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart5_clk", NULL),
+ CLKDEV_INIT("atmel_usart.6", "usart", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("t0_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("t1_clk", "atmel_tcb.1", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("t2_clk", "atmel_tcb.1", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(adc_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(usart4_clk_lookup),
+ ARRAY_SIZE(usart5_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ adc_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc_clk_lookup,
+ NULL,
+ NULL,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ usart3_clk_lookup,
+ usart4_clk_lookup,
+ usart5_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "usbck",
+ "usbck",
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
};
+static struct clk_range at91sam9260_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 240000000),
+};
+static u8 at91sam9260_plla_out[] = {0, 2};
+
+static struct clk_range at91sam9260_pllb_output[] = {
+ CLK_RANGE(70000000, 130000000),
+};
+static u8 at91sam9260_pllb_out[] = {1,};
+
+struct clk_pll_characteristics at91sam9260_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9260_plla_output),
+ .output = at91sam9260_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9xe_plla_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 220000000),
+};
+
+struct clk_pll_characteristics at91sam9xe_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9xe_plla_output),
+ .output = at91sam9xe_plla_output,
+ .out = at91sam9260_plla_out,
+ },
+ {
+ .input = CLK_RANGE(1000000, 5000000),
+ .num_output = ARRAY_SIZE(at91sam9260_pllb_output),
+ .output = at91sam9260_pllb_output,
+ .out = at91sam9260_pllb_out,
+ },
+};
+
+static struct clk_range at91sam9g20_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g20_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g20_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+static struct clk_range at91sam9g20_pllb_output[] = {
+ CLK_RANGE(30000000, 100000000),
+};
+static u8 at91sam9g20_pllb_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g20_pll_characteristics[] = {
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_plla_output),
+ .output = at91sam9g20_plla_output,
+ .out = at91sam9g20_plla_out,
+ .icpll = at91sam9g20_plla_icpll,
+ },
+ {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g20_pllb_output),
+ .output = at91sam9g20_pllb_output,
+ .out = at91sam9g20_pllb_out,
+ },
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9260_master_characteristics = {
+ .output = CLK_RANGE(0, 105000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9xe_master_characteristics = {
+ .output = CLK_RANGE(0, 90000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g20_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 6},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
static void __init at91sam9260_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_pll_layout *pll_layout;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9xe()) {
+ pll_characteristics = at91sam9xe_pll_characteristics;
+ master_characteristics = &at91sam9xe_master_characteristics;
+ } else if (cpu_is_at91sam9g20()) {
+ pll_characteristics = at91sam9g20_pll_characteristics;
+ master_characteristics = &at91sam9g20_master_characteristics;
+ } else {
+ pll_characteristics = at91sam9260_pll_characteristics;
+ master_characteristics = &at91sam9260_master_characteristics;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ pll_layout = &at91rm9200_pll_layout;
+ if (cpu_is_at91sam9g20()) {
+ if (!i)
+ pll_layout = &at91sam9g45_pll_layout;
+ else
+ pll_layout = &at91sam9g20_pllb_layout;
+ }
+ clk = at91_clk_register_pll(name, "main", i, pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
+
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < 2; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 5000000);
}
/* --------------------------------------------------------------------
--
1.7.9.5
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9261 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9261.c | 579 +++++++++++++++++++++++++-------------
1 file changed, 383 insertions(+), 196 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 8a63b81..ccc2bcc 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,216 +34,404 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* HClocks */
-static struct clk hck0 = {
- .name = "hck0",
- .pmc_mask = AT91_PMC_HCK0,
- .type = CLK_TYPE_SYSTEM,
- .id = 0,
-};
-static struct clk hck1 = {
- .name = "hck1",
- .pmc_mask = AT91_PMC_HCK1,
- .type = CLK_TYPE_SYSTEM,
- .id = 1,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &ohci_clk,
- &lcdc_clk,
- // irq0 .. irq2
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9261.0", NULL, NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.2", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ ohci_clk_lookup,
+ lcdc_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static struct clk_lookup hck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck0", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup hck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "hck1", NULL),
+ CLKDEV_INIT("at91sam9261-lcdfb.0", "hclk", NULL),
+ CLKDEV_INIT("at91sam9g10-lcdfb.0", "hclk", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(hck0_clk_lookup),
+ ARRAY_SIZE(hck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ hck0_clk_lookup,
+ hck1_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "usbck",
+ "usbck",
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "mck",
+ "mck",
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9261_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9261_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9261_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9261_pll_output),
+ .output = at91sam9261_pll_output,
+ .out = at91sam9261_pll_out,
+};
+
+static struct clk_range at91sam9g10_pll_output[] = {
+ CLK_RANGE(80000000, 266000000),
+};
+static u8 at91sam9g10_pll_out[] = {0};
+
+struct clk_pll_characteristics at91sam9g10_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g10_pll_output),
+ .output = at91sam9g10_pll_output,
+ .out = at91sam9g10_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9261_master_characteristics = {
+ .output = CLK_RANGE(0, 94000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+struct clk_master_characteristics at91sam9g10_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
};
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
static void __init at91sam9261_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+ struct clk_pll_characteristics *pll_characteristics;
+ struct clk_master_characteristics *master_characteristics;
+
+ if (cpu_is_at91sam9g10()) {
+ pll_characteristics = &at91sam9g10_pll_characteristics;
+ master_characteristics = &at91sam9g10_master_characteristics;
+ } else {
+ pll_characteristics = &at91sam9261_pll_characteristics;
+ master_characteristics = &at91sam9261_master_characteristics;
+ }
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &pll_characteristics[i]);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&hck0);
- clk_register(&hck1);
+ for (i = 0; i < 4; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9rl SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9rl.c | 512 ++++++++++++++++++++++++---------------
1 file changed, 323 insertions(+), 189 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 6fbda1a..a066685 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -25,7 +25,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -35,207 +34,342 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &twi0_clk,
- &twi1_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &udphs_clk,
- &lcdc_clk,
- &ac97_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
};
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g20.1", NULL, NULL),
+};
+
+static struct clk_lookup spi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9rl-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ udphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "prog0",
+ "prog1",
+};
+
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+};
+
+static struct clk_range at91sam9rl_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9rl_pll_out[] = {0, 2,};
+
+struct clk_pll_characteristics at91sam9rl_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9rl_pll_output),
+ .output = at91sam9rl_pll_output,
+ .out = at91sam9rl_pll_out,
+};
+
+
/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
+ * The master clock.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9rl_master_characteristics = {
+ .output = CLK_RANGE(0, 100000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+static const char *master_prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
};
+
static void __init at91sam9rl_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91rm9200_pll_layout,
+ &at91sam9rl_pll_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ master_prog_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9rl_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clk_register(&pck0);
- clk_register(&pck1);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < 2; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ master_prog_clock_parent_names,
+ ARRAY_SIZE(master_prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
Dear Boris BREZILLON,
On Fri, 7 Jun 2013 16:24:10 +0200, Boris BREZILLON wrote:
> + * This mainram is free software; you can redistribute it and/or modify
Looks like you did some funky 'sed' over your source files. In every
clk driver, instead of "program" you have "<name of clock>ram" :-)
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9263 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9263.c | 597 +++++++++++++++++++++++---------------
1 file changed, 368 insertions(+), 229 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 77b3c24..b22ec26 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -24,7 +24,6 @@
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,248 +33,388 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCDE_clk = {
- .name = "pioCDE_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
- .name = "can_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_CAN,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twodge_clk = {
- .name = "2dge_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91SAM9263_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioCDE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &can_clk,
- &twi_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ac97_clk,
- &tcb_clk,
- &pwm_clk,
- &macb_clk,
- &twodge_clk,
- &udc_clk,
- &isi_clk,
- &lcdc_clk,
- &dma_clk,
- &ohci_clk,
- // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioCDE_clk),
- CLKDEV_CON_ID("pioD", &pioCDE_clk),
- CLKDEV_CON_ID("pioE", &pioCDE_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioCDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioCDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup can_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "can_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9260.0", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi1_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup tcb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup twodge_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "2dge_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("at91sam9263-lcdfb.0", "hclk", NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioCDE_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(mci1_clk_lookup),
+ ARRAY_SIZE(can_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(tcb_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ 0,
+ ARRAY_SIZE(twodge_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ 0,
+ ARRAY_SIZE(ohci_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioCDE_clk_lookup,
+ NULL,
+ NULL,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ mci0_clk_lookup,
+ mci1_clk_lookup,
+ can_clk_lookup,
+ twi_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ac97_clk_lookup,
+ tcb_clk_lookup,
+ pwm_clk_lookup,
+ macb_clk_lookup,
+ NULL,
+ twodge_clk_lookup,
+ udc_clk_lookup,
+ isi_clk_lookup,
+ lcdc_clk_lookup,
+ dma_clk_lookup,
+ NULL,
+ ohci_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ ARRAY_SIZE(udp_clk_lookup),
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ udp_clk_lookup,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "usbck",
+ "usbck",
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91sam9263_pll_output[] = {
+ CLK_RANGE(80000000, 200000000),
+ CLK_RANGE(190000000, 240000000),
+};
+static u8 at91sam9263_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91sam9263_pll_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9263_pll_output),
+ .output = at91sam9263_pll_output,
+ .out = at91sam9263_pll_out,
+};
+
+struct clk_master_characteristics at91sam9263_master_characteristics = {
+ .output = CLK_RANGE(0, 120000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 0},
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
};
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 4, 0};
+
static void __init at91sam9263_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91sam9263_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9263_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (i = 0; i < 4; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91sam9g45 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9g45.c | 703 ++++++++++++++++++------------
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
2 files changed, 427 insertions(+), 277 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 31a1304..c68c2fb 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -24,7 +24,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,297 +33,449 @@
/*
* The peripheral clocks.
*/
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioDE_clk = {
- .name = "pioDE_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk trng_clk = {
- .name = "trng_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tsc_clk = {
- .name = "tsc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
- .name = "ac97_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-/* Video decoder clock - Only for sam9m10/sam9m11 */
-static struct clk vdec_clk = {
- .name = "vdec_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 13200000,
-};
-
-/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
-static struct clk aestdessha_clk = {
- .name = "aestdessha_clk",
- .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioDE_clk,
- &trng_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc0_clk,
- &twi0_clk,
- &twi1_clk,
- &spi0_clk,
- &spi1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &tcb0_clk,
- &pwm_clk,
- &tsc_clk,
- &dma_clk,
- &uhphs_clk,
- &lcdc_clk,
- &ac97_clk,
- &macb_clk,
- &isi_clk,
- &udphs_clk,
- &mmc1_clk,
- &adc_op_clk,
- &aestdessha_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* One additional fake clock for macb_hclk */
- CLKDEV_CON_ID("hclk", &macb_clk),
- /* One additional fake clock for ohci */
- CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
- CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
- CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
- /* more usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
- /* more tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
-
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioDE_clk),
- CLKDEV_CON_ID("pioE", &pioDE_clk),
- /* Fake adc clock */
- CLKDEV_CON_ID("adc_clk", &tsc_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioDE_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioDE_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+ CLKDEV_INIT(NULL, "pioE", NULL),
+};
+
+static struct clk_lookup trng_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "trng_clk", NULL),
+ CLKDEV_INIT("atmel-trng", NULL, NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci0_clk", NULL),
+ CLKDEV_INIT("atmel_mci.0", "mci_clk", NULL),
+};
+
+static struct clk_lookup twi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi0_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.0", NULL, NULL),
+};
+
+static struct clk_lookup twi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi1_clk", NULL),
+ CLKDEV_INIT("i2c-at91sam9g10.1", NULL, NULL),
+};
+
+static struct clk_lookup spi0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.0", "spi_clk", NULL),
+};
+
+static struct clk_lookup spi1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "spi0_clk", NULL),
+ CLKDEV_INIT("atmel_spi.1", "spi_clk", NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91sam9g45_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup tcb0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tcb0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup pwm_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pwm_clk", NULL),
+};
+
+static struct clk_lookup tsc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tsc_clk", NULL),
+ CLKDEV_INIT("adc_clk", NULL, NULL),
+};
+
+static struct clk_lookup dma_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "dma_clk", NULL),
+};
+
+static struct clk_lookup uhphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhphs_clk", NULL),
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("atmel-ehci", "ehci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup lcdc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "lcdc_clk", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45-lcdfb.0", NULL),
+ CLKDEV_INIT("hclk", "at91sam9g45es-lcdfb.0", NULL),
+};
+
+static struct clk_lookup ac97_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ac97_clk", NULL),
+};
+
+static struct clk_lookup macb_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pclk", NULL),
+ CLKDEV_INIT(NULL, "hclk", NULL),
+};
+
+static struct clk_lookup isi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "isi_clk", NULL),
+};
+
+static struct clk_lookup udphs_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udphs_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "pclk", NULL),
+};
+
+static struct clk_lookup aestdessha_clk_lookup[] = {
+ CLKDEV_INIT("atmel_sha", NULL, NULL),
+ CLKDEV_INIT("atmel_tdes", NULL, NULL),
+ CLKDEV_INIT("atmel_aes", NULL, NULL),
+};
+
+static struct clk_lookup mci1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci1_clk", NULL),
+ CLKDEV_INIT("atmel_mci.1", "mci_clk", NULL),
+};
+
+static struct clk_lookup vdec_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "vdec_clk", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioDE_clk_lookup),
+ ARRAY_SIZE(trng_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci0_clk_lookup),
+ ARRAY_SIZE(twi0_clk_lookup),
+ ARRAY_SIZE(twi1_clk_lookup),
+ ARRAY_SIZE(spi0_clk_lookup),
+ ARRAY_SIZE(spi1_clk_lookup),
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(tcb0_clk_lookup),
+ ARRAY_SIZE(pwm_clk_lookup),
+ ARRAY_SIZE(tsc_clk_lookup),
+ ARRAY_SIZE(dma_clk_lookup),
+ ARRAY_SIZE(uhphs_clk_lookup),
+ ARRAY_SIZE(lcdc_clk_lookup),
+ ARRAY_SIZE(ac97_clk_lookup),
+ ARRAY_SIZE(macb_clk_lookup),
+ ARRAY_SIZE(isi_clk_lookup),
+ ARRAY_SIZE(udphs_clk_lookup),
+ 0,
+ ARRAY_SIZE(mci1_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioDE_clk_lookup,
+ trng_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci0_clk_lookup,
+ twi0_clk_lookup,
+ twi1_clk_lookup,
+ spi0_clk_lookup,
+ spi1_clk_lookup,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ tcb0_clk_lookup,
+ pwm_clk_lookup,
+ tsc_clk_lookup,
+ dma_clk_lookup,
+ uhphs_clk_lookup,
+ lcdc_clk_lookup,
+ ac97_clk_lookup,
+ macb_clk_lookup,
+ isi_clk_lookup,
+ udphs_clk_lookup,
+ NULL,
+ mci1_clk_lookup,
+};
+
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup ddr_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ddrck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(ddr_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ ddr_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ NULL,
+ "mck",
+ NULL,
+ NULL,
+ NULL,
+ "usbck",
+ NULL,
+ "prog0",
+ "prog1",
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+ "mck",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+};
+
+static struct clk_range at91sam9g45_plla_output[] = {
+ CLK_RANGE(745000000, 800000000),
+ CLK_RANGE(695000000, 750000000),
+ CLK_RANGE(645000000, 700000000),
+ CLK_RANGE(595000000, 650000000),
+ CLK_RANGE(545000000, 600000000),
+ CLK_RANGE(495000000, 550000000),
+ CLK_RANGE(445000000, 500000000),
+ CLK_RANGE(400000000, 450000000),
+};
+static u8 at91sam9g45_plla_out[] = {0, 1, 2, 3, 0, 1, 2, 3};
+static u16 at91sam9g45_plla_icpll[] = {0, 0, 0, 0, 1, 1, 1, 1};
+
+struct clk_pll_characteristics at91sam9g45_plla_characteristics = {
+ .input = CLK_RANGE(2000000, 32000000),
+ .num_output = ARRAY_SIZE(at91sam9g45_plla_output),
+ .output = at91sam9g45_plla_output,
+ .out = at91sam9g45_plla_out,
+ .icpll = at91sam9g45_plla_icpll,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91sam9g45_master_characteristics = {
+ .output = CLK_RANGE(0, 133000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 4, 3},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plladiv",
+ "utmi_clk",
+};
+
+/*
+ * UTMI clock.
+ */
+static struct clk_lookup utmi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "utmi_clk", NULL),
+ CLKDEV_INIT("atmel_usba_udc", "hclk", NULL),
};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
+
+/*
+ * USB clock.
+ */
+static const char *usb_clock_parent_names[] __initdata = {
+ "plladiv",
+ "utmi_clk",
};
static void __init at91sam9g45_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ clk = at91_clk_register_pll("plla", "main", 0,
+ &at91sam9g45_pll_layout,
+ &at91sam9g45_plla_characteristics);
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++)
+ pll_clk_lookup[i].clk = clk;
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+ clk = at91_clk_register_plldiv("plladiv", "plla");
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ clk = at91_clk_register_utmi("utmi_clk", "main");
+ for (i = 0; i < ARRAY_SIZE(utmi_clk_lookup); i++)
+ utmi_clk_lookup[i].clk = clk;
+ clkdev_add_table(utmi_clk_lookup, ARRAY_SIZE(utmi_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91sam9g45_master_characteristics);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
- clk_register(&vdec_clk);
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
+
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_VDEC);
+ for (k = 0; k < ARRAY_SIZE(vdec_clk_lookup); k++)
+ vdec_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup, ARRAY_SIZE(vdec_clk_lookup));
+ }
+
+ if (cpu_is_at91sam9m11() || cpu_is_at91sam9g46()) {
+ clk = at91_clk_register_peripheral(vdec_clk_lookup[0].con_id,
+ "mck",
+ AT91SAM9G45_ID_AESTDESSHA);
+ for (k = 0; k < ARRAY_SIZE(aestdessha_clk_lookup); k++)
+ aestdessha_clk_lookup[k].clk = clk;
+ clkdev_add_table(vdec_clk_lookup,
+ ARRAY_SIZE(aestdessha_clk_lookup));
+ }
+
+ for (i = 0; i < 2; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91sam9g45_programmable_layout);
+ }
+
+ clk = at91sam9x5_clk_register_usb("usbck", usb_clock_parent_names,
+ ARRAY_SIZE(usb_clock_parent_names),
+ 0);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
- clk_register(&pck0);
- clk_register(&pck1);
+ clk_register_fixed_rate(NULL, "adc_op_clk", "mck", 0, 13200000);
}
/* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index acb703e..3907647 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -37,7 +37,6 @@
#include "board.h"
#include "generic.h"
-#include "clock.h"
/* --------------------------------------------------------------------
--
1.7.9.5
This patch removes all references to the old at91 clks for at91sam9n12 SoC.
This SoC only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9n12.c | 194 --------------------------------------
1 file changed, 194 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index f9ff4d2..a6eed93 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -19,202 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
- .name = "tcb_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
- .name = "dma_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhp_clk = {
- .name = "uhp",
- .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udp_clk = {
- .name = "udp_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &twi0_clk,
- &twi1_clk,
- &mmc_clk,
- &spi0_clk,
- &spi1_clk,
- &lcdc_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb_clk,
- &pwm_clk,
- &adc_clk,
- &dma_clk,
- &uhp_clk,
- &udp_clk,
- &ssc_clk,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9n12_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
- clk_register(&pck0);
- clk_register(&pck1);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
@@ -230,6 +37,5 @@ void __init at91sam9n12_initialize(void)
AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io,
- .register_clocks = at91sam9n12_register_clocks,
.init = at91sam9n12_initialize,
AT91_SOC_END
--
1.7.9.5
On 07/06/2013 17:30, Thomas Petazzoni wrote:
> Dear Boris BREZILLON,
>
> On Fri, 7 Jun 2013 16:24:10 +0200, Boris BREZILLON wrote:
>
>> + * This mainram is free software; you can redistribute it and/or modify
> Looks like you did some funky 'sed' over your source files. In every
> clk driver, instead of "program" you have "<name of clock>ram" :-)
Oups.
I based all my implementations on programmable clocks and replaced every
instance
of the "prog" pattern by the clock name.
That's why "program" is replaced by "<name of clock>ram".
I'll fix it.
Thanks
>
> Thomas
Make use of common clk framework for all at91sam9 SoCs
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 7256b81..add1719 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -32,6 +32,7 @@ config HAVE_AT91_SMD
config SOC_AT91SAM9
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
--
1.7.9.5
This patch removes all references to the old at91 clks for at91sam9x5 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam9x5.c | 289 ---------------------------------------
1 file changed, 289 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 83fc6b3..583a3d5 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -19,297 +19,9 @@
#include "board.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioAB_clk = {
- .name = "pioAB_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioCD_clk = {
- .name = "pioCD_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk smd_clk = {
- .name = "smd_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* USART3 clock - Only for sam9g25/sam9x25 */
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
- .name = "pwm_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
-static struct clk macb0_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi clock - Only for sam9g25 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac1 clock - Only for sam9x25 */
-static struct clk macb1_clk = {
- .name = "pclk",
- .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc_clk = {
- .name = "ssc_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can0 clock - Only for sam9x35 */
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* can1 clock - Only for sam9x35 */
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioAB_clk,
- &pioCD_clk,
- &smd_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &spi0_clk,
- &spi1_clk,
- &uart0_clk,
- &uart1_clk,
- &tcb0_clk,
- &pwm_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &mmc1_clk,
- &ssc_clk,
- // irq0
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
- /* additional fake clock for macb_hclk */
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
-};
-
-/*
- * The two programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static void __init at91sam9x5_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25())
- clk_register(&usart3_clk);
-
- if (cpu_is_at91sam9g25()
- || cpu_is_at91sam9x25()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&macb0_clk);
-
- if (cpu_is_at91sam9g15()
- || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35())
- clk_register(&lcdc_clk);
-
- if (cpu_is_at91sam9g25())
- clk_register(&isi_clk);
-
- if (cpu_is_at91sam9x25())
- clk_register(&macb1_clk);
-
- if (cpu_is_at91sam9x25()
- || cpu_is_at91sam9x35()) {
- clk_register(&can0_clk);
- clk_register(&can1_clk);
- }
-
- clk_register(&pck0);
- clk_register(&pck1);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -324,5 +36,4 @@ static void __init at91sam9x5_map_io(void)
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
- .register_clocks = at91sam9x5_register_clocks,
AT91_SOC_END
--
1.7.9.5
Move at91 clk init from early_init to timer_init for all at91rm9200 non dt
boards.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/board-1arm.c | 12 ++++++++++--
arch/arm/mach-at91/board-carmeva.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpuat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-csb337.c | 11 +++++++----
arch/arm/mach-at91/board-csb637.c | 11 +++++++----
arch/arm/mach-at91/board-dt-rm9200.c | 9 ++++++++-
arch/arm/mach-at91/board-eb9200.c | 11 +++++++----
arch/arm/mach-at91/board-ecbat91.c | 12 ++++++++++--
arch/arm/mach-at91/board-eco920.c | 13 +++++++++++--
arch/arm/mach-at91/board-kafa.c | 12 ++++++++++--
arch/arm/mach-at91/board-kb9202.c | 12 ++++++++++--
arch/arm/mach-at91/board-picotux200.c | 11 +++++++----
arch/arm/mach-at91/board-rm9200dk.c | 11 +++++++----
arch/arm/mach-at91/board-rm9200ek.c | 11 +++++++----
arch/arm/mach-at91/board-rsi-ews.c | 12 ++++++++----
arch/arm/mach-at91/board-yl-9200.c | 12 ++++++++++--
16 files changed, 137 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632..1ccfa2d 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -46,8 +46,16 @@ static void __init onearm_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init onearm_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata onearm_eth_data = {
@@ -90,7 +98,7 @@ static void __init onearm_board_init(void)
MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
/* Maintainer: Lennert Buytenhek <[email protected]> */
- .init_time = at91rm9200_timer_init,
+ .init_time = onearm_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = onearm_init_early,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 9298305..591ff4c 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init carmeva_init_early(void)
+static void __init carmeva_timer_init(void)
{
- /* Initialize processor: 20.000 MHz crystal */
- at91_initialize(20000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(20000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata carmeva_eth_data = {
@@ -157,10 +160,10 @@ static void __init carmeva_board_init(void)
MACHINE_START(CARMEVA, "Carmeva")
/* Maintainer: Conitec Datasystems */
- .init_time = at91rm9200_timer_init,
+ .init_time = carmeva_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = carmeva_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = carmeva_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353..42b51d9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -58,8 +58,16 @@ static void __init cpuat91_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init cpuat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata cpuat91_eth_data = {
@@ -178,7 +186,7 @@ static void __init cpuat91_board_init(void)
MACHINE_START(CPUAT91, "Eukrea")
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91rm9200_timer_init,
+ .init_time = cpuat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = cpuat91_init_early,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215..b772ec2 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -44,10 +44,13 @@
#include "generic.h"
-static void __init csb337_init_early(void)
+static void __init csb337_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb337_eth_data = {
@@ -251,10 +254,10 @@ static void __init csb337_board_init(void)
MACHINE_START(CSB337, "Cogent CSB337")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb337_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb337_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb337_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf1106..4815dbe 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -41,10 +41,13 @@
#include "generic.h"
-static void __init csb637_init_early(void)
+static void __init csb637_timer_init(void)
{
/* Initialize processor: 3.6864 MHz crystal */
- at91_initialize(3686400);
+ at91_clk_init(3686400);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata csb637_eth_data = {
@@ -132,10 +135,10 @@ static void __init csb637_board_init(void)
MACHINE_START(CSB637, "Cogent CSB637")
/* Maintainer: Bill Gatliff */
- .init_time = at91rm9200_timer_init,
+ .init_time = csb637_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = csb637_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = csb637_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb662..4f3882e 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -15,6 +15,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91rm9200_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91rm9200_timer_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
{ /*sentinel*/ }
@@ -47,7 +54,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
- .init_time = at91rm9200_timer_init,
+ .init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be816..84cc538 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init eb9200_init_early(void)
+static void __init eb9200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eb9200_eth_data = {
@@ -116,10 +119,10 @@ static void __init eb9200_board_init(void)
}
MACHINE_START(ATEB9200, "Embest ATEB9200")
- .init_time = at91rm9200_timer_init,
+ .init_time = eb9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = eb9200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = eb9200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71..fc767bd 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -49,8 +49,16 @@ static void __init ecb_at91init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init ecbat91_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ecb_at91eth_data = {
@@ -181,7 +189,7 @@ static void __init ecb_at91board_init(void)
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
- .init_time = at91rm9200_timer_init,
+ .init_time = ecbat91_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ecb_at91init_early,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410..b910c41 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -37,7 +37,16 @@ static void __init eco920_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
- at91_initialize(18432000);
+ at91_initialize();
+}
+
+static void __init eco920_timer_init(void)
+{
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata eco920_eth_data = {
@@ -149,7 +158,7 @@ static void __init eco920_board_init(void)
MACHINE_START(ECO920, "eco920")
/* Maintainer: Sascha Hauer */
- .init_time = at91rm9200_timer_init,
+ .init_time = eco920_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = eco920_init_early,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d..e7378c4 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -46,8 +46,16 @@ static void __init kafa_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kafa_eth_data = {
@@ -103,7 +111,7 @@ static void __init kafa_board_init(void)
MACHINE_START(KAFA, "Sperry-Sun KAFA")
/* Maintainer: Sergei Sharonov */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kafa_init_early,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9..58f2069 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -49,8 +49,16 @@ static void __init kb9202_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init kafa_timer_init(void)
+{
/* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ at91_clk_init(10000000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata kb9202_eth_data = {
@@ -149,7 +157,7 @@ static void __init kb9202_board_init(void)
MACHINE_START(KB9200, "KB920x")
/* Maintainer: KwikByte, Inc. */
- .init_time = at91rm9200_timer_init,
+ .init_time = kafa_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kb9202_init_early,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec..8855fad 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init picotux200_init_early(void)
+static void __init picotux200_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata picotux200_eth_data = {
@@ -119,10 +122,10 @@ static void __init picotux200_board_init(void)
MACHINE_START(PICOTUX2XX, "picotux 200")
/* Maintainer: Kleinhenz Elektronik GmbH */
- .init_time = at91rm9200_timer_init,
+ .init_time = picotux200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = picotux200_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = picotux200_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 690541b..1a0c830 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -47,10 +47,13 @@
#include "generic.h"
-static void __init dk_init_early(void)
+static void __init dk_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata dk_eth_data = {
@@ -219,10 +222,10 @@ static void __init dk_board_init(void)
MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
/* Maintainer: SAN People/Atmel */
- .init_time = at91rm9200_timer_init,
+ .init_time = dk_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = dk_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = dk_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dad..5d3abac 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -47,10 +47,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
static struct macb_platform_data __initdata ek_eth_data = {
@@ -186,10 +189,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
/* Maintainer: SAN People/Atmel */
- .init_time = at91rm9200_timer_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f19..31738f9 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -32,10 +32,14 @@
#include "board.h"
#include "generic.h"
-static void __init rsi_ews_init_early(void)
+
+static void __init rsi_ews_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -222,10 +226,10 @@ static void __init rsi_ews_board_init(void)
MACHINE_START(RSI_EWS, "RSI EWS")
/* Maintainer: Josef Holzmayr <[email protected]> */
- .init_time = at91rm9200_timer_init,
+ .init_time = rsi_ews_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = rsi_ews_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = rsi_ews_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be08377..78a0780 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -57,8 +57,16 @@ static void __init yl9200_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+ at91_initialize();
+}
+
+static void __init yl9200_timer_init(void)
+{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init rm9200 timer */
+ at91rm9200_timer_init();
}
/*
@@ -587,7 +595,7 @@ static void __init yl9200_board_init(void)
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles */
- .init_time = at91rm9200_timer_init,
+ .init_time = yl9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = yl9200_init_early,
--
1.7.9.5
This patch removes all references to the old at91 clks for sama5d3 SoCs.
These SoCs only supports dt boards: we can remove register_clocks
(all clocks are defined in dt).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/sama5d3.c | 342 ------------------------------------------
2 files changed, 1 insertion(+), 342 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index add1719..a2f57d2 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -41,6 +41,7 @@ config SOC_AT91SAM9
config SOC_SAMA5
bool
+ select COMMON_CLK
select AT91_SAM9_TIME
select CPU_V7
select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 32e0522..5e53be8 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -19,350 +19,9 @@
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
- * Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pid = SAMA5D3_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pid = SAMA5D3_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pid = SAMA5D3_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pid = SAMA5D3_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioE_clk = {
- .name = "pioE_clk",
- .pid = SAMA5D3_ID_PIOE,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pid = SAMA5D3_ID_USART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pid = SAMA5D3_ID_USART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pid = SAMA5D3_ID_USART2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pid = SAMA5D3_ID_USART3,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart0_clk = {
- .name = "uart0_clk",
- .pid = SAMA5D3_ID_UART0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk uart1_clk = {
- .name = "uart1_clk",
- .pid = SAMA5D3_ID_UART1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi0_clk = {
- .name = "twi0_clk",
- .pid = SAMA5D3_ID_TWI0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi1_clk = {
- .name = "twi1_clk",
- .pid = SAMA5D3_ID_TWI1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk twi2_clk = {
- .name = "twi2_clk",
- .pid = SAMA5D3_ID_TWI2,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk mmc0_clk = {
- .name = "mci0_clk",
- .pid = SAMA5D3_ID_HSMCI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
- .name = "mci1_clk",
- .pid = SAMA5D3_ID_HSMCI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc2_clk = {
- .name = "mci2_clk",
- .pid = SAMA5D3_ID_HSMCI2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
- .name = "spi0_clk",
- .pid = SAMA5D3_ID_SPI0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
- .name = "spi1_clk",
- .pid = SAMA5D3_ID_SPI1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb0_clk = {
- .name = "tcb0_clk",
- .pid = SAMA5D3_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk tcb1_clk = {
- .name = "tcb1_clk",
- .pid = SAMA5D3_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_clk = {
- .name = "adc_clk",
- .pid = SAMA5D3_ID_ADC,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk adc_op_clk = {
- .name = "adc_op_clk",
- .type = CLK_TYPE_PERIPHERAL,
- .rate_hz = 5000000,
-};
-static struct clk dma0_clk = {
- .name = "dma0_clk",
- .pid = SAMA5D3_ID_DMA0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma1_clk = {
- .name = "dma1_clk",
- .pid = SAMA5D3_ID_DMA1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk uhphs_clk = {
- .name = "uhphs",
- .pid = SAMA5D3_ID_UHPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
- .name = "udphs_clk",
- .pid = SAMA5D3_ID_UDPHS,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* gmac only for sama5d33, sama5d34, sama5d35 */
-static struct clk macb0_clk = {
- .name = "macb0_clk",
- .pid = SAMA5D3_ID_GMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* emac only for sama5d31, sama5d35 */
-static struct clk macb1_clk = {
- .name = "macb1_clk",
- .pid = SAMA5D3_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* lcd only for sama5d31, sama5d33, sama5d34 */
-static struct clk lcdc_clk = {
- .name = "lcdc_clk",
- .pid = SAMA5D3_ID_LCDC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-/* isi only for sama5d33, sama5d35 */
-static struct clk isi_clk = {
- .name = "isi_clk",
- .pid = SAMA5D3_ID_ISI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can0_clk = {
- .name = "can0_clk",
- .pid = SAMA5D3_ID_CAN0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk can1_clk = {
- .name = "can1_clk",
- .pid = SAMA5D3_ID_CAN1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pid = SAMA5D3_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pid = SAMA5D3_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV2,
-};
-static struct clk sha_clk = {
- .name = "sha_clk",
- .pid = SAMA5D3_ID_SHA,
- .type = CLK_TYPE_PERIPHERAL,
- .div = AT91_PMC_PCR_DIV8,
-};
-static struct clk aes_clk = {
- .name = "aes_clk",
- .pid = SAMA5D3_ID_AES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tdes_clk = {
- .name = "tdes_clk",
- .pid = SAMA5D3_ID_TDES,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &pioE_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &uart0_clk,
- &uart1_clk,
- &twi0_clk,
- &twi1_clk,
- &twi2_clk,
- &mmc0_clk,
- &mmc1_clk,
- &mmc2_clk,
- &spi0_clk,
- &spi1_clk,
- &tcb0_clk,
- &tcb1_clk,
- &adc_clk,
- &adc_op_clk,
- &dma0_clk,
- &dma1_clk,
- &uhphs_clk,
- &udphs_clk,
- &macb0_clk,
- &macb1_clk,
- &lcdc_clk,
- &isi_clk,
- &can0_clk,
- &can1_clk,
- &ssc0_clk,
- &ssc1_clk,
- &sha_clk,
- &aes_clk,
- &tdes_clk,
-};
-
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- /* lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
- CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
- CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
- CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
- CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
- CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
- CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
- CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
- CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
- CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
- CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
- CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
- CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
- CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
- CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
- CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
- CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
-};
-
-static void __init sama5d3_register_clocks(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
-
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
-
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
-}
-
-/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -373,5 +32,4 @@ static void __init sama5d3_map_io(void)
AT91_SOC_START(sama5d3)
.map_io = sama5d3_map_io,
- .register_clocks = sama5d3_register_clocks,
AT91_SOC_END
--
1.7.9.5
Move at91 clk init from early_init to timer_init for all at91sam9 non dt
boards.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/board-afeb-9260v1.c | 11 +++++++----
arch/arm/mach-at91/board-cam60.c | 13 ++++++++-----
arch/arm/mach-at91/board-cpu9krea.c | 12 ++++++++----
arch/arm/mach-at91/board-dt-sam9.c | 9 ++++++++-
arch/arm/mach-at91/board-dt-sama5.c | 9 ++++++++-
arch/arm/mach-at91/board-flexibity.c | 12 ++++++++----
arch/arm/mach-at91/board-foxg20.c | 12 +++++++-----
arch/arm/mach-at91/board-gsia18s.c | 8 ++------
arch/arm/mach-at91/board-pcontrol-g20.c | 9 ++-------
arch/arm/mach-at91/board-qil-a9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9-l9260.c | 11 +++++++----
arch/arm/mach-at91/board-sam9260ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9261ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9263ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9g20ek.c | 15 +++++++++------
arch/arm/mach-at91/board-sam9m10g45ek.c | 11 +++++++----
arch/arm/mach-at91/board-sam9rlek.c | 11 +++++++----
arch/arm/mach-at91/board-snapper9260.c | 12 ++++++++----
arch/arm/mach-at91/board-stamp9g20.c | 15 +++++++++------
arch/arm/mach-at91/stamp9g20.h | 2 +-
20 files changed, 136 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31c..c6849e1 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -48,10 +48,13 @@
#include "generic.h"
-static void __init afeb9260_init_early(void)
+static void __init afeb9260_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -210,10 +213,10 @@ static void __init afeb9260_board_init(void)
MACHINE_START(AFEB9260, "Custom afeb9260 board")
/* Maintainer: Sergey Lapin <[email protected]> */
- .init_time = at91sam926x_pit_init,
+ .init_time = afeb9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = afeb9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = afeb9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index ade948b..75c89a0 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -46,10 +46,13 @@
#include "generic.h"
-static void __init cam60_init_early(void)
+static void __init cam60_timer_init(void)
{
- /* Initialize processor: 10 MHz crystal */
- at91_initialize(10000000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(10000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -187,10 +190,10 @@ static void __init cam60_board_init(void)
MACHINE_START(CAM60, "KwikByte CAM60")
/* Maintainer: KwikByte */
- .init_time = at91sam926x_pit_init,
+ .init_time = cam60_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cam60_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cam60_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527e..a88d8ec 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -49,10 +49,14 @@
#include "sam9_smc.h"
#include "generic.h"
-static void __init cpu9krea_init_early(void)
+
+static void __init cpu9krea_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -374,10 +378,10 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
#endif
/* Maintainer: Eric Benard - EUKREA Electromatique */
- .init_time = at91sam926x_pit_init,
+ .init_time = cpu9krea_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = cpu9krea_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = cpu9krea_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db3013..a7ea21f 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -26,6 +27,12 @@
#include "generic.h"
+static void __init at91sam_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -49,7 +56,7 @@ static const char *at91_dt_board_compat[] __initdata = {
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sam_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e..51bfd85 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
+#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
@@ -27,6 +28,12 @@
#include "generic.h"
+static void __init at91sama5_dt_timer_init(void)
+{
+ of_clk_init(NULL);
+ at91sam926x_pit_init();
+}
+
static const struct of_device_id irq_of_match[] __initconst = {
{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
@@ -76,7 +83,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = at91sama5_dt_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic5_handle_irq,
.init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c085..f64b47a 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -38,10 +38,14 @@
#include "board.h"
#include "generic.h"
-static void __init flexibity_init_early(void)
+
+static void __init flexibity_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/* USB Host port */
@@ -159,10 +163,10 @@ static void __init flexibity_board_init(void)
MACHINE_START(FLEXIBITY, "Flexibity Connect")
/* Maintainer: Maxim Osipov */
- .init_time = at91sam926x_pit_init,
+ .init_time = flexibity_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = flexibity_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = flexibity_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870..c4caeb3 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -57,11 +57,13 @@
* For more info visit: http://www.acmesystems.it/foxg20
*/
-
-static void __init foxg20_init_early(void)
+static void __init foxg20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -262,10 +264,10 @@ static void __init foxg20_board_init(void)
MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
/* Maintainer: Sergio Tanzilli */
- .init_time = at91sam926x_pit_init,
+ .init_time = foxg20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = foxg20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = foxg20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index c1d61d2..4ed7ef4 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -39,10 +39,6 @@
#include "gsia18s.h"
#include "stamp9g20.h"
-static void __init gsia18s_init_early(void)
-{
- stamp9g20_init_early();
-}
/*
* Two USB Host ports
@@ -574,10 +570,10 @@ static void __init gsia18s_board_init(void)
}
MACHINE_START(GSIA18S, "GS_IA18_S")
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = gsia18s_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = gsia18s_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 65c0d6b..6602e14 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -38,11 +38,6 @@
#include "stamp9g20.h"
-static void __init pcontrol_g20_init_early(void)
-{
- stamp9g20_init_early();
-}
-
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.ncs_read_setup = 16,
.nrd_setup = 18,
@@ -217,10 +212,10 @@ static void __init pcontrol_g20_board_init(void)
MACHINE_START(PCONTROL_G20, "PControl G20")
/* Maintainer: [email protected] */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = pcontrol_g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = pcontrol_g20_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index aa3bc9b..b7a9976 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -49,10 +49,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -257,10 +260,10 @@ static void __init ek_board_init(void)
MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
/* Maintainer: calao-systems */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc..f078f94 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -45,10 +45,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -218,10 +221,10 @@ static void __init ek_board_init(void)
MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
/* Maintainer: Olimex */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 0b153c8..2737a5c 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -51,10 +51,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -343,10 +346,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index d343762..e66237b 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -55,10 +55,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -602,20 +605,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 3284df0..c7d7682 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -54,10 +54,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 16.367 MHz crystal */
- at91_initialize(16367660);
+ at91_clk_init(16367660);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -443,10 +446,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2..10abb59 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -64,10 +64,13 @@ static int inline ek_have_2mmc(void)
}
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -409,20 +412,20 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 2a94896..6493006 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -52,10 +52,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -502,10 +505,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index aa265dc..eeea1575 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -40,10 +40,13 @@
#include "generic.h"
-static void __init ek_init_early(void)
+static void __init ek_timer_init(void)
{
/* Initialize processor: 12.000 MHz crystal */
- at91_initialize(12000000);
+ at91_clk_init(12000000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -320,10 +323,10 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
/* Maintainer: Atmel */
- .init_time = at91sam926x_pit_init,
+ .init_time = ek_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = ek_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa978..afe48fd 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -41,9 +41,13 @@
#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
-static void __init snapper9260_init_early(void)
+static void __init snapper9260_timer_init(void)
{
- at91_initialize(18432000);
+ /* Initialize processor: 18.432 MHz crystal */
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
@@ -177,10 +181,10 @@ static void __init snapper9260_board_init(void)
}
MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
- .init_time = at91sam926x_pit_init,
+ .init_time = snapper9260_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = snapper9260_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = snapper9260_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 869cbec..e4cee53 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -33,10 +33,13 @@
#include "generic.h"
-void __init stamp9g20_init_early(void)
+void __init stamp9g20_timer_init(void)
{
/* Initialize processor: 18.432 MHz crystal */
- at91_initialize(18432000);
+ at91_clk_init(18432000);
+
+ /* Init sam9 PIT timer */
+ at91sam926x_pit_init();
}
/*
@@ -273,20 +276,20 @@ static void __init stamp9g20evb_board_init(void)
MACHINE_START(PORTUXG20, "taskit PortuxG20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = portuxg20_board_init,
MACHINE_END
MACHINE_START(STAMP9G20, "taskit Stamp9G20")
/* Maintainer: taskit GmbH */
- .init_time = at91sam926x_pit_init,
+ .init_time = stamp9g20_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
- .init_early = stamp9g20_init_early,
+ .init_early = at91_initialize,
.init_irq = at91_init_irq_default,
.init_machine = stamp9g20evb_board_init,
MACHINE_END
diff --git a/arch/arm/mach-at91/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
index f62c0ab..26a37b5 100644
--- a/arch/arm/mach-at91/stamp9g20.h
+++ b/arch/arm/mach-at91/stamp9g20.h
@@ -1,7 +1,7 @@
#ifndef __MACH_STAMP9G20_H
#define __MACH_STAMP9G20_H
-void stamp9g20_init_early(void);
+void stamp9g20_timer_init(void);
void stamp9g20_board_init(void);
#endif
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clocksource/tcb_clksrc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 8a61872..229c019 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -100,7 +100,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
- clk_disable(tcd->clk);
+ clk_disable_unprepare(tcd->clk);
}
switch (m) {
@@ -109,7 +109,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
* of oneshot, we get lower overhead and improved accuracy.
*/
case CLOCK_EVT_MODE_PERIODIC:
- clk_enable(tcd->clk);
+ clk_prepare_enable(tcd->clk);
/* slow clock, count up to RC, then irq and restart */
__raw_writel(timer_clock
@@ -126,7 +126,7 @@ static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
break;
case CLOCK_EVT_MODE_ONESHOT:
- clk_enable(tcd->clk);
+ clk_prepare_enable(tcd->clk);
/* slow clock, count up to RC, then irq and stop */
__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
@@ -275,7 +275,7 @@ static int __init tcb_clksrc_init(void)
pdev = tc->pdev;
t0_clk = tc->clk[0];
- clk_enable(t0_clk);
+ clk_prepare_enable(t0_clk);
/* How fast will we be counting? Pick something over 5 MHz. */
rate = (u32) clk_get_rate(t0_clk);
@@ -313,7 +313,7 @@ static int __init tcb_clksrc_init(void)
/* tclib will give us three clocks no matter what the
* underlying platform supports.
*/
- clk_enable(tc->clk[1]);
+ clk_prepare_enable(tc->clk[1]);
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(tc, best_divisor_idx);
}
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/dma/at_hdmac.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index e923cda..4772036 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1374,7 +1374,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
err = PTR_ERR(atdma->clk);
goto err_clk;
}
- clk_enable(atdma->clk);
+ clk_prepare_enable(atdma->clk);
/* force dma off, just in case */
at_dma_off(atdma);
@@ -1475,7 +1475,7 @@ err_pool_create:
platform_set_drvdata(pdev, NULL);
free_irq(platform_get_irq(pdev, 0), atdma);
err_irq:
- clk_disable(atdma->clk);
+ clk_disable_unprepare(atdma->clk);
clk_put(atdma->clk);
err_clk:
iounmap(atdma->regs);
@@ -1512,7 +1512,7 @@ static int at_dma_remove(struct platform_device *pdev)
list_del(&chan->device_node);
}
- clk_disable(atdma->clk);
+ clk_disable_unprepare(atdma->clk);
clk_put(atdma->clk);
iounmap(atdma->regs);
@@ -1531,7 +1531,7 @@ static void at_dma_shutdown(struct platform_device *pdev)
struct at_dma *atdma = platform_get_drvdata(pdev);
at_dma_off(platform_get_drvdata(pdev));
- clk_disable(atdma->clk);
+ clk_disable_unprepare(atdma->clk);
}
static int at_dma_prepare(struct device *dev)
@@ -1588,7 +1588,7 @@ static int at_dma_suspend_noirq(struct device *dev)
/* disable DMA controller */
at_dma_off(atdma);
- clk_disable(atdma->clk);
+ clk_disable_unprepare(atdma->clk);
return 0;
}
@@ -1618,7 +1618,7 @@ static int at_dma_resume_noirq(struct device *dev)
struct dma_chan *chan, *_chan;
/* bring back DMA controller */
- clk_enable(atdma->clk);
+ clk_prepare_enable(atdma->clk);
dma_writel(atdma, EN, AT_DMA_ENABLE);
/* clear any pending interrupt */
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/mmc/host/atmel-mci.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e75774f..99c2fcc 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -380,6 +380,8 @@ static int atmci_regs_show(struct seq_file *s, void *v)
{
struct atmel_mci *host = s->private;
u32 *buf;
+ int ret;
+
buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
if (!buf)
@@ -391,7 +393,11 @@ static int atmci_regs_show(struct seq_file *s, void *v)
* consistent.
*/
spin_lock_bh(&host->lock);
- clk_enable(host->mck);
+ ret = clk_enable(host->mck);
+ if (ret) {
+ kfree(buf);
+ return ret;
+ }
memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
clk_disable(host->mck);
spin_unlock_bh(&host->lock);
@@ -2379,7 +2385,9 @@ static int __init atmci_probe(struct platform_device *pdev)
if (!host->regs)
goto err_ioremap;
- clk_enable(host->mck);
+ ret = clk_prepare_enable(host->mck);
+ if (ret)
+ goto err_clk_prepare_enable;
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
host->bus_hz = clk_get_rate(host->mck);
clk_disable(host->mck);
@@ -2463,6 +2471,8 @@ err_init_slot:
dma_release_channel(host->dma.chan);
free_irq(irq, host);
err_request_irq:
+ clk_unprepare(host->mck);
+err_clk_prepare_enable:
iounmap(host->regs);
err_ioremap:
clk_put(host->mck);
@@ -2491,7 +2501,7 @@ static int __exit atmci_remove(struct platform_device *pdev)
atmci_writel(host, ATMCI_IDR, ~0UL);
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
atmci_readl(host, ATMCI_SR);
- clk_disable(host->mck);
+ clk_disable_unprepare(host->mck);
if (host->dma.chan)
dma_release_channel(host->dma.chan);
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pwm/pwm-atmel-tcb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index 0a7b658..09be626 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -76,7 +76,7 @@ static int atmel_tcb_pwm_request(struct pwm_chip *chip,
if (!tcbpwm)
return -ENOMEM;
- ret = clk_enable(tc->clk[group]);
+ ret = clk_prepare_enable(tc->clk[group]);
if (ret) {
devm_kfree(chip->dev, tcbpwm);
return ret;
@@ -124,7 +124,7 @@ static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
struct atmel_tc *tc = tcbpwmc->tc;
- clk_disable(tc->clk[pwm->hwpwm / 2]);
+ clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]);
tcbpwmc->pwms[pwm->hwpwm] = NULL;
devm_kfree(chip->dev, tcbpwm);
}
--
1.7.9.5
This patch removes all references to the old at91 clks implementation and
make use of the new at91 clk implem for at91rm9200 SoC.
All dt specific lookups are removed (handled in clk device tree binding).
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/Kconfig | 1 +
arch/arm/mach-at91/at91rm9200.c | 576 ++++++++++++++++++++++++---------------
2 files changed, 351 insertions(+), 226 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 8032871..7256b81 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -85,6 +85,7 @@ endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
+ select COMMON_CLK
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 6ea6de7..77430ca 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/clk/at91.h>
+#include <linux/clkdev.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@@ -24,7 +25,6 @@
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
-#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
@@ -34,245 +34,369 @@
/*
* The peripheral clocks.
*/
-static struct clk udc_clk = {
- .name = "udc_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UDP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
- .name = "ohci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_UHP,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ether_clk = {
- .name = "ether_clk",
- .pmc_mask = 1 << AT91RM9200_ID_EMAC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
- .name = "mci_clk",
- .pmc_mask = 1 << AT91RM9200_ID_MCI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
- .name = "twi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TWI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
- .name = "usart0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
- .name = "usart1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
- .name = "usart2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart3_clk = {
- .name = "usart3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_US3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi_clk = {
- .name = "spi_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SPI,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioA_clk = {
- .name = "pioA_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOA,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
- .name = "pioB_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOB,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
- .name = "pioC_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOC,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioD_clk = {
- .name = "pioD_clk",
- .pmc_mask = 1 << AT91RM9200_ID_PIOD,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
- .name = "ssc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
- .name = "ssc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
- .name = "ssc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_SSC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
- .name = "tc0_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC0,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
- .name = "tc1_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC1,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
- .name = "tc2_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC2,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc3_clk = {
- .name = "tc3_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC3,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc4_clk = {
- .name = "tc4_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC4,
- .type = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc5_clk = {
- .name = "tc5_clk",
- .pmc_mask = 1 << AT91RM9200_ID_TC5,
- .type = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
- &pioA_clk,
- &pioB_clk,
- &pioC_clk,
- &pioD_clk,
- &usart0_clk,
- &usart1_clk,
- &usart2_clk,
- &usart3_clk,
- &mmc_clk,
- &udc_clk,
- &twi_clk,
- &spi_clk,
- &ssc0_clk,
- &ssc1_clk,
- &ssc2_clk,
- &tc0_clk,
- &tc1_clk,
- &tc2_clk,
- &tc3_clk,
- &tc4_clk,
- &tc5_clk,
- &ohci_clk,
- ðer_clk,
- // irq0 .. irq6
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
- CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
- /* fake hclk clock */
- CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
- CLKDEV_CON_ID("pioA", &pioA_clk),
- CLKDEV_CON_ID("pioB", &pioB_clk),
- CLKDEV_CON_ID("pioC", &pioC_clk),
- CLKDEV_CON_ID("pioD", &pioD_clk),
- /* usart lookup table for DT entries */
- CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
- CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
- /* tc lookup table for DT entries */
- CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
- CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
- CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
- CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
- CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
- CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
- CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
- CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
- CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+static struct clk_lookup pioA_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioA_clk", NULL),
+ CLKDEV_INIT(NULL, "pioA", NULL),
+};
+
+static struct clk_lookup pioB_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioB_clk", NULL),
+ CLKDEV_INIT(NULL, "pioB", NULL),
+};
+
+static struct clk_lookup pioC_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioC_clk", NULL),
+ CLKDEV_INIT(NULL, "pioC", NULL),
+};
+
+static struct clk_lookup pioD_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pioD_clk", NULL),
+ CLKDEV_INIT(NULL, "pioD", NULL),
+};
+
+static struct clk_lookup usart0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart0_clk", NULL),
+ CLKDEV_INIT("atmel_usart.1", "usart", NULL),
+};
+
+static struct clk_lookup usart1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart1_clk", NULL),
+ CLKDEV_INIT("atmel_usart.2", "usart", NULL),
+};
+
+static struct clk_lookup usart2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart2_clk", NULL),
+ CLKDEV_INIT("atmel_usart.3", "usart", NULL),
+};
+
+static struct clk_lookup usart3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "usart3_clk", NULL),
+ CLKDEV_INIT("atmel_usart.4", "usart", NULL),
+};
+
+static struct clk_lookup mci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mci_clk", NULL),
+};
+
+static struct clk_lookup udc_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udc_clk", NULL),
+};
+
+static struct clk_lookup twi_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "twi_clk", NULL),
+ CLKDEV_INIT("i2c-at91rm9200.0", NULL, NULL),
+};
+
+static struct clk_lookup ssc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc0_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.0", "pclk", NULL),
+};
+
+static struct clk_lookup ssc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc1_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.1", "pclk", NULL),
+};
+
+static struct clk_lookup ssc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ssc2_clk", NULL),
+ CLKDEV_INIT("at91rm9200_ssc.2", "pclk", NULL),
+};
+
+static struct clk_lookup tc0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc0_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc1_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc2_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.0", "t2_clk", NULL),
+};
+
+static struct clk_lookup tc3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc3_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t0_clk", NULL),
+};
+
+static struct clk_lookup tc4_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc4_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t1_clk", NULL),
+};
+
+static struct clk_lookup tc5_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "tc5_clk", NULL),
+ CLKDEV_INIT("atmel_tcb.1", "t2_clk", NULL),
+};
+
+static struct clk_lookup ohci_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ohci_clk", NULL),
+ CLKDEV_INIT("at91_ohci", "hclk", NULL),
+};
+
+static struct clk_lookup ether_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "ether_clk", NULL),
+ CLKDEV_INIT("emac_clk", "fffbc000.ethernet", NULL),
+};
+
+static size_t periph_clock_lookup_sizes[] __initdata = {
+ 0,
+ 0,
+ ARRAY_SIZE(pioA_clk_lookup),
+ ARRAY_SIZE(pioB_clk_lookup),
+ ARRAY_SIZE(pioC_clk_lookup),
+ ARRAY_SIZE(pioD_clk_lookup),
+ ARRAY_SIZE(usart0_clk_lookup),
+ ARRAY_SIZE(usart1_clk_lookup),
+ ARRAY_SIZE(usart2_clk_lookup),
+ ARRAY_SIZE(usart3_clk_lookup),
+ ARRAY_SIZE(mci_clk_lookup),
+ ARRAY_SIZE(udc_clk_lookup),
+ ARRAY_SIZE(twi_clk_lookup),
+ 0,
+ ARRAY_SIZE(ssc0_clk_lookup),
+ ARRAY_SIZE(ssc1_clk_lookup),
+ ARRAY_SIZE(ssc2_clk_lookup),
+ ARRAY_SIZE(tc0_clk_lookup),
+ ARRAY_SIZE(tc1_clk_lookup),
+ ARRAY_SIZE(tc2_clk_lookup),
+ ARRAY_SIZE(tc3_clk_lookup),
+ ARRAY_SIZE(tc4_clk_lookup),
+ ARRAY_SIZE(tc5_clk_lookup),
+ ARRAY_SIZE(ohci_clk_lookup),
+ ARRAY_SIZE(ether_clk_lookup),
+};
+
+static struct clk_lookup *periph_clock_lookups[] __initdata = {
+ NULL,
+ NULL,
+ pioA_clk_lookup,
+ pioB_clk_lookup,
+ pioC_clk_lookup,
+ pioD_clk_lookup,
+ usart0_clk_lookup,
+ usart1_clk_lookup,
+ usart2_clk_lookup,
+ usart3_clk_lookup,
+ mci_clk_lookup,
+ udc_clk_lookup,
+ twi_clk_lookup,
+ NULL,
+ ssc0_clk_lookup,
+ ssc1_clk_lookup,
+ ssc2_clk_lookup,
+ tc0_clk_lookup,
+ tc1_clk_lookup,
+ tc2_clk_lookup,
+ tc3_clk_lookup,
+ tc4_clk_lookup,
+ tc5_clk_lookup,
+ ohci_clk_lookup,
+ ether_clk_lookup,
+};
+
+/*
+ * The system clocks.
+ */
+static struct clk_lookup udp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "udpck", NULL),
+};
+
+static struct clk_lookup uhp_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "uhpck", NULL),
+};
+
+static struct clk_lookup pck0_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck0", NULL),
+};
+
+static struct clk_lookup pck1_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck1", NULL),
+};
+
+static struct clk_lookup pck2_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck2", NULL),
+};
+
+static struct clk_lookup pck3_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "pck3", NULL),
+};
+
+static size_t system_clock_lookup_sizes[] __initdata = {
+ 0,
+ ARRAY_SIZE(udp_clk_lookup),
+ 0,
+ 0,
+ ARRAY_SIZE(uhp_clk_lookup),
+ 0,
+ 0,
+ 0,
+ ARRAY_SIZE(pck0_clk_lookup),
+ ARRAY_SIZE(pck1_clk_lookup),
+ ARRAY_SIZE(pck2_clk_lookup),
+ ARRAY_SIZE(pck3_clk_lookup),
+};
+
+static struct clk_lookup *system_clock_lookups[] __initdata = {
+ NULL,
+ udp_clk_lookup,
+ NULL,
+ NULL,
+ uhp_clk_lookup,
+ NULL,
+ NULL,
+ NULL,
+ pck0_clk_lookup,
+ pck1_clk_lookup,
+ pck2_clk_lookup,
+ pck3_clk_lookup,
+};
+
+static const char *system_clock_parent_names[] __initdata = {
+ NULL,
+ "usbck",
+ NULL,
+ NULL,
+ "usbck",
+ NULL,
+ NULL,
+ NULL,
+ "prog0",
+ "prog1",
+ "prog2",
+ "prog3",
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
-static struct clk pck0 = {
- .name = "pck0",
- .pmc_mask = AT91_PMC_PCK0,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 0,
-};
-static struct clk pck1 = {
- .name = "pck1",
- .pmc_mask = AT91_PMC_PCK1,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 1,
-};
-static struct clk pck2 = {
- .name = "pck2",
- .pmc_mask = AT91_PMC_PCK2,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 2,
-};
-static struct clk pck3 = {
- .name = "pck3",
- .pmc_mask = AT91_PMC_PCK3,
- .type = CLK_TYPE_PROGRAMMABLE,
- .id = 3,
+static const char *prog_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The pll clocks.
+ */
+static struct clk_lookup pll_clk_lookup[] __initdata = {
+ CLKDEV_INIT(NULL, "plla", NULL),
+ CLKDEV_INIT(NULL, "pllb", NULL),
+};
+
+static struct clk_range at91rm9200_pll_output[] = {
+ CLK_RANGE(80000000, 160000000),
+ CLK_RANGE(150000000, 180000000),
};
+static u8 at91rm9200_pll_out[] = {0, 2};
+
+struct clk_pll_characteristics at91rm9200_pll_characteristics = {
+ .input = CLK_RANGE(1000000, 32000000),
+ .num_output = ARRAY_SIZE(at91rm9200_pll_output),
+ .output = at91rm9200_pll_output,
+ .out = at91rm9200_pll_out,
+};
+
+
+/*
+ * The master clock.
+ */
+static struct clk_lookup mck_clk_lookup[] = {
+ CLKDEV_INIT(NULL, "mck", NULL),
+ CLKDEV_INIT("atmel_usart.0", "usart", NULL),
+};
+
+struct clk_master_characteristics at91rm9200_master_characteristics = {
+ .output = CLK_RANGE(0, 80000000),
+ .have_div3_pres = 0,
+ .divisors = {1, 2, 3, 4},
+};
+
+static const char *master_clock_parent_names[] __initdata = {
+ "clk32k",
+ "main",
+ "plla",
+ "pllb",
+};
+
+/*
+ * The USB clock.
+ */
+static u32 usb_divisors[] = {1, 2, 0, 0};
static void __init at91rm9200_register_clocks(void)
{
int i;
+ int k;
+ size_t size;
+ struct clk *clk;
+ const char *name;
+ struct clk_lookup *lookup;
+
+ for (i = 0; i < ARRAY_SIZE(pll_clk_lookup); i++) {
+ name = pll_clk_lookup[i].con_id;
+ clk = at91_clk_register_pll(name, "main", i,
+ &at91rm9200_pll_layout,
+ &at91rm9200_pll_characteristics);
+ pll_clk_lookup[i].clk = clk;
+ }
+ clkdev_add_table(pll_clk_lookup, ARRAY_SIZE(pll_clk_lookup));
+
+ clk = at91_clk_register_master("mck",
+ ARRAY_SIZE(master_clock_parent_names),
+ master_clock_parent_names,
+ &at91rm9200_master_layout,
+ &at91rm9200_master_characteristics);
- for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
- clk_register(periph_clocks[i]);
+ for (i = 0; i < ARRAY_SIZE(mck_clk_lookup); i++)
+ mck_clk_lookup[i].clk = clk;
+ clkdev_add_table(mck_clk_lookup, ARRAY_SIZE(mck_clk_lookup));
- clkdev_add_table(periph_clocks_lookups,
- ARRAY_SIZE(periph_clocks_lookups));
- clkdev_add_table(usart_clocks_lookups,
- ARRAY_SIZE(usart_clocks_lookups));
+ for (i = 0; i < ARRAY_SIZE(periph_clock_lookup_sizes); i++) {
+ size = periph_clock_lookup_sizes[i];
+ lookup = periph_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = periph_clock_lookups[i][0].con_id;
+ if (!name)
+ continue;
+ clk = at91_clk_register_peripheral(name, "mck", i);
- clk_register(&pck0);
- clk_register(&pck1);
- clk_register(&pck2);
- clk_register(&pck3);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
+
+ for (i = 0; i < 4; i++) {
+ name = system_clock_parent_names[8 + i];
+ clk = at91_clk_register_programmable(name,
+ prog_clock_parent_names,
+ ARRAY_SIZE(prog_clock_parent_names),
+ i, &at91rm9200_programmable_layout);
+ }
+
+ clk = at91rm9200_clk_register_usb("usbck", "pllb", usb_divisors);
+
+ for (i = 0; i < ARRAY_SIZE(system_clock_lookup_sizes); i++) {
+ size = system_clock_lookup_sizes[i];
+ lookup = system_clock_lookups[i];
+ if (!size || !lookup)
+ continue;
+ name = system_clock_lookups[i][0].con_id;
+ if (!name || !system_clock_parent_names[i])
+ continue;
+ clk = at91_clk_register_system(name,
+ system_clock_parent_names[i],
+ i);
+ for (k = 0; k < size; k++)
+ lookup[k].clk = clk;
+ clkdev_add_table(lookup, size);
+ }
}
/* --------------------------------------------------------------------
--
1.7.9.5
Use device tree to get the source clock of the PIT (Periodic Interval Timer).
If the clock is not found in device tree (or dt is not enabled) we'll try to
get it using clk_lookup definitions.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/mach-at91/at91sam926x_time.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 3a4bc2e..fba7bd6 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
static u32 pit_cycle; /* write-once */
static u32 pit_cnt; /* access only w/system irq blocked */
static void __iomem *pit_base_addr __read_mostly;
+static struct clk *mck;
static inline unsigned int pit_read(unsigned int reg_offset)
{
@@ -186,6 +187,7 @@ static int __init of_at91sam926x_pit_init(void)
{
struct device_node *np;
int ret;
+ int err = -EINVAL;
np = of_find_matching_node(NULL, pit_timer_ids);
if (!np)
@@ -195,10 +197,19 @@ static int __init of_at91sam926x_pit_init(void)
if (!pit_base_addr)
goto node_err;
+ mck = of_clk_get(np, 0);
+ if (IS_ERR(mck)) {
+ err = PTR_RET(mck);
+ mck = NULL;
+ pr_crit("AT91: PIT: Unable to get mck clk from DT\n");
+ goto ioremap_err;
+ }
+
/* Get the interrupts property */
ret = irq_of_parse_and_map(np, 0);
if (!ret) {
pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+ clk_put(mck);
goto ioremap_err;
}
at91sam926x_pit_irq.irq = ret;
@@ -212,7 +223,7 @@ ioremap_err:
node_err:
of_node_put(np);
err:
- return -EINVAL;
+ return err;
}
#else
static int __init of_at91sam926x_pit_init(void)
@@ -237,7 +248,13 @@ void __init at91sam926x_pit_init(void)
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
- pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ if (!mck)
+ mck = clk_get(NULL, "mck");
+
+ if (IS_ERR(mck))
+ panic("AT91: PIT: Unable to get mck clk\n");
+ pit_rate = clk_get_rate(mck) / 16;
+ pr_notice("AT91: PIT: mck rate = %lu\n", pit_rate);
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/misc/atmel-ssc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
index c09c28f..e619197 100644
--- a/drivers/misc/atmel-ssc.c
+++ b/drivers/misc/atmel-ssc.c
@@ -58,7 +58,7 @@ struct ssc_device *ssc_request(unsigned int ssc_num)
ssc->user++;
spin_unlock(&user_lock);
- clk_enable(ssc->clk);
+ clk_prepare_enable(ssc->clk);
return ssc;
}
@@ -69,7 +69,7 @@ void ssc_free(struct ssc_device *ssc)
spin_lock(&user_lock);
if (ssc->user) {
ssc->user--;
- clk_disable(ssc->clk);
+ clk_disable_unprepare(ssc->clk);
} else {
dev_dbg(&ssc->pdev->dev, "device already free\n");
}
@@ -172,10 +172,10 @@ static int ssc_probe(struct platform_device *pdev)
}
/* disable all interrupts */
- clk_enable(ssc->clk);
+ clk_prepare_enable(ssc->clk);
ssc_writel(ssc->regs, IDR, -1);
ssc_readl(ssc->regs, SR);
- clk_disable(ssc->clk);
+ clk_disable_unprepare(ssc->clk);
ssc->irq = platform_get_irq(pdev, 0);
if (!ssc->irq) {
--
1.7.9.5
On Fri, Jun 07, 2013 at 06:26:09PM +0200, Boris BREZILLON wrote:
> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
> avoid common clk framework warnings.
Applied since I happened to notice this on he list but you should
*always* CC maintainers on patches otherwise they're likely to get
missed.
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/tty/serial/atmel_serial.c | 35 ++++++++++++++++++++++++++++-------
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 3467462..b9b42cf 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -1458,9 +1458,10 @@ static void atmel_of_init_port(struct atmel_uart_port *atmel_port,
/*
* Configure the port from the platform device resource info.
*/
-static void atmel_init_port(struct atmel_uart_port *atmel_port,
+static int atmel_init_port(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
+ int ret;
struct uart_port *port = &atmel_port->uart;
struct atmel_uart_data *pdata = pdev->dev.platform_data;
@@ -1496,7 +1497,17 @@ static void atmel_init_port(struct atmel_uart_port *atmel_port,
/* for console, the clock could already be configured */
if (!atmel_port->clk) {
atmel_port->clk = clk_get(&pdev->dev, "usart");
- clk_enable(atmel_port->clk);
+ if (IS_ERR(atmel_port->clk)) {
+ ret = PTR_ERR(atmel_port->clk);
+ atmel_port->clk = NULL;
+ return ret;
+ }
+ ret = clk_prepare_enable(atmel_port->clk);
+ if (ret) {
+ clk_put(atmel_port->clk);
+ atmel_port->clk = NULL;
+ return ret;
+ }
port->uartclk = clk_get_rate(atmel_port->clk);
clk_disable(atmel_port->clk);
/* only enable clock when USART is in use */
@@ -1511,6 +1522,8 @@ static void atmel_init_port(struct atmel_uart_port *atmel_port,
} else {
atmel_port->tx_done_mask = ATMEL_US_TXRDY;
}
+
+ return 0;
}
struct platform_device *atmel_default_console_device; /* the serial console device */
@@ -1601,6 +1614,7 @@ static void __init atmel_console_get_options(struct uart_port *port, int *baud,
static int __init atmel_console_setup(struct console *co, char *options)
{
+ int ret;
struct uart_port *port = &atmel_ports[co->index].uart;
int baud = 115200;
int bits = 8;
@@ -1612,7 +1626,9 @@ static int __init atmel_console_setup(struct console *co, char *options)
return -ENODEV;
}
- clk_enable(atmel_ports[co->index].clk);
+ ret = clk_enable(atmel_ports[co->index].clk);
+ if (ret)
+ return ret;
UART_PUT_IDR(port, -1);
UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
@@ -1645,6 +1661,7 @@ static struct console atmel_console = {
*/
static int __init atmel_console_init(void)
{
+ int ret;
if (atmel_default_console_device) {
struct atmel_uart_data *pdata =
atmel_default_console_device->dev.platform_data;
@@ -1655,7 +1672,9 @@ static int __init atmel_console_init(void)
port->uart.line = id;
add_preferred_console(ATMEL_DEVICENAME, id, NULL);
- atmel_init_port(port, atmel_default_console_device);
+ ret = atmel_init_port(port, atmel_default_console_device);
+ if (ret)
+ return ret;
register_console(&atmel_console);
}
@@ -1786,7 +1805,9 @@ static int atmel_serial_probe(struct platform_device *pdev)
port->backup_imr = 0;
port->uart.line = ret;
- atmel_init_port(port, pdev);
+ ret = atmel_init_port(port, pdev);
+ if (ret)
+ goto err;
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
if (IS_ERR(pinctrl)) {
@@ -1812,9 +1833,9 @@ static int atmel_serial_probe(struct platform_device *pdev)
&& ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
/*
* The serial core enabled the clock for us, so undo
- * the clk_enable() in atmel_console_setup()
+ * the clk_prepare_enable() in atmel_console_setup()
*/
- clk_disable(port->clk);
+ clk_disable_unprepare(port->clk);
}
#endif
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/usb/gadget/at91_udc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 073b938..ad03b6b 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -870,8 +870,8 @@ static void clk_on(struct at91_udc *udc)
if (udc->clocked)
return;
udc->clocked = 1;
- clk_enable(udc->iclk);
- clk_enable(udc->fclk);
+ clk_prepare_enable(udc->iclk);
+ clk_prepare_enable(udc->fclk);
}
static void clk_off(struct at91_udc *udc)
@@ -880,8 +880,8 @@ static void clk_off(struct at91_udc *udc)
return;
udc->clocked = 0;
udc->gadget.speed = USB_SPEED_UNKNOWN;
- clk_disable(udc->fclk);
- clk_disable(udc->iclk);
+ clk_disable_unprepare(udc->fclk);
+ clk_disable_unprepare(udc->iclk);
}
/*
@@ -1782,12 +1782,12 @@ static int at91udc_probe(struct platform_device *pdev)
}
/* don't do anything until we have both gadget driver and VBUS */
- clk_enable(udc->iclk);
+ clk_prepare_enable(udc->iclk);
at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff);
/* Clear all pending interrupts - UDP may be used by bootloader. */
at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff);
- clk_disable(udc->iclk);
+ clk_disable_unprepare(udc->iclk);
/* request UDC and maybe VBUS irqs */
udc->udp_irq = platform_get_irq(pdev, 0);
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/usb/host/ehci-atmel.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 6642009..015ce6e 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -37,15 +37,15 @@ static int clocked;
static void atmel_start_clock(void)
{
- clk_enable(iclk);
- clk_enable(fclk);
+ clk_prepare_enable(iclk);
+ clk_prepare_enable(fclk);
clocked = 1;
}
static void atmel_stop_clock(void)
{
- clk_disable(fclk);
- clk_disable(iclk);
+ clk_disable_unprepare(fclk);
+ clk_disable_unprepare(iclk);
clocked = 0;
}
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/video/atmel_lcdfb.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 540909d..8525457 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -893,14 +893,14 @@ static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
{
- clk_enable(sinfo->bus_clk);
- clk_enable(sinfo->lcdc_clk);
+ clk_prepare_enable(sinfo->bus_clk);
+ clk_prepare_enable(sinfo->lcdc_clk);
}
static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
{
- clk_disable(sinfo->bus_clk);
- clk_disable(sinfo->lcdc_clk);
+ clk_disable_unprepare(sinfo->bus_clk);
+ clk_disable_unprepare(sinfo->lcdc_clk);
}
--
1.7.9.5
Define at91rm9200 clocks in at91rm9200 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91rm9200.dtsi | 133 +++++++++++++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b91cf78..f373aa8 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -75,6 +75,106 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 180000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 80000000>;
+ divisors = <1 2 3 4>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 0 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1 2 3>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ clock-output-names = "prog0", "prog1", "prog2", "prog3";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <1 4 8 9 10 11>;
+ clocks = <&usb>, <&usb>,
+ <&prog 0>, <&prog 1>,
+ <&prog 2>, <&prog 3>;
+ clock-output-names = "udpck", "uhpck",
+ "pck0", "pck1",
+ "pck2", "pck3";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 11 12 13 14 17
+ 18 19 20 21 22 23 24 25 26 27 28>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioC_clk",
+ "pioD_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "usart3_clk",
+ "mci_clk",
+ "udc_clk",
+ "twi_clk",
+ "spi_clk",
+ "ssc0_clk",
+ "ssc1_clk",
+ "ssc2_clk",
+ "tc0_clk",
+ "tc1_clk",
+ "tc2_clk",
+ "tc3_clk",
+ "tc4_clk",
+ "tc5_clk",
+ "ohci_clk",
+ "pclk";
+ };
};
st: timer@fffffd00 {
@@ -89,6 +189,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffa4000 {
@@ -97,6 +199,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&periph 21>, <&periph 22>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
i2c0: i2c@fffb8000 {
@@ -107,6 +211,7 @@
pinctrl-0 = <&pinctrl_twi>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -116,6 +221,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -125,6 +232,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disable";
};
@@ -134,6 +243,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 15>;
+ clock-names = "pclk";
status = "disable";
};
@@ -143,6 +254,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disable";
};
@@ -153,6 +266,8 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 24>, <&periph 24>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -482,6 +597,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -492,6 +608,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -502,6 +619,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffffa00 {
@@ -512,6 +630,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -521,6 +640,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -532,6 +653,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -543,6 +666,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -554,6 +679,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -565,6 +692,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -572,6 +701,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 11>, <&system 1>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
};
@@ -597,6 +728,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00300000 0x100000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 23>, <&periph 23>, <&system 4>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define at91sam9260 clocks in at91sam9260 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9260.dtsi | 144 +++++++++++++++++++++++++++++++++++-
1 file changed, 143 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 899a7cf..eac42f9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -72,6 +72,109 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 5000000>;
+ output = <70000000 130000000>;
+ out = <1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 105000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <6 7 8 9>;
+ clocks = <&usb>, <&usb>, <&prog 0>, <&prog 1>;
+ clock-output-names = "udpck", "uhpck", "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 11 12 13 14 17
+ 18 19 20 21 22 23 24 25 26 27 28>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioC_clk",
+ "adc_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "mci_clk",
+ "udc_clk",
+ "twi_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "ssc_clk",
+ "tc0_clk",
+ "tc1_clk",
+ "tc2_clk",
+ "ohci_clk",
+ "pclk",
+ "isi_clk",
+ "usart3_clk",
+ "usart4_clk",
+ "usart5_clk",
+ "tc3_clk",
+ "tc4_clk",
+ "tc5_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
};
rstc@fffffd00 {
@@ -88,6 +191,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fffa0000 {
@@ -96,6 +200,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffdc000 {
@@ -104,6 +210,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>, <&periph 27>, <&periph 28>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
pinctrl@fffff400 {
@@ -271,7 +379,7 @@
atmel,pins =
<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
- AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
@@ -439,6 +547,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -449,6 +558,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -459,6 +569,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -468,6 +579,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -479,6 +592,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -490,6 +605,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -501,6 +618,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -512,6 +631,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 23>;
+ clock-names = "usart";
status = "disabled";
};
@@ -523,6 +644,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 24>;
+ clock-names = "usart";
status = "disabled";
};
@@ -534,6 +657,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 25>;
+ clock-names = "usart";
status = "disabled";
};
@@ -543,6 +668,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -550,6 +677,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 10>, <&system 6>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -559,6 +688,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -568,6 +698,8 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -577,6 +709,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -588,6 +722,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 12>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -599,6 +735,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -606,6 +744,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 5>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
@@ -669,6 +809,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 20>, <&periph 20>, <&system 7>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define at91sam9263 clocks in at91sam9263 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9263.dtsi | 135 ++++++++++++++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index ff63811..f948575 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -64,6 +64,106 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 32000000>;
+ output = <80000000 200000000
+ 190000000 240000000>;
+ out = <0 2>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 120000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1 2 3>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ clock-output-names = "prog0", "prog1", "prog2", "prog3";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <6 7 8 9 10 11>;
+ clocks = <&usb>, <&usb>, <&prog 0>, <&prog 1>, <&prog 2>,
+ <&prog 3>;
+ clock-output-names = "udpck", "uhpck", "pck0", "pck1",
+ "pck2", "pck3";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 23 24 25 26 27 29>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioCDE_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "mci0_clk",
+ "mci1_clk",
+ "can_clk",
+ "twi_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "ssc0_clk",
+ "ssc1_clk",
+ "ac97_clk",
+ "tcb_clk",
+ "pwm_clk",
+ "pclk",
+ "2dge_clk",
+ "udc_clk",
+ "isi_clk",
+ "lcdc_clk",
+ "dma_clk",
+ "ohci_clk";
+
+ };
};
ramc: ramc@ffffe200 {
@@ -76,12 +176,15 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>;
+ clock-names = "t0_clk";
};
rstc@fffffd00 {
@@ -370,6 +473,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff400 {
@@ -380,6 +484,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff600 {
@@ -390,6 +495,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffff800 {
@@ -400,6 +506,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioE: gpio@fffffa00 {
@@ -410,6 +517,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -419,6 +527,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -430,6 +540,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -441,6 +553,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -452,6 +566,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -461,6 +577,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -470,6 +588,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -479,6 +599,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -486,6 +608,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 24>, <&system 7>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -495,6 +619,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -504,6 +629,8 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -513,6 +640,8 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -530,6 +659,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -541,6 +672,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
};
@@ -567,6 +700,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 29>, <&periph 29>, <&system 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define at91sam9g45 clocks in at91sam9g45 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9g45.dtsi | 157 ++++++++++++++++++++++++++++++++++++
1 file changed, 157 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index faec17d..413c6cf 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -76,6 +76,119 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9g45-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <2 6 8 9>;
+ clocks = <&mck>, <&usb>, <&prog 0>, <&prog 1>;
+ clock-output-names = "ddrck", "uhpck", "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 29>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioC_clk",
+ "pioDE_clk",
+ "trng_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "usart3_clk",
+ "mci0_clk",
+ "twi0_clk",
+ "twi1_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "ssc0_clk",
+ "ssc1_clk",
+ "tcb0_clk",
+ "pwm_clk",
+ "tsc_clk",
+ "dma_clk",
+ "uhphs_clk",
+ "lcdc_clk",
+ "ac97_clk",
+ "pclk",
+ "isi_clk",
+ "udphs_clk",
+ "mci1_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
};
rstc@fffffd00 {
@@ -87,6 +200,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
@@ -99,12 +213,16 @@
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 18>;
+ clock-names = "t0_clk";
};
dma: dma-controller@ffffec00 {
@@ -112,6 +230,8 @@
reg = <0xffffec00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl@fffff200 {
@@ -428,6 +548,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff400 {
@@ -438,6 +559,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff600 {
@@ -448,6 +570,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
pioD: gpio@fffff800 {
@@ -458,6 +581,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
pioE: gpio@fffffa00 {
@@ -468,6 +592,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 5>;
};
};
@@ -477,6 +602,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -488,6 +615,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -499,6 +628,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -510,6 +641,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 9>;
+ clock-names = "usart";
status = "disabled";
};
@@ -521,6 +654,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 10>;
+ clock-names = "usart";
status = "disabled";
};
@@ -530,6 +665,8 @@
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 25>, <&periph 25>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -539,6 +676,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
status = "disabled";
};
@@ -548,6 +686,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 13>;
status = "disabled";
};
@@ -557,6 +696,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 16>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -566,6 +707,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 17>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -573,6 +716,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 20>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>;
@@ -617,6 +762,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -628,6 +775,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 29>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -645,6 +794,8 @@
interrupts = <14 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -656,6 +807,8 @@
interrupts = <15 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 15>;
+ clock-names = "spi_clk";
status = "disabled";
};
};
@@ -682,6 +835,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -689,6 +844,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define at91sam9n12 clocks in at91sam9n12 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 153 ++++++++++++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 3166e1d..be947bb 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -70,6 +70,126 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ usbs0-unused;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <2 3 6 7 8 9>;
+ clocks = <&mck>, <&mck>, <&usb>, <&usb>,
+ <&prog 0>, <&prog 1>;
+ clock-output-names = "ddrck", "lcdck", "uhpck", "udpck",
+ "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 12 13 14 15 16
+ 17 18 19 20 22 23 25 27 28 29 30>;
+ clock-output-names = "pioAB_clk",
+ "pioCD_clk",
+ "fuse_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "usart3_clk",
+ "twi0_ck",
+ "twi1_ck",
+ "hsmci_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "uart0_clk",
+ "uart1_clk",
+ "tcb_clk",
+ "pwm_clk",
+ "adc_clk",
+ "dma_clk",
+ "uhp_clk",
+ "udc_clk",
+ "lcdc_clk",
+ "sha_clk",
+ "ssc_clk",
+ "aes_clk",
+ "trng_clk";
+ };
};
rstc@fffffe00 {
@@ -81,6 +201,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
shdwc@fffffe10 {
@@ -96,6 +217,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -103,12 +226,16 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma: dma-controller@ffffec00 {
@@ -116,6 +243,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
pinctrl@fffff400 {
@@ -369,6 +498,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -379,6 +509,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio@fffff800 {
@@ -389,6 +520,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio@fffffa00 {
@@ -399,6 +531,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -408,6 +541,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -417,6 +552,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -426,6 +563,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -435,6 +574,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -444,6 +585,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -453,6 +596,8 @@
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -465,6 +610,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -477,6 +623,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -488,6 +635,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -499,6 +648,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -534,6 +685,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define at91sam9x5 clocks in at91sam9x5 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9g15.dtsi | 11 ++
arch/arm/boot/dts/at91sam9g25.dtsi | 3 +
arch/arm/boot/dts/at91sam9g35.dtsi | 23 +++
arch/arm/boot/dts/at91sam9x25.dtsi | 25 +---
arch/arm/boot/dts/at91sam9x35.dtsi | 3 +
arch/arm/boot/dts/at91sam9x5.dtsi | 226 +++++++++++++++++++++---------
arch/arm/boot/dts/at91sam9x5_can.dtsi | 24 ++++
arch/arm/boot/dts/at91sam9x5_isi.dtsi | 24 ++++
arch/arm/boot/dts/at91sam9x5_lcdc.dtsi | 32 +++++
arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 68 +++++++++
arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 56 ++++++++
arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 60 ++++++++
12 files changed, 467 insertions(+), 88 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index cfd7044..29d765c 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
/ {
model = "Atmel AT91SAM9G15 SoC";
@@ -23,6 +24,16 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ at91sam9g15periph: at91sam9g15periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <25>;
+ clock-output-names = "lcdc_clk";
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index b4ec6fe..49f5122 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index bebf9f5..6ee3c5a 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -7,6 +7,8 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_isi.dtsi"
/ {
model = "Atmel AT91SAM9G35 SoC";
@@ -23,6 +25,27 @@
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
+
+ pmc: pmc@fffffc00 {
+ at91sam9g35periph: at91sam9g35periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <24 25>;
+ clock-output-names = "macb_clk", "isi_clk";
+ };
+ };
+
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <24 4 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clocks = <&at91sam9g35periph 24>, <&at91sam9g35periph 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 49e94ab..3c5fa33 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -7,6 +7,10 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_usart3.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_macb1.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X25 SoC";
@@ -22,27 +26,6 @@
0x80000000 0xfffd0000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
- AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
- AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
- AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
- AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
- AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
- AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
- AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
- AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
- AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
- };
- };
- };
-
- macb1: ethernet@f8030000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
};
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 1a3d525..ecbdf5d 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -7,6 +7,9 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_macb0.dtsi"
+#include "at91sam9x5_lcdc.dtsi"
+#include "at91sam9x5_can.dtsi"
/ {
model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index e77106e..18f9283 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -73,6 +73,125 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 133000000>;
+ divisors = <1 2 4 3>;
+ have-div3-pres;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ smd: smdck {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <2 4 6 7 8 9>;
+ clocks = <&mck>, <&smd>, <&usb>,
+ <&usb>, <&prog 0>, <&prog 1>;
+ clock-output-names = "ddrck", "smdck",
+ "uhpck", "udpck",
+ "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 26 28>;
+ clock-output-names = "pioAB_clk",
+ "pioCD_clk",
+ "smd_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "twi0_clk",
+ "twi1_clk",
+ "twi2_clk",
+ "mci0_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "uart0_clk",
+ "uart1_clk",
+ "tcb_clk",
+ "pwm_clk",
+ "adc_clk",
+ "dma0_clk",
+ "dma1_clk",
+ "uhphs_clk",
+ "udphs_clk",
+ "mci1_clk",
+ "ssc_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13200000>;
+ };
+ };
};
rstc@fffffe00 {
@@ -89,18 +208,23 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@f8008000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>;
+ clock-names = "t0_clk";
};
dma0: dma-controller@ffffec00 {
@@ -108,6 +232,8 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 20>;
+ clock-names = "dma_clk";
};
dma1: dma-controller@ffffee00 {
@@ -115,6 +241,8 @@
reg = <0xffffee00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 21>;
+ clock-names = "dma_clk";
};
pinctrl@fffff400 {
@@ -201,29 +329,6 @@
};
};
- usart3 {
- pinctrl_usart3: usart3-0 {
- atmel,pins =
- <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
- AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
- };
-
- pinctrl_usart3_rts: usart3_rts-0 {
- atmel,pins =
- <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
- };
-
- pinctrl_usart3_cts: usart3_cts-0 {
- atmel,pins =
- <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
- };
-
- pinctrl_usart3_sck: usart3_sck-0 {
- atmel,pins =
- <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
- };
- };
-
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
@@ -272,34 +377,6 @@
};
};
- macb0 {
- pinctrl_macb0_rmii: macb0_rmii-0 {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
- };
-
- pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
- };
- };
-
mmc0 {
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
atmel,pins =
@@ -498,6 +575,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -509,6 +587,7 @@
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioC: gpio@fffff800 {
@@ -519,6 +598,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioD: gpio@fffffa00 {
@@ -530,6 +610,7 @@
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
};
@@ -539,6 +620,8 @@
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 28>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -550,6 +633,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 26>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -561,6 +646,8 @@
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 12>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -570,6 +657,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -579,6 +668,8 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 5>;
+ clock-names = "usart";
status = "disabled";
};
@@ -588,6 +679,8 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -597,22 +690,8 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- status = "disabled";
- };
-
- macb0: ethernet@f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_rmii>;
- status = "disabled";
- };
-
- macb1: ethernet@f8030000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf8030000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -627,6 +706,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&periph 9>;
status = "disabled";
};
@@ -641,6 +721,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&periph 10>;
status = "disabled";
};
@@ -655,6 +736,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -680,6 +762,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 19>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external;
atmel,adc-channels-used = <0xffff>;
atmel,adc-vref = <3300>;
@@ -725,6 +809,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -736,6 +822,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 14>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -778,6 +866,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&periph 22>, <&system 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -785,6 +875,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 22>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
new file mode 100644
index 0000000..224752c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -0,0 +1,24 @@
+/*
+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ isiperiph: isiperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <29 30>;
+ clock-output-names = "can0_clk", "can1_clk";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
new file mode 100644
index 0000000..86244c6
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -0,0 +1,24 @@
+/*
+ * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * ISI (Image Sensor Interface) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ isiperiph: isiperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <25>;
+ clock-output-names = "isi_clk";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
new file mode 100644
index 0000000..6c77b0f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_lcdc.dtsi
@@ -0,0 +1,32 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCDC (LCD controller) support.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ lcdsys: lcdsysck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <3>;
+ clocks = <&mck>;
+ clock-output-names = "lcdck";
+ };
+
+ lcdcperiph: lcdcperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <25>;
+ clock-output-names = "lcdc_clk";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
new file mode 100644
index 0000000..2d05137
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -0,0 +1,68 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+
+ pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ macb0periph: macb0periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <24>;
+ clock-output-names = "macb0_clk";
+ };
+ };
+
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clocks = <&macb0periph 24>, <&macb0periph 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
new file mode 100644
index 0000000..8d9c8f7
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -0,0 +1,56 @@
+/*
+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
+ * Ethernet interfaces.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
+ AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
+ AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
+ AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
+ AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
+ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
+ AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
+ AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
+ AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
+ AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ macb1periph: macb1periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <27>;
+ clock-output-names = "macb1_clk";
+ };
+ };
+
+ macb1: ethernet@f8030000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf8030000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&macb1periph 27>, <&macb1periph 27>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
new file mode 100644
index 0000000..6146fd0
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -0,0 +1,60 @@
+/*
+ * at91sam9x5_lcdc.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 4 USART.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
+ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
+ };
+
+ pinctrl_usart3_sck: usart3_sck-0 {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ usart3periph: usart3periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <8>;
+ clock-output-names = "usart3_clk";
+ };
+ };
+
+ usart3: serial@f8028000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf8028000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&usart3periph 8>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+ };
+ };
+};
--
1.7.9.5
Define at91sam9g20 clocks in at91sam9g20 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9g20.dtsi | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index b8e7946..60a20ec 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -25,6 +25,43 @@
adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
+
+ pmc: pmc@fffffc00 {
+ plla: pllack {
+ compatible = "atmel,at91sam9g45-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <2000000 32000000>;
+ output = <74500000 800000000
+ 69500000 750000000
+ 64500000 700000000
+ 59500000 650000000
+ 54500000 600000000
+ 49500000 550000000
+ 44500000 500000000
+ 40000000 450000000>;
+ out = <0 1 2 3 0 1 2 3>;
+ icpll = <0 0 0 0 1 1 1 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91sam9g20-clk-pllb";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <2000000 32000000>;
+ output = <30000000 100000000>;
+ out = <0>;
+ };
+
+ mck: masterck {
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 133000000>;
+ divisors = <1 2 4 6>;
+ };
+ };
};
};
};
--
1.7.9.5
Define sama5d3 clocks in sama5d3 device tree.
Add references to the appropriate clocks in each peripheral.
Split optional sam9x5 peripherals in several device tree files. These
files are included by each SoC according to it's availability.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sama5d3.dtsi | 358 +++++++++++++++--------------------
arch/arm/boot/dts/sama5d3_can.dtsi | 67 +++++++
arch/arm/boot/dts/sama5d3_emac.dtsi | 56 ++++++
arch/arm/boot/dts/sama5d3_gmac.dtsi | 89 +++++++++
arch/arm/boot/dts/sama5d3_lcd.dtsi | 73 +++++++
arch/arm/boot/dts/sama5d3_mci2.dtsi | 59 ++++++
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 39 ++++
arch/arm/boot/dts/sama5d3_uart.dtsi | 42 ++++
8 files changed, 580 insertions(+), 203 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index c00e158..fded941 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -30,7 +30,6 @@
gpio3 = &pioD;
gpio4 = &pioE;
tcb0 = &tcb0;
- tcb1 = &tcb1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -70,6 +69,8 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 21>;
+ clock-names = "mci_clk";
};
spi0: spi@f0004000 {
@@ -85,6 +86,8 @@
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 24>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -94,15 +97,8 @@
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
- };
-
- can0: can@f000c000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf000c000 0x300>;
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&periph 38>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -110,6 +106,8 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf0010000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>;
+ clock-names = "t0_clk";
};
i2c0: i2c@f0014000 {
@@ -123,6 +121,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 18>;
status = "disabled";
};
@@ -137,6 +136,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 19>;
status = "disabled";
};
@@ -146,6 +146,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 12>;
+ clock-names = "usart";
status = "disabled";
};
@@ -155,15 +157,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- status = "disabled";
- };
-
- macb0: ethernet@f0028000 {
- compatible = "cnds,pc302-gem", "cdns,gem";
- reg = <0xf0028000 0x100>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 13>;
+ clock-names = "usart";
status = "disabled";
};
@@ -187,19 +182,6 @@
#size-cells = <0>;
};
- mmc2: mmc@f8004000 {
- compatible = "atmel,hsmci";
- reg = <0xf8004000 0x600>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
- dmas = <&dma1 2 1>;
- dma-names = "rxtx";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
spi1: spi@f8008000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -213,6 +195,8 @@
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 25>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -222,23 +206,11 @@
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&periph 39>;
+ clock-names = "pclk";
status = "disabled";
};
- can1: can@f8010000 {
- compatible = "atmel,at91sam9x5-can";
- reg = <0xf8010000 0x300>;
- interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_rx_tx>;
- };
-
- tcb1: timer@f8014000 {
- compatible = "atmel,at91sam9x5-tcb";
- reg = <0xf8014000 0x100>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
adc0: adc@f8018000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xf8018000 0x100>;
@@ -259,6 +231,8 @@
&pinctrl_adc0_ad10
&pinctrl_adc0_ad11
>;
+ clocks = <&periph 29>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channel-base = <0x50>;
atmel,adc-channels-used = <0xfff>;
atmel,adc-drdy-mask = <0x1000000>;
@@ -314,6 +288,7 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 20>;
status = "disabled";
};
@@ -323,6 +298,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 14>;
+ clock-names = "usart";
status = "disabled";
};
@@ -332,15 +309,8 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- status = "disabled";
- };
-
- macb1: ethernet@f802c000 {
- compatible = "cdns,at32ap7000-macb", "cdns,macb";
- reg = <0xf802c000 0x100>;
- interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&periph 15>;
+ clock-names = "usart";
status = "disabled";
};
@@ -367,6 +337,8 @@
reg = <0xffffe600 0x200>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 30>;
+ clock-names = "dma_clk";
};
dma1: dma-controller@ffffe800 {
@@ -374,6 +346,8 @@
reg = <0xffffe800 0x200>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
+ clocks = <&periph 31>;
+ clock-names = "dma_clk";
};
ramc0: ramc@ffffea00 {
@@ -387,6 +361,8 @@
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&periph 2>;
+ clock-names = "usart";
status = "disabled";
};
@@ -468,22 +444,6 @@
};
};
- can0 {
- pinctrl_can0_rx_tx: can0_rx_tx {
- atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
- AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
- };
- };
-
- can1 {
- pinctrl_can1_rx_tx: can1_rx_tx {
- atmel,pins =
- <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
- AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
- };
- };
-
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
@@ -531,107 +491,6 @@
};
};
- lcd {
- pinctrl_lcd: lcd-0 {
- atmel,pins =
- <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
- AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
- AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
- AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
- AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
- AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
- AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
- AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
- AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
- AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
- AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
- AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
- AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
- AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
- AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
- AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
- AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
- AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
- AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
- AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
- AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
- AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
- AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
- AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
- AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
- AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
- AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
- AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
- };
- };
-
- macb0 {
- pinctrl_macb0_data_rgmii: macb0_data_rgmii {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
- };
- pinctrl_macb0_data_gmii: macb0_data_gmii {
- atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
- AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
- AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
- AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
- AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
- AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
- AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
- AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
- };
- pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
- atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
- };
- pinctrl_macb0_signal_gmii: macb0_signal_gmii {
- atmel,pins =
- <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
- AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
- AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
- AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
- AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
- AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
- AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
- AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
- AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
- };
-
- };
-
- macb1 {
- pinctrl_macb1_rmii: macb1_rmii-0 {
- atmel,pins =
- <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
- AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
- AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
- AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
- AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
- AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
- AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
- AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
- AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
- AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
- };
- };
-
mmc0 {
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
atmel,pins =
@@ -669,21 +528,6 @@
};
};
- mmc2 {
- pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
- atmel,pins =
- <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
- AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
- AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
- };
- pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
- atmel,pins =
- <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
- AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
- AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
- };
- };
-
nand0 {
pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
atmel,pins =
@@ -742,22 +586,6 @@
};
};
- uart0 {
- pinctrl_uart0: uart0-0 {
- atmel,pins =
- <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
- AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
- };
- };
-
- uart1 {
- pinctrl_uart1: uart1-0 {
- atmel,pins =
- <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
- AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
- };
- };
-
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -869,6 +697,125 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x120>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,sama5d3-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <8000000 50000000>;
+ output = <400000000 1000000000>;
+ out = <0>;
+ icpll = <0>;
+ };
+
+ plladiv: plladivck {
+ compatible = "atmel,at91sam9x5-clk-plldiv";
+ #clock-cells = <0>;
+ clocks = <&plla>;
+ };
+
+ utmi: utmick {
+ compatible = "atmel,at91sam9x5-clk-utmi";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91sam9x5-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+ output = <0 166000000>;
+ divisors = <1 2 4 3>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91sam9x5-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91sam9x5-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1 2>;
+ clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+ clock-output-names = "prog0", "prog1", "prog2";
+ };
+
+ smd: smdck {
+ compatible = "atmel,at91sam9x5-clk-smd";
+ #clock-cells = <0>;
+ clocks = <&plladiv>, <&utmi>;
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <2 4 6 7 8 9 10>;
+ clocks = <&mck>, <&smd>, <&usb>, <&usb>,
+ <&prog 0>, <&prog 1>, <&prog 2>;
+ clock-output-names = "ddrck", "smdck", "uhpck", "udpck",
+ "pck0", "pck1", "pck2";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 6 7 8 9 10 12 13 14 15 18 19 20 21 22 23 24
+ 25 26 28 29 37 38 39 42 43 44 45 48>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioB_clk",
+ "pioD_clk",
+ "pioE_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "usart3_clk",
+ "twi0_clk",
+ "twi1_clk",
+ "twi2_clk",
+ "mci0_clk",
+ "mci1_clk",
+ "mci2_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "tcb0_clk",
+ "pwm_clk",
+ "adc_clk",
+ "dma0_clk",
+ "dma1_clk",
+ "uhphs_clk",
+ "udphs_clk",
+ "isi_clk",
+ "ssc0_clk",
+ "ssc1_clk",
+ "sha_clk",
+ "aes_clk",
+ "tdes_clk",
+ "trng_clk",
+ "fuse_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+ };
};
rstc@fffffe00 {
@@ -880,6 +827,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&mck>;
};
watchdog@fffffe40 {
@@ -1014,6 +962,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 32>, <&periph 32>, <&system 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1021,6 +971,8 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 32>, <&system 6>;
+ clock-names = "ehci_clk", "uhpck";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
new file mode 100644
index 0000000..2c428e6
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -0,0 +1,67 @@
+/*
+ * at91sama5d3_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * CAN support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+ AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
+ AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
+ };
+ };
+
+ };
+
+ pmc: pmc@fffffc00 {
+ canperiph: canperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <40 41>;
+ clock-output-names = "can0_clk", "can1_clk";
+ };
+ };
+
+ can0: can@f000c000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf000c000 0x300>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ clocks = <&canperiph 40>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ can1: can@f8010000 {
+ compatible = "atmel,at91sam9x5-can";
+ reg = <0xf8010000 0x300>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ clocks = <&canperiph 41>;
+ clock-names = "can_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
new file mode 100644
index 0000000..53e63ca
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -0,0 +1,56 @@
+/*
+ * at91sama5d3_emac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ macb1 {
+ pinctrl_macb1_rmii: macb1_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ emacperiph: emacperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <35>;
+ clock-output-names = "macb0_clk";
+ };
+ };
+
+ macb1: ethernet@f802c000 {
+ compatible = "cdns,at32ap7000-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb1_rmii>;
+ clocks = <&emacperiph 35>, <&periph 35>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
new file mode 100644
index 0000000..8db198b
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -0,0 +1,89 @@
+/*
+ * at91sama5d3_gmac.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * Gigabit Ethernet.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ macb0 {
+ pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
+ };
+ pinctrl_macb0_data_gmii: macb0_data_gmii {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+ AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
+ AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
+ AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
+ };
+ pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
+ };
+ pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+ atmel,pins =
+ <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
+ AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
+ AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
+ AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
+ };
+
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ gmacperiph: gmacperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <34>;
+ clock-output-names = "macb0_clk";
+ };
+ };
+
+ macb0: ethernet@f0028000 {
+ compatible = "cnds,pc302-gem", "cdns,gem";
+ reg = <0xf0028000 0x100>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+ clocks = <&periph 34>, <&periph 34>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
new file mode 100644
index 0000000..06a42e7
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -0,0 +1,73 @@
+/*
+ * at91sama5d3_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * LCD support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ lcd {
+ pinctrl_lcd: lcd-0 {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
+ AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
+ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
+ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
+ AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
+ AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
+ AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
+ AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
+ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
+ AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
+ AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
+ AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
+ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
+ AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
+ AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
+ AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
+ AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
+ AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
+ AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
+ AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
+ AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ lcdperiph: lcdperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <36>;
+ clock-output-names = "lcdc_clk";
+ };
+
+ lcdsys: lcdsysck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <3>;
+ clocks = <&mck>;
+ clock-output-names = "lcdck";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
new file mode 100644
index 0000000..9bec872
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -0,0 +1,59 @@
+/*
+ * at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 3 MMC ports
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ mmc2 {
+ pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
+ };
+ pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ mci2periph: mci2periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <23>;
+ clock-output-names = "mci2_clk";
+ };
+ };
+
+ mmc2: mmc@f8004000 {
+ compatible = "atmel,hsmci";
+ reg = <0xf8004000 0x600>;
+ interrupts = <23 4 0>;
+ dmas = <&dma1 2 1>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph 23>;
+ clock-names = "mci_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
new file mode 100644
index 0000000..338acc2
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -0,0 +1,39 @@
+/*
+ * at91sama5d3_tcb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * 2 TC blocks.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ tcb1 = &tcb1;
+ };
+
+ ahb {
+ apb {
+ pmc: pmc@fffffc00 {
+ tcb1periph: tcb1periphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <27>;
+ clock-output-names = "tcb1_clk";
+ };
+ };
+
+ tcb1: timer@f8014000 {
+ compatible = "atmel,at91sam9x5-tcb";
+ reg = <0xf8014000 0x100>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb1periph 27>;
+ clock-names = "t0_clk";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
new file mode 100644
index 0000000..8c3d869
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -0,0 +1,42 @@
+/*
+ * at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
+ * UART support
+ *
+ * Copyright (C) 2013 Boris BREZILLON <[email protected]>
+ *
+ * Licensed under GPLv2.
+ */
+
+/ {
+ ahb {
+ apb {
+ pinctrl@fffff200 {
+ uart0 {
+ pinctrl_uart0: uart0-0 {
+ atmel,pins =
+ <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+ AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+ };
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ uartperiph: uartperiphck {
+ compatible = "atmel,at91sam9x5-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <16 17>;
+ clock-output-names = "uart0_clk", "uart1_clk";
+ };
+ };
+ };
+ };
+};
--
1.7.9.5
Define the main clock frequency in every sam9260/sam9g20 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/animeo_ip.dts | 17 ++++++-----------
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/ge863-pro3.dtsi | 16 ++++++----------
arch/arm/boot/dts/kizbox.dts | 5 +++++
arch/arm/boot/dts/tny_a9260_common.dtsi | 17 ++++++-----------
arch/arm/boot/dts/usb_a9260_common.dtsi | 17 ++++++-----------
6 files changed, 35 insertions(+), 54 deletions(-)
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9e..1843f15 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -31,17 +31,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
usart0: serial@fffb0000 {
@@ -82,6 +71,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 1373546..b8c823d 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -17,17 +17,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
pinctrl@fffff400 {
@@ -108,6 +97,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 230099b..b0b6aae 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -10,22 +10,18 @@
#include "at91sam9260.dtsi"
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <6000000>;
- };
- };
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <6000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 02df191..091da2e 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -53,6 +53,11 @@
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index 0e6d3de..1cecb7a 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -15,22 +15,17 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index 2859776..3ed4db8 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -7,17 +7,6 @@
*/
/ {
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -33,6 +22,12 @@
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
Define the main clock frequency in every at91rm9200 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91rm9200ek.dts | 17 ++++++-----------
arch/arm/boot/dts/mpa1600.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 1405812..40772f3 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -16,19 +16,14 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
+
dbgu: serial@fffff200 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index ccf9ea2..317ee5a 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -16,17 +16,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -45,6 +34,11 @@
ssc1: ssc@fffd4000 {
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
usb0: ohci@00300000 {
--
1.7.9.5
Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
avoid common clk framework warnings.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/usb/host/ohci-at91.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index a0cb44f..329d277 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -41,17 +41,17 @@ extern int usb_disabled(void);
static void at91_start_clock(void)
{
- clk_enable(hclk);
- clk_enable(iclk);
- clk_enable(fclk);
+ clk_prepare_enable(hclk);
+ clk_prepare_enable(iclk);
+ clk_prepare_enable(fclk);
clocked = 1;
}
static void at91_stop_clock(void)
{
- clk_disable(fclk);
- clk_disable(iclk);
- clk_disable(hclk);
+ clk_disable_unprepare(fclk);
+ clk_disable_unprepare(iclk);
+ clk_disable_unprepare(hclk);
clocked = 0;
}
--
1.7.9.5
Define at91sam9260 clocks in at91sam9260 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9260.dtsi | 144 +++++++++++++++++++++++++++++++++++-
1 file changed, 143 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 899a7cf..eac42f9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -72,6 +72,109 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 5000000>;
+ output = <70000000 130000000>;
+ out = <1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 105000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <6 7 8 9>;
+ clocks = <&usb>, <&usb>, <&prog 0>, <&prog 1>;
+ clock-output-names = "udpck", "uhpck", "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 11 12 13 14 17
+ 18 19 20 21 22 23 24 25 26 27 28>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioC_clk",
+ "adc_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "mci_clk",
+ "udc_clk",
+ "twi_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "ssc_clk",
+ "tc0_clk",
+ "tc1_clk",
+ "tc2_clk",
+ "ohci_clk",
+ "pclk",
+ "isi_clk",
+ "usart3_clk",
+ "usart4_clk",
+ "usart5_clk",
+ "tc3_clk",
+ "tc4_clk",
+ "tc5_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
};
rstc@fffffd00 {
@@ -88,6 +191,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fffa0000 {
@@ -96,6 +200,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffdc000 {
@@ -104,6 +210,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>, <&periph 27>, <&periph 28>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
pinctrl@fffff400 {
@@ -271,7 +379,7 @@
atmel,pins =
<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
- AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
@@ -439,6 +547,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -449,6 +558,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -459,6 +569,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -468,6 +579,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -479,6 +592,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -490,6 +605,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -501,6 +618,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -512,6 +631,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 23>;
+ clock-names = "usart";
status = "disabled";
};
@@ -523,6 +644,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 24>;
+ clock-names = "usart";
status = "disabled";
};
@@ -534,6 +657,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 25>;
+ clock-names = "usart";
status = "disabled";
};
@@ -543,6 +668,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -550,6 +677,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 10>, <&system 6>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -559,6 +688,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -568,6 +698,8 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -577,6 +709,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -588,6 +722,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 12>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -599,6 +735,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -606,6 +744,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 5>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
@@ -669,6 +809,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 20>, <&periph 20>, <&system 7>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
Define the main clock frequency in every at91sam9263 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9263ek.dts | 17 ++++++-----------
arch/arm/boot/dts/tny_a9263.dts | 17 ++++++-----------
arch/arm/boot/dts/usb_a9263.dts | 17 ++++++-----------
3 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b..b3aa143 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16367660>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -93,6 +82,12 @@
watchdog@fffffd40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <16367660>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 0751a6a..067eefb 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -41,6 +30,12 @@
atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 290e603..ae5b92d 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -20,17 +20,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -61,6 +50,12 @@
atmel,wakeup-counter = <10>;
atmel,wakeup-rtt-timer;
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
Define the main clock frequency in every at91sam9g45 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9m10g45ek.dts | 17 ++++++-----------
arch/arm/boot/dts/pm9g45.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 91dbf79..e84b26d 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -21,17 +21,6 @@
reg = <0x70000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -116,6 +105,12 @@
reg = <0>;
};
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 33ffabe..3d8af99 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -20,17 +20,6 @@
reg = <0x70000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@ffffee00 {
@@ -73,6 +62,11 @@
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
Define the main clock frequency in every at91sam9n12 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9n12ek.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d59b70c..35f484a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -21,17 +21,6 @@
reg = <0x20000000 0x10000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <16000000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -81,6 +70,12 @@
watchdog@fffffe40 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <16000000>;
+ };
+ };
};
nand0: nand@40000000 {
--
1.7.9.5
Define the main clock frequency in every at91sam9x5 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91-ariag25.dts | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index cce45f5..f574682 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -33,17 +33,6 @@
reg = <0x20000000 0x8000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
mmc0: mmc@f0008000 {
@@ -147,6 +136,12 @@
rtc@fffffeb0 {
status = "okay";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
usb0: ohci@00600000 {
--
1.7.9.5
Define the main clock frequency in every sama5d3 boards.
Remove the old main clock definition.
Include the appropriate peripheral options according to peripherals
availability.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sama5d31ek.dts | 4 ++++
arch/arm/boot/dts/sama5d33ek.dts | 2 ++
arch/arm/boot/dts/sama5d34ek.dts | 4 ++++
arch/arm/boot/dts/sama5d35ek.dts | 6 ++++++
arch/arm/boot/dts/sama5d3xcm.dtsi | 17 ++++++-----------
5 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 027bac7..3a6c391 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,6 +7,10 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index 99bd0c8..3e35854 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,6 +7,8 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index fb8ee11..d03db9f 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,6 +7,10 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
+#include "sama5d3_lcd.dtsi"
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
#include "sama5d3xmb.dtsi"
#include "sama5d3xdm.dtsi"
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index 509a53d..57e49b1 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,6 +7,12 @@
* Licensed under GPLv2 or later.
*/
/dts-v1/;
+#include "sama5d3_gmac.dtsi"
+#include "sama5d3_emac.dtsi"
+#include "sama5d3_can.dtsi"
+#include "sama5d3_mci2.dtsi"
+#include "sama5d3_uart.dtsi"
+#include "sama5d3_tcb1.dtsi"
#include "sama5d3xmb.dtsi"
/ {
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 60637e4..a4ae732 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -19,22 +19,17 @@
reg = <0x20000000 0x20000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <12000000>;
- };
- };
-
ahb {
apb {
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
};
+
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <12000000>;
+ };
+ };
};
nand0: nand@60000000 {
--
1.7.9.5
On 07/06/2013 18:55, Mark Brown wrote:
> On Fri, Jun 07, 2013 at 06:26:09PM +0200, Boris BREZILLON wrote:
>> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
>> avoid common clk framework warnings.
>
> Applied since I happened to notice this on he list but you should
> *always* CC maintainers on patches otherwise they're likely to get
> missed.
>
I used get_mainainer script and it returns:
Arnd Bergmann <[email protected]> (supporter:CHAR and MISC DRI...)
Greg Kroah-Hartman <[email protected]> (supporter:CHAR and MISC
DRI...)
[email protected] (open list)
Please tell me if misuse this script or if I should use something else.
Best regards,
Boris
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Define the main clock frequency in every at91rm9200 boards.
Remove the old main clock definition.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91rm9200ek.dts | 17 ++++++-----------
arch/arm/boot/dts/mpa1600.dts | 16 +++++-----------
2 files changed, 11 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 1405812..40772f3 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -16,19 +16,14 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
+
dbgu: serial@fffff200 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index ccf9ea2..317ee5a 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -16,17 +16,6 @@
reg = <0x20000000 0x4000000>;
};
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- main_clock: clock@0 {
- compatible = "atmel,osc", "fixed-clock";
- clock-frequency = <18432000>;
- };
- };
-
ahb {
apb {
dbgu: serial@fffff200 {
@@ -45,6 +34,11 @@
ssc1: ssc@fffd4000 {
status = "okay";
};
+ pmc: pmc@fffffc00 {
+ main: mainck {
+ clock-frequency = <18432000>;
+ };
+ };
};
usb0: ohci@00300000 {
--
1.7.9.5
Define at91sam9260 clocks in at91sam9260 device tree.
Add references to the appropriate clocks in each peripheral.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/at91sam9260.dtsi | 144 +++++++++++++++++++++++++++++++++++-
1 file changed, 143 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 899a7cf..eac42f9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -72,6 +72,109 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
+
+ clk32k: slck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main", "fixed-clock";
+ #clock-cells = <0>;
+ clocks = <&clk32k>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <0>;
+ input = <1000000 32000000>;
+ output = <80000000 160000000
+ 150000000 240000000>;
+ out = <0 2>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ clocks = <&main>;
+ id = <1>;
+ input = <1000000 5000000>;
+ output = <70000000 130000000>;
+ out = <1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ output = <0 105000000>;
+ divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ clocks = <&pllb>;
+ divisors = <1 2 4 0>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #clock-cells = <1>;
+ ids = <0 1>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ clock-output-names = "prog0", "prog1";
+ };
+
+ system: systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #clock-cells = <1>;
+ ids = <6 7 8 9>;
+ clocks = <&usb>, <&usb>, <&prog 0>, <&prog 1>;
+ clock-output-names = "udpck", "uhpck", "pck0", "pck1";
+ };
+
+ periph: periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #clock-cells = <1>;
+ clocks = <&mck>;
+ ids = <2 3 4 5 6 7 8 9 10 11 12 13 14 17
+ 18 19 20 21 22 23 24 25 26 27 28>;
+ clock-output-names = "pioA_clk",
+ "pioB_clk",
+ "pioC_clk",
+ "adc_clk",
+ "usart0_clk",
+ "usart1_clk",
+ "usart2_clk",
+ "mci_clk",
+ "udc_clk",
+ "twi_clk",
+ "spi0_clk",
+ "spi1_clk",
+ "ssc_clk",
+ "tc0_clk",
+ "tc1_clk",
+ "tc2_clk",
+ "ohci_clk",
+ "pclk",
+ "isi_clk",
+ "usart3_clk",
+ "usart4_clk",
+ "usart5_clk",
+ "tc3_clk",
+ "tc4_clk",
+ "tc5_clk";
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
};
rstc@fffffd00 {
@@ -88,6 +191,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
};
tcb0: timer@fffa0000 {
@@ -96,6 +200,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 17>, <&periph 18>, <&periph 19>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
tcb1: timer@fffdc000 {
@@ -104,6 +210,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 26>, <&periph 27>, <&periph 28>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk";
};
pinctrl@fffff400 {
@@ -271,7 +379,7 @@
atmel,pins =
<AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
- AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
@@ -439,6 +547,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 2>;
};
pioB: gpio@fffff600 {
@@ -449,6 +558,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 3>;
};
pioC: gpio@fffff800 {
@@ -459,6 +569,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
+ clocks = <&periph 4>;
};
};
@@ -468,6 +579,8 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
status = "disabled";
};
@@ -479,6 +592,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&periph 6>;
+ clock-names = "usart";
status = "disabled";
};
@@ -490,6 +605,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&periph 7>;
+ clock-names = "usart";
status = "disabled";
};
@@ -501,6 +618,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&periph 8>;
+ clock-names = "usart";
status = "disabled";
};
@@ -512,6 +631,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&periph 23>;
+ clock-names = "usart";
status = "disabled";
};
@@ -523,6 +644,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&periph 24>;
+ clock-names = "usart";
status = "disabled";
};
@@ -534,6 +657,8 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&periph 25>;
+ clock-names = "usart";
status = "disabled";
};
@@ -543,6 +668,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&periph 21>, <&periph 21>;
+ clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -550,6 +677,8 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 10>, <&system 6>;
+ clock-names = "udc_clk", "udpck";
status = "disabled";
};
@@ -559,6 +688,7 @@
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 11>;
status = "disabled";
};
@@ -568,6 +698,8 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&periph 9>;
+ clock-names = "mci_clk";
status = "disabled";
};
@@ -577,6 +709,8 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&periph 14>;
+ clock-names = "pclk";
status = "disabled";
};
@@ -588,6 +722,8 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&periph 12>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -599,6 +735,8 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&periph 13>;
+ clock-names = "spi_clk";
status = "disabled";
};
@@ -606,6 +744,8 @@
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&periph 5>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
@@ -669,6 +809,8 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&periph 20>, <&periph 20>, <&system 7>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
--
1.7.9.5
On Fri, Jun 07, 2013 at 09:56:52PM +0200, Boris BREZILLON wrote:
> On 07/06/2013 18:55, Mark Brown wrote:
> >On Fri, Jun 07, 2013 at 06:26:09PM +0200, Boris BREZILLON wrote:
> >>Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
> >>avoid common clk framework warnings.
> >Applied since I happened to notice this on he list but you should
> >*always* CC maintainers on patches otherwise they're likely to get
> >missed.
> I used get_mainainer script and it returns:
> Arnd Bergmann <[email protected]> (supporter:CHAR and MISC DRI...)
> Greg Kroah-Hartman <[email protected]> (supporter:CHAR and
> MISC DRI...)
> [email protected] (open list)
> Please tell me if misuse this script or if I should use something else.
I suspect you only ran this on some of the patches as that's missing
pretty much all of the subsystem maintainers, but in general you always
have to think about the output of get_maintainer.pl - it isn't terribly
reliable.
On 10/06/2013 11:06, Mark Brown wrote:
> On Fri, Jun 07, 2013 at 09:56:52PM +0200, Boris BREZILLON wrote:
>> On 07/06/2013 18:55, Mark Brown wrote:
>>> On Fri, Jun 07, 2013 at 06:26:09PM +0200, Boris BREZILLON wrote:
>>>> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
>>>> avoid common clk framework warnings.
>>> Applied since I happened to notice this on he list but you should
>>> *always* CC maintainers on patches otherwise they're likely to get
>>> missed.
>> I used get_mainainer script and it returns:
>> Arnd Bergmann <[email protected]> (supporter:CHAR and MISC DRI...)
>> Greg Kroah-Hartman <[email protected]> (supporter:CHAR and
>> MISC DRI...)
>> [email protected] (open list)
>> Please tell me if misuse this script or if I should use something else.
> I suspect you only ran this on some of the patches as that's missing
> pretty much all of the subsystem maintainers, but in general you always
> have to think about the output of get_maintainer.pl - it isn't terribly
> reliable.
I use a script to add "cc" and "to" fields to each patch:
to.sh:
#!/bin/bash
opts="--nogit --nogit-fallback --norolestats --pattern-depth=1"
if [[ $(basename $1) =~ ^0000- ]] ; then
./scripts/get_maintainer.pl --nom $opts $(dirname $1)/*
else
maint=$(./scripts/get_maintainer.pl --nol $opts $1)
if [ "$maint" == "" ] ; then
echo "[hidden email]"
else
echo "$maint"
fi
fi
cc.sh:
#!/bin/bash
opts="--nogit --nogit-fallback --norolestats"
if [[ $(basename $1) =~ ^0000- ]] ; then
./scripts/get_maintainer.pl --nom $opts $(dirname $1)/*
else
./scripts/get_maintainer.pl $opts $1
fi
But I guess it does not handle subsystem maintainers.
I'll check it before sending patch series next time.
BTW thanks for applying this patch.
Best Regards,
Boris
On Fri, Jun 07, 2013 at 06:25:57PM +0200, Boris BREZILLON wrote:
> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
> avoid common clk framework warnings.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> drivers/dma/at_hdmac.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index e923cda..4772036 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -1374,7 +1374,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
> err = PTR_ERR(atdma->clk);
> goto err_clk;
> }
> - clk_enable(atdma->clk);
> + clk_prepare_enable(atdma->clk);
Can you add checks for return value in the driver as well
>
> /* force dma off, just in case */
> at_dma_off(atdma);
> @@ -1475,7 +1475,7 @@ err_pool_create:
> platform_set_drvdata(pdev, NULL);
> free_irq(platform_get_irq(pdev, 0), atdma);
> err_irq:
> - clk_disable(atdma->clk);
> + clk_disable_unprepare(atdma->clk);
> clk_put(atdma->clk);
> err_clk:
> iounmap(atdma->regs);
> @@ -1512,7 +1512,7 @@ static int at_dma_remove(struct platform_device *pdev)
> list_del(&chan->device_node);
> }
>
> - clk_disable(atdma->clk);
> + clk_disable_unprepare(atdma->clk);
> clk_put(atdma->clk);
>
> iounmap(atdma->regs);
> @@ -1531,7 +1531,7 @@ static void at_dma_shutdown(struct platform_device *pdev)
> struct at_dma *atdma = platform_get_drvdata(pdev);
>
> at_dma_off(platform_get_drvdata(pdev));
> - clk_disable(atdma->clk);
> + clk_disable_unprepare(atdma->clk);
> }
>
> static int at_dma_prepare(struct device *dev)
> @@ -1588,7 +1588,7 @@ static int at_dma_suspend_noirq(struct device *dev)
>
> /* disable DMA controller */
> at_dma_off(atdma);
> - clk_disable(atdma->clk);
> + clk_disable_unprepare(atdma->clk);
> return 0;
> }
>
> @@ -1618,7 +1618,7 @@ static int at_dma_resume_noirq(struct device *dev)
> struct dma_chan *chan, *_chan;
>
> /* bring back DMA controller */
> - clk_enable(atdma->clk);
> + clk_prepare_enable(atdma->clk);
> dma_writel(atdma, EN, AT_DMA_ENABLE);
>
> /* clear any pending interrupt */
--
~Vinod
On Fri, Jun 07, 2013 at 06:26:42PM +0200, Boris BREZILLON wrote:
> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
> avoid common clk framework warnings.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> drivers/pwm/pwm-atmel-tcb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied, thanks.
Thierry
On 12/06/2013 11:05, Vinod Koul wrote:
> On Fri, Jun 07, 2013 at 06:25:57PM +0200, Boris BREZILLON wrote:
>> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
>> avoid common clk framework warnings.
>>
>> Signed-off-by: Boris BREZILLON <[email protected]>
>> ---
>> drivers/dma/at_hdmac.c | 12 ++++++------
>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
>> index e923cda..4772036 100644
>> --- a/drivers/dma/at_hdmac.c
>> +++ b/drivers/dma/at_hdmac.c
>> @@ -1374,7 +1374,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
>> err = PTR_ERR(atdma->clk);
>> goto err_clk;
>> }
>> - clk_enable(atdma->clk);
>> + clk_prepare_enable(atdma->clk);
> Can you add checks for return value in the driver as well
Sure. I'll add it in the next version.
>>
>> /* force dma off, just in case */
>> at_dma_off(atdma);
>> @@ -1475,7 +1475,7 @@ err_pool_create:
>> platform_set_drvdata(pdev, NULL);
>> free_irq(platform_get_irq(pdev, 0), atdma);
>> err_irq:
>> - clk_disable(atdma->clk);
>> + clk_disable_unprepare(atdma->clk);
>> clk_put(atdma->clk);
>> err_clk:
>> iounmap(atdma->regs);
>> @@ -1512,7 +1512,7 @@ static int at_dma_remove(struct platform_device *pdev)
>> list_del(&chan->device_node);
>> }
>>
>> - clk_disable(atdma->clk);
>> + clk_disable_unprepare(atdma->clk);
>> clk_put(atdma->clk);
>>
>> iounmap(atdma->regs);
>> @@ -1531,7 +1531,7 @@ static void at_dma_shutdown(struct platform_device *pdev)
>> struct at_dma *atdma = platform_get_drvdata(pdev);
>>
>> at_dma_off(platform_get_drvdata(pdev));
>> - clk_disable(atdma->clk);
>> + clk_disable_unprepare(atdma->clk);
>> }
>>
>> static int at_dma_prepare(struct device *dev)
>> @@ -1588,7 +1588,7 @@ static int at_dma_suspend_noirq(struct device *dev)
>>
>> /* disable DMA controller */
>> at_dma_off(atdma);
>> - clk_disable(atdma->clk);
>> + clk_disable_unprepare(atdma->clk);
>> return 0;
>> }
>>
>> @@ -1618,7 +1618,7 @@ static int at_dma_resume_noirq(struct device *dev)
>> struct dma_chan *chan, *_chan;
>>
>> /* bring back DMA controller */
>> - clk_enable(atdma->clk);
>> + clk_prepare_enable(atdma->clk);
>> dma_writel(atdma, EN, AT_DMA_ENABLE);
>>
>> /* clear any pending interrupt */
> --
> ~Vinod
On Fri, Jun 07, 2013 at 08:08:18PM +0200, Boris BREZILLON wrote:
> Replace clk_enable/disable with clk_prepare_enable/disable_unprepare to
> avoid common clk framework warnings.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Felipe Balbi <[email protected]>
--
balbi
Quoting Boris BREZILLON (2013-06-07 08:11:03)
> +static struct clk_lookup pioA_clk_lookup[] = {
> + CLKDEV_INIT(NULL, "pioA_clk", NULL),
> + CLKDEV_INIT(NULL, "pioA", NULL),
> +};
It would be great to get rid of this clkdev data from the kernel as
well. Have you looked into encoding the aliases into your DT bindings?
Or have you looked into using of_clk_get?
Regards,
Mike
Hello,
On 20/06/2013 08:52, Mike Turquette wrote:
> Quoting Boris BREZILLON (2013-06-07 08:11:03)
>> +static struct clk_lookup pioA_clk_lookup[] = {
>> + CLKDEV_INIT(NULL, "pioA_clk", NULL),
>> + CLKDEV_INIT(NULL, "pioA", NULL),
>> +};
> It would be great to get rid of this clkdev data from the kernel as
> well. Have you looked into encoding the aliases into your DT bindings?
I already switched all dt boards to dt clk definition (see patch 36 to 50).
These definition are kept for all non-dt boards (see in
arch/arm/mach-at91/board-xxx.c).
This will be cleaned as soon as all non-dt boards are moved to dt.
>
> Or have you looked into using of_clk_get?
If I remember correctly, the clk_get function first tries to get the clk
from dt binding.
Then if it fails it uses the clk_lookup info. Am I right ?
If so, I don't need to use of_clk_get in drivers calling clk_get with a
non NULL device
parameter.
The only place where I use of_clk_get is in init timer driver
(at91sam926x_time.c).
I first try to retrieve the clk from dt, then if it fails (or if dt is
not supported),
I use clk_get with a NULL device param, which will lead to clk_lookup
search.
Tell me if I misunderstood the API.
>
> Regards,
> Mike
Best Regards,
Boris